1 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part II Iowa State...

1 - ECpE 583 (Reconfigurable Computing): Placing Applications onto FPGAs, Part IIIowa State University (Ames)

ECpE 583Reconfigurable ComputingLecture 21: Thur 11/06/2008

(Placing Applications onto FPGAs: Part II)

Instructor: Dr. Phillip Jones([email protected])

Reconfigurable Computing LaboratoryIowa State University

Ames, Iowa, USAhttp://www.ece.iastate.edu

http://class.ece.iastate.edu/cpre583 (coming soon)http://www.arl.wustl.edu/~phjones/cpre583 (temporary)


• Updated schedule (coming soon)• MP2 concerns

Class Announcements


• Placing an application on an FPGA– Low-level details

Outline


Applications on FPGA

• Low-level: Application to FPGA refs– Reconfigurable Computing (2008)

• Scott Hauck, Andre DeHon– The VLSI handbook (2000)

• Wai-Kai Chen (note: there’s a 2nd edition (2006))– Combinational Logic Synthesis for LUT Based

Field Programmable Gate Arrays• Jason Cong (TODAES’96)


Applications on FPGA: Low-level

• Implement circuit in VHDL (Verilog)• Simulate compiled VHDL• Synthesis VHDL into a device independent format• Map device independent format to device specific

resources– Check that device has enough resources for the design

• Place resources onto physical device locations• Route (connect) resources together

– Completely routed– Circuit meets specified performance

• Download configuration file (bit-steam) to the FPGA



Implement

Simulate

Synthesize

Map

Place

Route

Download


Implement Design

• Several methods of design entry– HDL: VHDL, Verilog– Higher level languages: HandleC– Schematic Capture



Implement

Simulate

Synthesize

Map

Place

Route

Download


Design Simulation

• Compile Implemented design (e.g. in VHDL) into a format understood by a simulator– vcom: ModelSim’s compiler

• Simulate Design– vsim: ModelSim’s simulator



Implement

Simulate

Synthesize

Map

Place

Route

Download


(Logic) Synthesis

• Technology independent representation– EDIF (Electronic Design Interchange Format)

• Technology independent optimization– Combinational optimization

• 2-level• Multi-level

– Sequential optimization• FSM state reduction• retiming


EDIF representation

• Gives a standard means to target a design to different vendors


Combinational Optimization

• 2-level example


Combinational Optimization

• multi-level example (Berkley MIS)


Sequential Optimization

• State reduction example


Sequential Optimization

• Retiming example


(Technology) Map

• Translate device independent net list to device specific resources– Rule based– Tree based



Implement

Simulate

Synthesize

Map

Place

Route

Download


(Technology) Map

• Rule based example


(Technology) Map

• Tree based example



Implement

Simulate

Synthesize

Map

Place

Route

Download


Place

• Bind each mapped resources to a physical device location– General Purpose

• Clustering• Simulated Annealing• Partition-based

– Structured Guided• Data Path based

– User Guided Layout


Place (General Purpose)

• Places resources without any knowledge of high level structure

• Guided primarily by local connections between resources



• Placement using clustering



• Placement using simulated annealing



• Placement using partitioning


Place (Structured-based)

• Automatically leverage structure of the application– Algorithms my work well for a give structure, but

will likely give unacceptable results for an design with little regular structure.


Place (Structure-based)

• Datapath-based example


Place (User-Guided)

• User provide information about applications structure to help guide placement– Can help remove critical paths– Can greatly reduce amount of time for routing

• Several ways to provide guide information– VHDL directives (e.g. RLOC)– GUI-based (e.g. Xilinx FloorPlanner)


Place (User-Guided)

• User-guided placement example



Implement

Simulate

Synthesize

Map

Place

Route

Download


Route

• Connect placed resources together• Two requirements

– Design must be completely routed– Routed design meets timing requirements

• Widely used algorithm “PathFinder”– PathFinder (FPGA’95)

• McMurchie and Ebeling – Reconfigurable Computing (Chapter 17)

• Scott Hauch, Andre Dehon (2008)


Route (PathFinder)

• PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs (FPGA’95)



Implement

Simulate

Synthesize

Map

Place

Route

Download


Download

• Convert routed design into a device configuration file (e.g. bitfile for Xilinx devices)


Next Lecture

• Compute Models: Part I– Recommended Reading

• Design Patterns for Reconfigurable Computing– http://ic.ese.upenn.edu/abstracts/despat_fccm2004.html


Questions/Comments/Concerns

• Write down– Main point of lecture

– One thing that’s still not quite clear

– If everything is clear, then give an example of how to apply something from lecture

OR

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