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Transcript of 1 - ECpE 583 (Reconfigurable Computing): Map, Place & route Iowa State University (Ames) CPRE 583...
1 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
CPRE 583Reconfigurable ComputingLecture 24: Wed 12/8/2010
(Map, Place & Route)
Instructor: Dr. Phillip Jones([email protected])
Reconfigurable Computing LaboratoryIowa State University
Ames, Iowa, USA
http://class.ee.iastate.edu/cpre583/
2 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
• HW3: finishing up (hope to release this evening) will be due Fri12/17 midnight.
• Two lectures left– Fri 12/3: Synthesis and Map– Wed 12/8: Place and Route
• Two class sessions for Project Presentations – Fri 12/10– Wed 12/15 (9 – 10:30 am)
• Take home final given on Wed 12/15 due 12/17 5pm
Announcements/Reminders
3 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Initial Project Proposal Slides (5-10 slides)
• Project team list: Name, Responsibility (who is project leader)– Team size: 3-4 (5 case-by-case)
• Project idea• Motivation (why is this interesting, useful)• What will be the end result• High-level picture of final product
• High-level Plan– Break project into mile stones
• Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip.
– System block diagrams– High-level algorithms (if any)– Concerns
• Implementation• Conceptual
• Research papers related to you project idea
4 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
• FPL• FPT• FCCM• FPGA• DAC• ICCAD• Reconfig• RTSS• RTAS• ISCA
Projects Ideas: Relevant conferences
• Micro• Super Computing• HPCA• IPDPS
5 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Initial Project Proposal Slides (5-10 slides)
• Project team list: Name, Responsibility (who is project leader)• Project idea
• Motivation (why is this interesting, useful)• What will be the end result• High-level picture of final product
• High-level Plan– Break project into mile stones
• Provide initial schedule: I would initially schedule aggressively to have project complete by Thanksgiving. Issues will pop up to cause the schedule to slip.
– System block diagrams– High-level algorithms (if any)– Concerns
• Implementation• Conceptual
• Research papers related to you project idea
6 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Final Project Presentation (12-15 slides)
• Project team list: Name, Responsibility (who is project leader)• Project idea
• Motivation (why is this interesting, useful)• High-level picture of final product
• Implementation– System block diagrams– High-level algorithms (if any)
• Lessons learned– Design issue realizations– Implementation issues
• Research papers related to you project idea
7 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Weekly Project Updates
• The current state of your project write up– Even in the early stages of the project you
should be able to write a rough draft of the Introduction and Motivation section
• The current state of your Final Presentation– Your Initial Project proposal presentation
(Due Fri 10/22). Should make for a starting point for you Final presentation
• What things are work & not working• What roadblocks are you running into
8 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
• Teams Formed and Idea: Mon 10/11– Project idea in Power Point 3-5 slides
• Motivation (why is this interesting, useful)• What will be the end result• High-level picture of final product
– Project team list: Name, Responsibility• High-level Plan/Proposal: Fri 10/22
– Power Point 5-10 slides• System block diagrams• High-level algorithms (if any)• Concerns
– Implementation– Conceptual
• Related research papers (if any)
Projects: Target Timeline
9 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
• Work on projects: 10/22 - 12/8– Weekly update reports
• More information on updates will be given• Presentations: Last Wed/Fri of class
– Present / Demo what is done at this point– 25-30 minutes (depends on number of projects)
• Final write up and Software/Hardware turned in (Fri: 12/17).
Projects: Target Timeline
10 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Project Grading Breakdown
• 50% Final Project Demo• 30% Final Project Report
– 30% of your project report grade will come from your 5-6 project updates. Friday’s midnight
• 20% Final Project Presentation
11 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
• Mapping a synthesized circuit to FPGA components
• Placing components on the FPGA
• Routing: connecting components
Outline
12 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Applications on FPGA: Low-level
• Implement circuit in VHDL (Verilog)• Simulate compiled VHDL• Synthesis VHDL into a device independent format• Map device independent format to device specific
resources– Check that device has enough resources for the design
• Place resources onto physical device locations• Route (connect) resources together
– Completely routed– Circuit meets specified performance
• Download configuration file (bit-steam) to the FPGA
13 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Applications on FPGA: Low-level
Implement
Simulate
Synthesize
Map
Place
Route
Download
14 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
(Technology) Map
• Translate device independent net list to device specific resources
15 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
(Technology) Map
• Translate device independent net list to device specific resources
16 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
(Technology) Map
• Translate device independent net list to device specific resources
17 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
(Technology) Map
• Translate device independent net list to device specific resources
18 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Applications on FPGA: Low-level
Implement
Simulate
Synthesize
Map
Place
Route
Download
19 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place• Bind each mapped resource to a physical
device location– User Guided Layout (Chapter 16:Reconfigurable Computing)
– General Purpose (Chapter 14:Reconfigurable Computing)
• Simulated Annealing• Partition-based
– Structured Guided (Chapter 15:Reconfigurable Computing)
• Data Path based
• Heuristics used– No efficient means for finding an optimal solution
20 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (High-level)
Netlist from technology mapping
in A in B in C
LUTD RAM
E
DFFF
DFFGclk
out
21 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (High-level)
Netlist from technology mapping
in A in B in C
LUTD RAM
E
DFFF
DFFGclk
out
FPGA physical layout
I/O I/O I/O I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O I/O I/O I/O
I/O
I/O
I/O
I/O
I/O
I/O
LUT
LUTBRAM
BRAM
LUT
LUT
LUT
LUT
LUT
LUT
22 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (High-level)
FPGA physical layout
clk in C out I/O
In A
In B
I/O
I/O
I/O
I/O
I/O I/O I/O I/O
I/O
I/O
I/O
I/O
I/O
I/O
LUT
DE
BRAM
G
F
LUT
LUT
LUT
LUT
LUT
LUT
Netlist from technology mapping
in A in B in C
LUTD RAM
E
DFFF
DFFGclk
out
23 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place
• User Guided Layout (Chapter 16:Reconfigurable Computing
• General Purpose (Chapter 14:Reconfigurable Computing)
– Simulated Annealing– Partition-based
• Structured Guided (Chapter 15:Reconfigurable Computing)
– Data Path based
24 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (User-Guided)
• User provide information about applications structure to help guide placement– Can help remove critical paths– Can greatly reduce amount of time for routing
• Several methods to guide placement– Fixed region– Floating region– Exact location– Relative location
25 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (User-Guided): Examples
Fixed region
LUTD
DFFF
DFFG
Part ofMap Netlist
FPGA
26 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (User-Guided): Examples
Fixed region
LUTD
DFFF
DFFG
Part ofMap Netlist
FPGA
SDRAM
27 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (User-Guided): Examples
Floating region
FPGA
SoftcoreProcessor
28 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (User-Guided): Examples
LUTD
DFFF
DFFG
Part ofMap Netlist
FPGA
LUT
LUTBRAM
BRAM
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
Exact Location
29 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (User-Guided): Examples
Exact Location
LUTD
DFFF
DFFG
Part ofMap Netlist
FPGA
LUT
LUTBRAM
BRAM
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT G
D
LUT
F
LUT
LUT
LUT
LUT
30 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (User-Guided): Examples
LUTD
DFFF
DFFG
Part ofMap Netlist
FPGA
LUT
LUTBRAM
BRAM
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
Relative Location
G
D F
31 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (User-Guided): Examples
LUTD
DFFF
DFFG
Part ofMap Netlist
FPGA
LUT
LUTBRAM
BRAM
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
Relative Location
G
D F
32 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (User-Guided): Examples
LUTD
DFFF
DFFG
Part ofMap Netlist
FPGA
LUT
LUTBRAM
BRAM
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
Relative Location
G
D F
33 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place
• User Guided Layout (Chapter 16:Reconfigurable Computing
• General Purpose (Chapter 14:Reconfigurable Computing)
– Simulated Annealing– Partition-based
• Structured Guided (Chapter 15:Reconfigurable Computing)
– Data Path based
34 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (General Purpose)
• Characteristics:– Places resources without any knowledge of high
level structure– Guided primarily by local connections between
resources
• Drawback: Does not take explicit advantage of applications structure
• Advantage: Typically can be used to place any arbitrary circuit
35 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (General Purpose)
• Preprocess Map Netlist using Clustering– Group netlist components that have local
conductivity into a single logic block
• Clustering helps to reduce the number of objects a placement algorithm has to explicitly place.
36 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (General Purpose)
• Placement using simulated annealing– Based on the physical process of annealing
used to create metal alloys
37 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (General Purpose)
• Simulated annealing basic algorithm
Placement_cur = Inital_Placement;T = Initial_Temperature;
While (not exit criteria 1) While (not exit criteria 2)
• Placement_new = Modify_placement(Placement_cur)1. ∆ Cost = Cost(Placement_new) – Cost(Placement_cur)2. r = random (0,1);3. If r < e^(-∆Cost / T), Then Placement_cur = Placement_new
End loop T = UpdateTemp(T);End loop
38 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (General Purpose)
• Simulated annealing: IllustrationFPGA
LUT
LUTBRAM
BRAM
A
LUT
B
LUT
LUT
LUT
LUT
X
LUT
Z
LUT
LUT
LUT
LUT
G
D F
39 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (General Purpose)
• Simulated annealing: IllustrationFPGA
LUT
LUTBRAM
BRAM
LUT
LUT
B
A
LUT
D
LUT
LUT
LUT
Z
G
X
LUT
LUT
LUT
LUT F
40 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (General Purpose)
• Simulated annealing: IllustrationFPGA
LUT
LUTBRAM
BRAM
A
LUT
B
LUT
LUT
LUT
LUT
X
LUT
Z
LUT
LUT
LUT
LUT
G
D F
41 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (General Purpose)
• Simulated annealing: IllustrationFPGA
LUT
LUTBRAM
BRAM
LUT
A
B
LUT
LUT
LUT
LUT
X
LUT
Z
LUT
LUT
LUT
LUT
G
D F
42 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (General Purpose)
• Simulated annealing: IllustrationFPGA
LUT
LUTBRAM
BRAM
LUT
A
B
LUT
LUT
LUT
LUT
LUT
X
Z
LUT
LUT
LUT
LUT
G
D F
43 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place
• User Guided Layout (Chapter 16:Reconfigurable Computing
• General Purpose (Chapter 14:Reconfigurable Computing)
– Simulated Annealing– Partition-based
• Structured Guided (Chapter 15:Reconfigurable Computing)
– Data Path based
44 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (Structured-based)
• Leverage structure of the application
• Algorithms my work well for a give structure, but will likely give unacceptable results for an design with little regular structure.
45 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Structure high-level example
46 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Applications on FPGA: Low-level
Implement
Simulate
Synthesize
Map
Place
Route
Download
47 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route
• Connect placed resources together• Two requirements
– Design must be completely routed– Routed design meets timing requirements
• Widely used algorithm “PathFinder”– PathFinder (FPGA’95)
• McMurchie and Ebeling – Reconfigurable Computing (Chapter 17)
• Scott Hauch, Andre Dehon (2008)
48 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route: Route FPGA Circuit
49 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder)
• PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs (FPGA’95)
• Basic PathFinder algorithm– Based closely on Djikstra’s shortest path
• Weights are assigned to nodes instead of edges
50 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder): Example
• G = (V,E)– Vertices V: set of nodes (wires)– Edges E: set of switches used to connect wires– Cost of using a wire: c_n = (b_n + h_n) * p_n
S1 S2 S3
D1 D2 D3
A B C
1
1
1
11
14 3
34
3
3
2
2
51 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder): Example
• Simple node cost cn = bn
– Obstacle avoidance• Note order matters
S1 S2 S3
D1 D2 D3
A B C
1
1
1
11
14 3
34
3
3
2
2
52 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder): Example
• cn = b * p– p: sharing cost (function of number of signals
sharing a resource)– Congestion avoidance
S1 S2 S3
D1 D2 D3
A B C
1
1
1
11
14 3
34
3
3
2
2
53 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder): Example
• cn = (b + h) * p– h: history of previous iteration sharing cost– Congestion avoidance
S1 S2 S3
D1 D2 D3
A B C
2
21
1 1
1
2
2
1
1
54 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder): Example
• cn = (b + h) * p– h: history of previous iteration sharing cost– Congestion avoidance
S1 S2 S3
D1 D2 D3
A B C
2
21
1 1
1
2
2
1
1
55 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder): Example
• cn = (b + h) * p– h: history of previous iteration sharing cost– Congestion avoidance
S1 S2 S3
D1 D2 D3
A B C
2
21
1 1
1
2
2
1
1
56 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder): Example
• cn = (b + h) * p– h: history of previous iteration sharing cost– Congestion avoidance
S1 S2 S3
D1 D2 D3
A B C
2
21
1 1
1
2
2
1
1
57 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder): Example
• cn = (b + h) * p– h: history of previous iteration sharing cost– Congestion avoidance
S1 S2 S3
D1 D2 D3
A B C
2
21
1 1
1
2
2
1
1
58 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder): Example
• cn = (b + h) * p– h: history of previous iteration sharing cost– Congestion avoidance
S1 S2 S3
D1 D2 D3
A B C
2
21
1 1
1
2
2
1
1
59 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Route (PathFinder): Example
• cn = (b + h) * p– h: history of previous iteration sharing cost– Congestion avoidance
S1 S2 S3
D1 D2 D3
A B C
2
21
1 1
1
2
2
1
1
60 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Applications on FPGA: Low-level
Implement
Simulate
Synthesize
Map
Place
Route
Download
61 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Download
• Convert routed design into a device configuration file (e.g. bitfile for Xilinx devices)
62 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Next Lecture
• Project presentations
63 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Questions/Comments/Concerns
• Write down– Main point of lecture
– One thing that’s still not quite clear
– If everything is clear, then give an example of how to apply something from lecture
OR
64 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
Place (Structured-based)
• Leverage structure of the application– Algorithms my work well for a give structure, but will likely
give unacceptable results for an design with little regular structure.
• GLACE “A Generic Library for Adaptive Computing Environments” (FPL 2001)– Is an example tool that takes the structure of an application
into account.• FLAME (Flexible API for Module-based Environments)• JHDL (From BYU)• Gen (From Lockheed-Martin Advanced Technology
Laboratories)
65 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
GLACE: High-level
66 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
GLACE: Flow
67 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
GLACE: Library Modules
68 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
GLACE: Data Path and Control Path
69 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
GLACE: FLAME low-level
70 - ECpE 583 (Reconfigurable Computing): Map, Place & routeIowa State University (Ames)
GLACE: Final placement example