Post on 31-Mar-2018
International Journal of Electronics Engineering Research.
ISSN 0975-6450 Volume 9, Number 8 (2017) pp. 1171-1184
© Research India Publications
http://www.ripublication.com
Power Optimized Dadda Multiplier Using Two-Phase
Clocking Sub-threshold Adiabatic Logic
Jayaram Bevara
Department of Electronics & Communication Engineering, Gudlavalleru Engineering College, Gudlavalleru, A.P. - 521356,
Tilak V.N.Alapati *
Department of Electronics & Communication Engineering, Gudlavalleru Engineering College, Gudlavalleru, A.P. - 521356, India *Corresponding author
Srilakshmi Kaza
Department of Electronics & Communication Engineering, Gudlavalleru Engineering College, Gudlavalleru, A.P. - 521356, India
Abstract
With increasing demand for portable and battery operated devices, design of
low power circuits is gaining importance. Multiplier is an important building
block in applications such as digital signal processing, communication systems
and arithmetic logic units. In this work, a 4-bit Dadda multiplier with
Brent-Kung adder using Two-Phase Clocking Sub-threshold Adiabatic Logic
(2PCSAL) is implemented. The designed circuits are simulated by Mentor
Graphics tool using TSMC 180 nm CMOS technology. Simulation results
indicate that the power consumption of the 2PCSAL Dadda multiplier is
75.1 % less as compared to that reported for 45 nm technology conventional
CMOS circuit.
Keywords: adiabatic logic, Brent-Kung adder, Dadda multiplier, sub-threshold,
two-phase clocking, ultralow-power
1172 Jayaram Bevara, Tilak V.N.Alapati and Srilakshmi Kaza
1. INTRODUCTION
The requirement for low power chips is increasing day by day due to the demand for
portable consumer electronics powered by batteries. In present modern digital systems
like sensor networks, pace makers, and mobile systems the battery life is precious and
hence ultralow-power consumption is very important [1]. For any digital system,
multipliers and adders are the basic and key components and thus are playing a vital
role in all these systems. Several multiplier and adder circuits have been designed by
many researchers [2-5] to attain low power consumption, lesser area and delay.
Power dissipation in VLSI circuits [6] has two major components: static and dynamic.
The static and the dynamic power are caused by inherent device leakage when the
circuit is in the off state and by charging and discharging of the capacitive nodes
respectively. Several low-power design technologies like adiabatic, sub-threshold, and
multi-threshold have been used to reduce dynamic power, among which adiabatic
logic, a novel low-power circuit structure uses AC supply rather than constant DC to
recycle the energy of circuits. Ideally, adiabatic logic circuits have zero power
consumption without considering the leakage power. Quasi or partial and fully are the
two classifications in adiabatic logic circuits. The quasi type adiabatic logic circuits
suffer with adiabatic losses but have a simple architecture. Complex architecture and
clock synchronization are the major drawbacks of full adiabatic logic circuits [7 - 16].
Threshold voltage of the transistors in sub-threshold based digital circuits is higher
than the supply voltage. These sub-threshold adiabatic logic circuits have good
performance and ultralow-power consumption [17] but the circuit delay is slightly
higher.
Column compression or tree multipliers like Wallace [18] and Dadda [19] are
characterized by high speed. These multipliers are widely used in digital systems for
achieving better performance. Full and half adder circuits are the key components for
the column compression. The Dadda multiplier needs lesser hardware and its speed of
operations is more than the Wallace tree multiplier. The Dadda algorithm
implementation requires an adder circuit to add the final set of partial products. The
conventional adder circuits like carry select adder and ripple carry adders are failed to
give satisfactory results [20]. Hence, we use a parallel prefix adder, such as
Brent-Kung adder. These are unique kind of adders, operated using generate and
propagate signals [21].
The remaining part of the paper is organized as follows: In section 2, the background
of this work is presented. Section 3 describes the implementation of proposed 4-bit
Dadda multiplier using Brent-Kung adder. Simulation results are given in section 4.
Finally, section 5 contains the conclusion of the paper.
Power Optimized Dadda Multiplier Using Two-Phase Clocking… 1173
2. TWO-PHASE CLOCKING SUB-THRESHOLD ADIABATIC LOGIC
2.1 Adiabatic logic
Figure 1 shows a conventional CMOS inverter, in which the load capacitance is
charged through the PMOS transistor when the inverter input is logical low. If input is
logical high, the NMOS transistor is ON, and the load capacitance is discharged to
ground.
The CMOS inverter can be modeled as an RC equivalent circuit as shown in figure
2(a) in which R is the resistance of the PMOS and NMOS transistors, CL is the load
capacitance and Vdd is the DC supply voltage. When the switch is closed current
flows through the resistor R and the load capacitance CL is charged to Q = CLVdd. The
total supplied energy in the charging process is Esupply = QVdd = CLVdd2. At the load
capacitance half of the energy is stored and the remaining energy was consumed.
Hence, the dissipated energy per input transition is given as
Echarge = CL (1)
The total stored charge on load capacitor is dissipated through the NMOS transistor to
ground, during the discharge operation. If Etotal is the total energy consumption due to
the charging and discharging, it can be expressed as
total = Echarge + Edischarge = CL + CL = CL (2)
The adiabatic logic circuits are powered by time changing supply voltage like ramp or
sinusoidal signals as shown in figure 2(b). The voltage drop across the resistor is
small and the energy dissipation during charging and discharging decreases. If the
adiabatic circuit is operated by ramp signal with time period T then the power
P = CLVdd2f, where f = 1/T. In this case the total energy consumption for every
process is
Eadiabatic = (3)
where ξ is the shape factor that depends on clock edges shape, I is the current and R is
the resistance.
Figure 1: Conventional CMOS inverter
1174 Jayaram Bevara, Tilak V.N.Alapati and Srilakshmi Kaza
(a) (b)
Figure 2: Supply voltage and currents in (a) conventional CMOS logic and
(b) adiabatic logic
2.2 Sub-threshold region operation
Sub-threshold region is also known as weak inversion region, where the threshold
voltage Vth is greater than the gate to source voltage Vgs. In sub-threshold operation of
the MOSFET, leakage current occurs at its drain to source region and is expressed as
[22]
T
thgs
nVVV
ds eII
0 (4)
2
0 )1( Tox VnL
WCI (5)
where µ = mobility, Cox= capacitance of gate oxide film, n = slope factor of
sub-threshold region, VT = thermal voltage = kT/q, L= length of the channel and
W = width of the channel. Ids exponentially varies with Vgs. In this region of
operation, though an order of magnitude decrease in power consumption due to small
current compared to the strong inversion region operation is possible, the circuit delay
is high.
2.3 Inverter circuit using 2PCSAL
The circuit topology of two-phase clocking sub-threshold adiabatic logic (2PCSAL)
inverter shown in figure 3 is same as that of conventional static CMOS inverter [23].
The inverter uses a two-phase sinusoidal clocking power supply (Vpa and Vpb) having
different frequencies and amplitudes. It has a pulsed input signal A and output Y as
shown.
Power Optimized Dadda Multiplier Using Two-Phase Clocking… 1175
Figure 3: 2PCSAL inverter circuit
Figure 4: Simulation results of 2PCSAL inverter
Figure 4 shows the simulation results of the 2PCSAL inverter obtained by Mentor
Graphics tool using 180 nm standard CMOS process technology. The frequency and
peak amplitude of supply voltages Vpa, Vpb and the input signal are 1 MHz, 2 MHz,
0.5 MHz and 0.7 V, 0.35 V, 0.7 V respectively. The size L/W of each transistor is
0.35 μm/1.4 μm. The output Y takes on peak values of Vpa and Vpb respectively when
the input A goes low or high as shown in figure 4.
3. 4-BIT DADDA MULTIPLIER IMPLEMENTATION
The block diagram of a 4-bit Dadda multiplier with Brent-Kung adder and
implemented using 2PCSAL is shown in figure 5. A1 to A4 and B1 to B4 are the
1176 Jayaram Bevara, Tilak V.N.Alapati and Srilakshmi Kaza
inputs to the Dadda multiplier. Figure 6 describes the scheme for reduction of the
initial sixteen partial products P1 to P16. The reduction process comprises the
following steps [19].
(i) Partial products are generated by multiplying both the multiplier and multiplicand
bits.
(ii) (2,2) and (3,2) compressors are used to reduce the partial products.
Figure 5: Block diagram of a 4-bit Dadda multiplier with Brent-Kung adder
Figure 6: Partial products reduction scheme in 4-bit Dadda multiplier
Power Optimized Dadda Multiplier Using Two-Phase Clocking… 1177
Figure 7: Schematic circuit for partial products reduction in 4-bit Dadda multiplier
The schematic diagram for partial products reduction in 4-bit Dadda multiplier is
shown in figure 7. The input data (multiplier and multiplicand) is given to the
multiplier. Partial products P1 to P16 are generated using an array of AND gates. The
final set of partial products (P1, P2, P5, P9, S3, C3, S4, C4, S5, C5, S6, C6, P16) is
derived with the help of half adder and full adder circuits.
The final set of partial products is added using Brent-Kung parallel prefix adder of
figure 5. Dadda multiplier employing conventional adders perform serial addition of
reduced partial products, thus leading to more power consumption. To avoid this
problem, the Brent-Kung adder is used at the final stage of addition. P1 is directly
available at the output as S[0] and the remaining partial products are given as inputs
to the Brent-Kung adder. These partial products are added up in parallel in three
stages. The propagate and generate signals are produced using XOR and AND gates
in the initial pre-processing stage. The prefix carry trees simultaneously generate the
carry signals and are added at post-processing stage. S[1] to S[7] are the other final
outputs.
The (2,2) and (3,2) compressors are equivalent to half and full adder circuits
respectively. For the reduction, conventional half adder is used, but the full adder is
optimized by two XNOR gates and one 2×1 multiplexer. The optimized full adder
using 2PCSAL shown in figure 8 has three input bits A, B and Cin to generate sum
and carry. Both sum and carry outputs depends on the intermediate output bit X. The
full adder uses less number of components and hence reduces area and delay as well.
equations (7) and (8) represents the outputs of full adder circuit.
X = A XNOR B (6)
Sum = X XNOR Cin (7)
Carry = X ? A : Cin (8)
1178 Jayaram Bevara, Tilak V.N.Alapati and Srilakshmi Kaza
Figure 8: Optimized full adder using 2PCSAL
Figure 9: Simulation results of optimized full adder using 2PCSAL
Power Optimized Dadda Multiplier Using Two-Phase Clocking… 1179
From the simulation results given in figure 9 , it can be noted that when the input A, B
and Cin bits are high, the peak values of output sum and carry are equal to Vpa and
when the inputs are low, the outputs are equal to Vpb.
3.1 6-bit Brent-Kung adder
The block diagram of a Brent-Kung adder is shown in figure 10. For high speed
binary additions Bren-Kung adder is used. Brent-Kung adder architecture comprises
three stages: pre-processing, prefix carry tree and post-processing.
(i) Pre-processing: Initially propagate and generate bits (equations (9) and (10)) are
generated at pre-processing stage. Since it is a 6-bit module, the pre-processing
stage calculates 6 initial propagate and generate signals.
Propagate = A XOR B (9)
Generate = A AND B (10)
(ii) Prefix carry tree: The signals from the first stage will proceed to this stage and
intermediate and final carry bits are generated using the black and gray cells. Figure
11 depicts the implementation of black cell using 2PCSAL. Black cell computes
single pair of propagate and generate signals from two pairs of generate and propagate
signals.
Propagate = Pi AND Pj (11)
Generate = (Pi AND Gj) OR Gi (12)
The implementation of gray cell is shown in figure 12. This cell generates
intermediate carry signals at the end of prefix carry stage. The carry is given by
Ci-1 = (Pi AND Cin) OR Gi (13)
(iii) Post-processing:
SUM[1] = A[i] XOR B[i] XOR C[i-1]
= P[i] XOR C[i-1] (14)
CARRY = Final MSB bit
The final sum and carry signals as given in equation (14) are generated at the end of
post-processing stage using the prefix carry tree output. The inputs P2, P5, P9, S3, C3,
S4, C4, S5, C5, S6, C6, P16 to the 6-bit Brent-Kung adder using 2PCSAL generate
the outputs S[1] to S[7] as shown in figure 13.
1180 Jayaram Bevara, Tilak V.N.Alapati and Srilakshmi Kaza
Figure 10: Block representation of 6-bit Brent-Kung adder
Figure 11: Black cell schematic using 2PCSAL
Figure 12: Gray cell logic diagram using 2PCSAL
Figure 13: Schematic representation of 6-bit Brent-Kung adder
Power Optimized Dadda Multiplier Using Two-Phase Clocking… 1181
4. SIMULATION RESULTS
The results of the two-phase clocking sub-threshold adiabatic logic based 4-bit Dadda
multiplier simulated with Mentor Graphics tool using TSMC 180 nm CMOS
technology are shown in figure 14. A1 to A4 are the multiplicand bits, B1 to B4 are
the multiplier bits, and S[0] to S[7] are the outputs. For example if A1, B1, A2, B2 are
equal to logical zero and A3, B3, A4, B4 are equal to logical one, then the peak values
of S[4] and S[7] are Vpa and the remaining output signals are equal to Vpb.
The power consumed by the circuit found to be 20.14 μW and is much lower than the
value 81 μW reported for the conventional multiplier circuit implemented using 45nm
technology [24].
Figure 14: Simulation results of 4-bit Dadda multiplier
1182 Jayaram Bevara, Tilak V.N.Alapati and Srilakshmi Kaza
5. CONCLUSION
In this work a 4-bit Dadda multiplier with parallel prefix Brent-Kung adder for
summing up the final set of partial products is implemented using two-phase clocking
sub-threshold adiabatic logic in TSMC 180nm CMOS technology. The simulation
results indicate that a power reduction of 75.1% is achieved with the designed
multiplier as compared to the value reported for 45nm technology static CMOS
circuit. The proposed adiabatic logic circuit is advantageous for the design of
ultralow-power digital circuits.
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1184 Jayaram Bevara, Tilak V.N.Alapati and Srilakshmi Kaza
BIOGRAPHICAL SKETCH OF AUTHORS:
Jayaram Bevara was born on 25th June 1993 in Andhra Pradesh,
India. He received his B.Tech degree in 2014 in Electronics and
Communication Engineering and M.Tech degree in 2016 in
Embedded Systems from Jawaharlal Nehru Technological
University Kakinada, Kakinada. His area of interest is Low Power
VLSI.
A. V. N. Tilak has obtained his B.E, M.Tech, and Ph.D from MIT
Manipal, IIT Kanpur, and IIT Madras respectively. His areas of
interest are Microelectronics, Digital Design, and Low Power
VLSI Design. Dr. Tilak is a member of IEEE, Fellow IETE,
Fellow IE(I), and Life member of ISTE.
Srilakshmi. K obtained her B.Tech in Electronics and
Communication Engineering and M.Tech in VLSI System
Design from Jawaharlal Nehru Technological University
Kakinada, Kakinada in 2009 and 2011 respectively. At present
she is pursuing Ph.D from JNTUH, Hyderabad. Her research
interests include Low power VLSI and Embedded design.