Post on 05-Apr-2015
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 1 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Part 7
Instruction Set Architecture(ISA)
Computer Architecture
Slide Sets
WS 2011/2012
Prof. Dr. Uwe BrinkschulteProf. Dr. Klaus Waldschmidt
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 2 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Programming model
The Instruction Set Architecture (ISA) is the programming model
which is needed for programming a processor.
All details concerning the implementation of the processor are out of
focus in the ISA.
Therefore the ISA can be regarded as an abstract interface between
the compiler and the microarchitecture of the processor.
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 3 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Programming model
The following key questions lead us to the specification of this
interface:
• How data is represented?
• Where data is stored?
• How data is accessed?
• How instructions are coded?
• Which instructions are available to process data?
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 4 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Programming model
Therefore, the ISA defines:
• machine data types
• address space organisation
• register model
• addressing modes
• machine instruction set
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 5 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Programming model
Since the programming model abstracts from implementation details it is
realized either in hardware (real processors) or in software (virtual
processors).
For instance, if the instruction set includes an instruction for multiplication,
the CPU of the processor needs a digital combinatorial circuit for
multiplication.
In this sense, a relation between the abstract ISA and the
microarchitecture exists.
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 6 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Machine data types
A data type is a tuple of values and operations which can be
performed on these values.
The operations are implemented by the machine instructions.
Machine data types (like data types in high level languages)
are classified into structured and unstructured data types.
An additional class are the primitive data types.
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 7 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Primitive machine data types
Bit: value set: 0,1operations: AND, OR, XOR, negation, compare
Byte: value set: bit pattern (8 bit)normally smallest addressable unit operations: same as for bit, additionally ADD, SUB, MUL, DIV, SHIFT, ROTATE, …
Word: value set: normally a multiple of byteslargest addressable unit (in a single operation)operations: same as for byte
(sometimes the following convention is used: Half-Word = 16 BitWord = 32 BitDouble Word = 64 Bit)
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 8 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Examples for more data types
1
- vector (bit)
- BCD number (binary coded decimal)
- Binary number unsigned
- two complement number
- floating point number
- string
n-1 i 0
n = 8,16,32
0 3 2 1 0
7 6 5 4 3 2 1 0
8, 16 Bit
32 Bit31 0
7 0 15 0
n-1 0n = 8, 16, 32
MSB LSB
n-1 0
MSB=sign bit LSB
n = 8, 16, 32
biased.expon.s fraction
... n = 8, 16, 32n-1 0 n-1 0 n-1 0
31 23 22 0
(taken from MC680x0)
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 9 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Address space organisation
Physical organisation:
depends on the processor
. . .
7 0
0
n
8 bit processor
. . .
15 8 7 0
0
n
16 bit processor
. . . . . .
31 24 23 16 15 8 7 0
0
n
32 bit processor
. . . . . . . . .
n: physical address, n = 2 address bus width
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 10 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Address space organisation
Locical organisation:
byte oriented access for most processor types
. . .
7 0
0
1
2
3
m
physical word on a 8 bit processorphysical word on a 16 bit processorphysical word on a 32 bit processor
m: logical address, m = n * bit width / 8
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 11 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Address space organisation
Physical to logical mapping:
. . .
31 24 23 16 15 8 7 0
0
n
. . . . . . . . .
0123
456789101112131415
m-3m-2m-1m
physical address
locical address
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 12 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Address space organisation
Aligned access: the accessed word is aligned according to its length in the physical address space
(logical adress mod length) = 0
. . .
31 24 23 16 15 8 7 0
0
n
. . . . . . . . .
bytebytebytebyte bytes to byte boundarieshalf-wordhalf-word half-words to half-word boundaries
word words to word boundaries
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 13 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Address space organisation
. . .
31 24 23 16 15 8 7 0
0
n
. . . . . . . . .
half-word
-word
word
Unaligned (misaligned) access: the accessed word is not aligned according to its length in the physical address space
(logical adress mod length) 0
half-
Some processors do not support unaligned access (e.g. SPARC)
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 14 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Byte order in words
8 Bit - byte
16 Bit - word
32 Bit - word
8 Bit - byte
16 Bit - word
32 Bit - word
N + 1N N + 2 N + 3
N + 1N
N
N + 1 NN + 2N + 3
N + 1 N
N
big endian byte ordering
little endian byte ordering
31 24 23 16 15 8 7 0
31 24 23 16 15 8 7 0
Two different formats:
N: least significant byte, N + 3: most significant byte
Word address is the address of the most significant byte (used e.g. in MC680x0 or SPARC)
Word address is the address of the least significant byte (used e.g. in Pentium family)
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 15 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Byte order in words
N + 1
N
N + 2N + 3big endian byte ordering
Locical (byte oriented) memory organization of a 32 bit word
b
b+1
b+2
b+3
byte address
N + 2
N + 3
N + 1Nlittle endian byte ordering b
b+1
b+2
b+3
byte address
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 16 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Register model
The number of registers being part of a processor varies between 20
and 200. The advantage of data storage in registers against DRAM
or SRAM-memories are:
• faster access time
• register addresses could be shorter with respect to the instruction
format.
An ISA is called Load-Store-ISA if all machine instructions except
register load and store instructions operate on the register file only.
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 17 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Registers are classified into hidden registers and programmer visible
registers.
The visible registers are the workplace of the programmer and are
often organized as register files.
Hidden registers are supply registers needed for the internal
functionality of the processing unit (CPU).
Both visible and hidden registers are designed for various purpose
and functionality.
Register model
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 18 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
A register model defines which processor registers are visible
(addressable) to the programmer.
Usually these are the working registers and the state register.
The state register monitors the state of the processor through
conditional flags.
It shows for example whether the processor operates in system or user
mode.
The state register is mostly read-only
Commonly existing hidden registers are the instruction register and the
memory interface registers.
Register model
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 19 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Register implementation
clk
Q0
D Q
D0
Q1
D Q
D1
Q31
D Q
D31
........
32 bit registerwith D-Latches
Asynchronouscounter withD-Latches
D Q
Q
clk D Q
Q
D Q
Q
D Q
Q
Q0 Q2Q1 Q3
....
clk
D31
Q31
D1
D0 Q0
Q1
Symbol
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 20 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
• program counter (PC) - contains the next instruction address
• state register (SR) - monitors the state of the processor
• stackpointer (SP) - stores the top of the stack
• accumulator (ACCU) – stores computation results (in older or simple
processors)
• data registers (DXi) - storing operands for computations
• address registers (AXi) - storing operand addresses
• general purpose registers (GPi) - storing either operands or operand
addresses
Common visible registers
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 21 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
• instruction register (IR) – contains the currently processed instruction
• instruction queue (IQ) - contains the next instructions to be processed
• memory address register (MAR) - buffers the address of a
memory
access (e.g. to save or load
a general purpose register)
• memory data register (MDR) - buffers the content of a memory access
(e.g. to save or load a general
purpose register)
Common hidden registers
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 22 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Program counter register
Pointer to the next instruction to be executed
Normally incremented
Set by a jump, jump subroutine, interrupt, return or return from interrupt instruction
Program counter
PC
N - 4
N
N + 4
M
……
31 0
Add
A
B
Jump
M
…
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 23 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Stackpointer register
Addresses a location in the memory which is organized as a stack (LIFO).
Elements can be pushed (write) and popped (read) only from the top of the stack.
Consequence: Data are stored in a subsequent order
Used e.g. for jump subroutine/return operation on PC
StackpointerN - 4
N
N + 4…
…
31 0
Push X
Pop
Some processors distinguish between user stackpointer (e.g. for jump subroutine/return) and supervisor stackpointer (e.g. for interrupt/return from interrupt)
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 24 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Sampe CISC register set
Intel Pentium
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 25 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Sampe RISC register set
Power PC (extract)
The register file of RISC processors has to be much
bigger compared to CISC processors.
A RISC needs more registers, because the register
file is source and destination of all arithmetic or logic
instructions.
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 26 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Multiple register sets
Register set n
Program counter content
State register content
Data-/address-register 1
Data-/address-register 2
Data-/address-register m
. . .
Register set 3
Register set 2
Register set 1
. . .
register set structure
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 27 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Processors with multiple register sets: a step towards multithreaded processors
Processor with multiple register sets:
Each register set can store the program counter (PC) and the state register (SR)
PC and SR exist only once
=> several contexts can be stored, fast context switching
Multithreaded processor:
multiple PCs and SRs exist
instructions from several threads can be executed at the same time in the pipeline
=> several contexts can be processed
Multiple register sets
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 28 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
The registers of a register file are grouped into blocks called windows.
These overlapping windows are used by the subroutines of a program.
MORS (multiple overlapping register set)
Multiple overlapping register sets,register windows
Overall register set
Register window 1
Register window 2
Register window 3
Register window n
jump subroutine
return
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 29 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Simplifies parameter passing on jumping to subroutines
Each subroutine has its own working space within the register file
Parameters can be directly passed with no need to copy registers or
pass parameters by memory
=> mainly used in RISC processors
Two possible approaches:
• Fixed size register window
• Variable size register window
Multiple overlapping register sets,register windows
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 30 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
precedingwindow
continued
continued
global registers
r7
r0
current window
succeedingwindow
CWP
restore
save
alternative register naming:
r31 = i7
r24 = i0r23 = I7
r16 = I0r15 = o7
r8 = o0r7 = g7
r0 = g0
based on SPARC architecture
r31
r24r23
r16r15
r8
r31
r31
r8
r8
In i+1
Local i+1
Out i+1 In i
Local i
Out i
Out i-1
Local i-1
In i-1
Fixed size window
local register
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 31 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
In case of the SPARC architecture, a window consists of 32 registers of which the first 8 also belong to the preceding window and the last 8 also belong to the succeeding window.
The registers are addressed relative to the current window pointer (CWP).
A subroutine call is performed by incrementing the CWP and saving the PC.
The parameters are passed through the overlapping registers of the two windows.
The content of the program counter is saved (return address) into one of these registers.
A time consuming save and reload of registers is omitted.
In case of an overflow of the MORS the window contents have to be saved to a stack.
Fixed size window
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 32 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
In
Local
Out
Local
Out
preceding
currentwindow
globalregisters
localregisters
0
63
127
0 previous RSP
current RSP
r0r1
r0r1
Variable size window
gr0gr1
gr63
register stack pointer (RSP)
r0
r1
r127
r65
r66
r64 based on AMD 29000 architecture
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 33 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Register size of processors with 3-address architecture
processor/architecture (vendor)
# of general purpose registers bit width
overalldirectlyaccessible
register width
registeraddress
immediateoperands
instr.
Alpha 21364 (Compaq) 32 32 64 Bit 5 Bit 8 Bit 32 BitAm29000 (AMD) 192 192 32 Bit 8 Bit 8 Bit 32 BitARM7TDMI (ARM) 16 16 32 Bit 4 Bit 8 Bit 32 BitCrusoe TM5800 (Transmeta) 64 64 32 Bit 6 Bit - -pa-8700 (HP) 32 32 64 Bit 5 Bit 11 Bit 32 BitItanium 2 (Intel, HP) 128 128 64 Bit 7 Bit 8 Bit 41 BitMC88100 (Motorola) 32 32 32 Bit 5 Bit 16 Bit 32 BitMIPS65 20Kc (MIPS) 32 32 64 Bit 5 Bit 16 Bit 32 BitNemesis C (TU Berlin) 96 16 32 Bit 4 Bit 1 Bit 16 BitPowerPC 970 (IBM) 32 32 64 Bit 5 Bit 16 Bit 32 BitUltraSPARC III Cu (SUN) 160 32 64 Bit 5 Bit 13 Bit 32 Bit
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 34 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Register size of processors with 2-address architecture
processor (vendor)
# of general purpose registers bit width
overalldirectly accessible
register width
register address
immediate operands
smallest instr.
Athlon (AMD X86-64) 16 16 64 Bit 4 Bit 8 - 32 Bit 8 Bit
ColdFire MFC5206 (Motorola) 8 + 8 8 + 8 32 Bit 3 Bit 8 - 32 Bit 16 Bit
MC680xx (Motorola) 8 + 8 8 + 8 32 Bit 3 Bit 8 - 32 Bit 16 Bit
Pentium X (Intel X86) 8 8 32 Bit 3 Bit 8 - 32 Bit 8 Bit
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 35 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Addressing modes
Machine instructions normally hold information about the operand
addresses.
This can either be a physical address, e.g. a register number or the
address of a memory location, or it can be an address specification.
An address specification defines how to calculate the address.
Thus, the address information determines the location of the
operand(s) belonging to the instruction using one of many addressing
modes.
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 36 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Addressing modes
Instruction format
e.g. arithmetic instruction
opcode
target source source
operands needed for the execution defined by the opcode
operand register memory address specificationitself number location (dynamic address calculation)
The result of the dynamic address calculation is called effective address
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 37 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
• immediate:
The operand is part of the instruction.
• memory direct and register direct:
The instruction contains the operand address.
• register indirect:
The instruction contains a register number pointing to a register
holding the address of the operand.
In assembler code this addressing mode is typically denoted by
register name
Addressing modes
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 38 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
• memory indirect:
A register addressed in the instruction contains the address of a
memory cell which holds the operand address.
• register offset:
The instruction contains a register number and an offset.
The operand address is the sum of the register’s content and the offset.
• implicit:
The instruction implicitly targets a single register (like the ACCU)
Addressing modes
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 39 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Reasons for using dynamic address calculation:
• Addresses of data structure elements are composed of the
first
address of the data structure and the offset of the element to the
beginning. Often this offset is unknown at compile time, therefore
the effective address has to be calculated at runtime.
• Repeated execution of the same instruction, e.g. in a loop,
often accesses successive memory addresses which have to be
calculated at runtime.
Effective address
The address is calculated from several parts found in the instruction and in registers or memory cells at runtime (dynamic address calculation).
The calculated address is defined as effective address.
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 40 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
• An operand address often is unknown at compile time,
because it is calculated during program execution.
• The partitioning of addresses into a base address stored
in a
register and an offset simplifies the handling of shift able
variables and shift able program code.
Effective address (cont.)
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 41 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
o p e r a n d
o p e r a n d
immediate
instruction
instruction
instruction
register
memory
operand
eff. address
eff. address register direct
memory direct
Addressing modes 1
e.g. LOAD 8, r1
e.g. LOAD (2000), r1
e.g. LOAD r2, r1
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 42 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
o p e r a n d
o p e r a n d
register indirectinstruction
register
instruction
registeraddress
e f f e c t i v e a d d r e s s
registeraddress
memory
m e m o r y a d d r e s s
decrement
memory
- eff. address
register
register indirectwith predecrement
Addressing modes 2
e.g. LOAD (r2), r1
e.g. LOAD -(r2), r1
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 43 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
register indirect with displacement(indexed)
o p e r a n d
instruction
register
registeraddress
m e m o r y a d d r e s s
memory
+
+ i n d e xregister
displacement
scaling 1, 2 or 4
eff. address
Addressing modes 3
e.g. LOAD.B 126(r3)(r2), r1
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 44 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
memory indirect
o p e r a n d
instruction
register
registeraddress
m e m o r y a d d r e s s
memory
+
+
displacement1
indirect memory address
displacement2eff. address
memory
Addressing modes 4
e.g. LOAD 28(126(r2)), r1
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 45 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
memory indirect(post indexed)
o p e r a n d
instruction
register
registeraddress
m e m o r y a d d r e s s
memory
+
+
displacement1
indirect memory address
displacement2
eff. address
memory
i n d e x
scaling 1, 2 or 4
+register
Addressing modes 5
e.g. LOAD.B 28(r3)(126(r2)), r1
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 46 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
memory indirect(preindexed)
o p e r a n d
instruction
register
registeraddress
m e m o r y a d d r e s s
memory
+
+
displacement1
indirect memory address
displacement2eff. address
memory
i n d e x
scaling 1, 2 or 4
+register
Addressing modes 6
e.g. LOAD.B 28(126(r3)(r2)), r1
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 47 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
branch target table accessthrough program counter relative addressing
JMP disp (PC)(rn)
memory
target 0
target 2
target 1
• • •
i n d e x
(PC)
+
+
displacement
Access to branch target table by PC relative addressing
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 48 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Machine instruction set
The machine instruction set of a computer normally includes
instructions of different formats, e.g. 0-address instructions, 1-address
instructions, 2-address instructions and 3-address instructions.
An instruction is divided into so called fields.
The more address fields an instruction contains the smaller the
number of addressable memory cells and/or the number of operations
encoded in the opcode field becomes
(if we assume a constant instruction length).
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 49 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Variable length vs. constant length instruction format
Variable length: (e.g. 16 - 256 Bit) mostly used in CISC architectures
+ flexible instruction format
+ high code density
+ long immediate and displacement values
Constant length: (e.g. 32 Bit) mostly used in RISC architectures
+ simple and fast fetch
+ simple and fast decode
+ simplified pipelining
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 50 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Scheme of basic operations of common processors
basic operations
unconditional operations conditional operations
combinatorial operations control flow operations
transportoperations
arithmetic logicoperations
simple branches system branches
load operations
store operations
semaphore operations
arithmetic operations
logic and shift operations
state and control operations
subroutine branches
call call
return return
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 51 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Instruction sets are divided into groups combining instructions with similar functionality:
Typical instruction groups:
• transport instructions
• arithmetic instructions
• logic instructions
• shift and rotate instructions
• bitwise instructions
• string and array instructions
• branch instructions
• system instructions
• synchronization instructions
Instruction classes
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 52 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Load store architecture
All instructions - except load and store instructions - address registers only.
Load and store instructions are needed to transfer data to and from main memory.
Mainly used in RISC ISA, combined with pipelining it allows to complete most instructions in one cycle
Furthermore, the address fields of instructions becomes shorter as they only have to address a register instead of a memory address.
A load store ISA accelerates a machine if there are only small caches or if the caches are completely missing and a big register file is available.
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 53 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Example: An arithmetic instruction
SUBc r3, r7, r21binary code 11010 10101 00111 00011
1 0000000000hexcode D54E3800
31 26 21 16 11 0
instruction format:
OP: opcodeTR: target registerSRn: source registerc/x: set/do not set condition code
Example: A store instruction
STORE r24, 126(r5)binary code 00111 11000 00101
00000000001111110hexcode 3E0A007E
31 26 21 16 0
instruction format:
OP: opcodeSR: source registerBR: base registerDP: displacement (signed)
Two examples for an instruction format
OP TR SR1 SR2 OP SR BRcx DP
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 54 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
State register of a RISC processor (based on SPARC-architecture)
N Z V C
31 16 15 0
IM IE
PS S CWP SR
interruptmask
interrupt enable
previous S-bit
supervisor/user
current windowpointer
carry
overflow
zero
negative
conditional bits
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 55 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Conditional codes dependent on conditional bits Z (zero),N (negative), C (carry) und V (overflow). Mnemonics according toMotorolas ColdFire MFC5206 processor.conditional value mnemonic operation expression operand typeequal
not equal
eq
ne
=
≠
Z
Z independent
higher than
higher than or same
lower than
lower than or same
ht
hs
lo
ls
>
≥
<
≤
C Z
C
C
C Z
unsigned
greater than
greater than or equal
less than
less than or equal
gt
ge
lt
le
>
≥
<
≤
(N = V) Z
(N = V)
(N ≠ V)
(N ≠ V) Z
signed
arithmetic overflow
arithmetic shortfall
negative
positive
vs
vc
ne
pl
V
V
N
N
signed
Hier wird Wissen Wirklichkeit Computer Architecture – Part 7 – page 56 of 56 – Prof. Dr. Uwe Brinkschulte, Prof. Dr. Klaus Waldschmidt
Multimedia instructions
Typical SIMD instructions to process a single operation on a set of
data (e.g. changing the brightness of image pixels)
Operations can be on packed integers (e.g. MMX on Pentium) or
packed floats (e.g. SSE2 on Pentium)
Typical operations: arithmetic (saturated or overflow), logic, compare,
pack, unpack
Example: