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13-September-05 1
SiGe biCMOS for Next Gen Strip Readout 1E.N. SpencerSCIPP-UCSC
ATLASATLAS
Evaluation of SiGe biCMOS Technologies for Evaluation of SiGe biCMOS Technologies for Next Generation Strip ReadoutNext Generation Strip Readout
11th LHC Electronics Workshop
Heidelberg
13-Sept-2005
E. N. SpencerSCIPP – UCSC
13-September-05 2
SiGe biCMOS for Next Gen Strip Readout 2E.N. SpencerSCIPP-UCSC
ATLASATLAS
ParticipantsParticipants
D.E. Dorfan, A. A. Grillo, J. Metcalfe, M Rogers, H. F.-W. Sadrozinski, A. Seiden, E. N. Spencer, M. Wilder
SCIPP-UCSC
Collaborators: A. Sutton, J.D. Cressler
Georgia Tech, Atlanta, GA 30332-0250, USAM. Ullan, M. Lozano
CNM, Barcelona
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SiGe biCMOS for Next Gen Strip Readout 3E.N. SpencerSCIPP-UCSC
ATLASATLAS
Bipolar for Large C – Fast Bipolar for Large C – Fast ss
We have shown for past experiments that the bipolar technology has advantages over CMOS in power and performance for front-end amplification of silicon strip readout when the capacitive loads are high and the shaping times short.
• ZEUS-LPS Tek-Z IC
• SSC-SDC LBIC IC
• ATLAS-SCT ABCD, CAFE-M, CAFE-P ICs
Since CMOS is the preferred technology for back-end data processing, biCMOS technologies have not been readily available, making it difficult to find a one chip solution.
Experience with the commercial 0.25 m CMOS has shown the great advantage of using a high volume commercial rather than a niche technology.
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SiGe biCMOS for Next Gen Strip Readout 4E.N. SpencerSCIPP-UCSC
ATLASATLAS
biCMOS with Enhanced SiGebiCMOS with Enhanced SiGe
The market for wireless communication has now spawned many biCMOS technologies where the bipolar devices have been enhanced with a germanium doped base region (SiGe devices).
We have identified at least the following vendors:
• IBM (at least 3 generations available)
• STm
• IHP, (Frankfurt on Oder, Germany)
• Motorola
• JAZZ
Advanced versions include CMOS with feature sizes of 0.25 m to 0.13 m.
The bipolar devices have DC current gains () of several 100 and fTs up to 100s of GHz. This implies very small geometries that could afford higher current densities and more rad-hardness.
Growing number of fab facilities
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SiGe biCMOS for Next Gen Strip Readout 5E.N. SpencerSCIPP-UCSC
ATLASATLAS
Tracker Regions Amenable for SiGeTracker Regions Amenable for SiGe
For the inner tracker layers, pixel detectors will be needed, and their small capacitances allow the use of deep sub-micron CMOS as an efficient readout technology.
Starting at a radius of about 20 cm, at fluence levels of 1015 n/cm2, short strips can be used, with a detector length of about 3 cm and capacitances of the order of 5 pF. At a radius of about 60 cm, the expected fluence is a few times 1014 p/cm2, and longer strips of about 10 cm and capacitance of 15 pF can be used.
It is in these two outer regions with sensors with larger capacitive loads where bipolar SiGe might be used in the front-end readout ASICs with welcome power savings while still maintaining fast shaping times.
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SiGe biCMOS for Next Gen Strip Readout 6E.N. SpencerSCIPP-UCSC
ATLASATLAS
Biasing the Analogue CircuitBiasing the Analogue Circuit
The analog section of a readout IC for silicon strips typically has a special front transistor, selected to minimize noise (often requiring a larger current than the other transistors), and a large number of additional transistors used in the shaping sections and for signal-level discrimination.
The current for the front transistor is selected in order to achieve the desired transconductance (minimize noise). For the other bipolar devices, bias levels for the other transistors are determined to achieve the necessary rad-hardness, matching and shaping times.
Depending upon the performance (especially radiation hardness) of the bipolar process, power savings could be realized in both the front transistor and in the other parts of the analogue circuit.
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SiGe biCMOS for Next Gen Strip Readout 7E.N. SpencerSCIPP-UCSC
ATLASATLAS
J. Kaplon et al., 2004 IEEE Rome Oct 2004, use 0.25 m CMOS
For CMOS: Input transistor: 300 A, other transistors 330 A (each 20 – 90 A)
Potential CMOS Front-EndPotential CMOS Front-End
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SiGe biCMOS for Next Gen Strip Readout 8E.N. SpencerSCIPP-UCSC
ATLASATLAS
Radiation vs. Radius in Upgraded TrackerRadiation vs. Radius in Upgraded Tracker
The usefulness of a SiGe bipolar front-end circuit will depend upon its radiation hardness for the various regions (i.e. radii) where silicon strip detectors might be used.
Outer Radius
Long Strips
Inner
Pixels
Mid-Radius
Short Strips
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SiGe biCMOS for Next Gen Strip Readout 9E.N. SpencerSCIPP-UCSC
ATLASATLAS
First SiGe High-rate Radiation Testing First SiGe High-rate Radiation Testing
Radiation testing has been performed on some SiGe devices by our Georgia Tech collaborators up to a fluence of 1x1014 p/cm2 and they have demonstrated acceptable performance. (See for example: http://isde.vanderbilt.edu/Content/muri/2005MURI/Cressler_MURI.ppt)
In order to extend this data to higher fluences, we obtained some arrays of test structures from our collaborator at Georgia Tech. These were from a -enhanced 5HP process from IBM. (i.e. the was ~250 rather than ~100.)
The parts were tested at UCSC and with the help of RD50 collaborators (Michael Moll & Maurice Glaser) they were irradiated in Fall 2004 at the CERN PS and then re-tested at UCSC.
For expediency, all terminals were grounded during the irradiation This gives slightly amplified rad effects than with normal biasing.
Annealing was performed after initial post-rad testing.
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SiGe biCMOS for Next Gen Strip Readout 10E.N. SpencerSCIPP-UCSC
ATLASATLAS
Irradiated SamplesIrradiated Samples
Pre-rad
ATLAS-SCT => ATLAS-upgrade
Outer Radius
ATLAS-upgrade
Mid RadiusATLAS-upgrade
Inner Radius
4.15E13 1.15E14 3.50E14 1.34E15 3.58E15 1.05E16
Fluences:
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SiGe biCMOS for Next Gen Strip Readout 11E.N. SpencerSCIPP-UCSC
ATLASATLAS
Base Leakage Current Increased by RadiationBase Leakage Current Increased by Radiation
1e15 Irrad Comparison Ic,Ib vs Vbe
1.00E-14
1.00E-13
1.00E-12
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
1.00E-01
1.00E+000 0.2 0.4 0.6 0.8 1
Vbe
Ic, non-irrad
Ib, non-irrad
Ic, Irrad
Ib, Irrad
Gummel Plot before and after 1.3x1015 p/cm2
(decreases as base leakage current increases.)
5HP, enhanced 0.5x2.5 m2
Vce=0.75 V
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SiGe biCMOS for Next Gen Strip Readout 12E.N. SpencerSCIPP-UCSC
ATLASATLAS
Radiation Damage vs. CurrentsRadiation Damage vs. Currents
1e15 Irrad Comparison of Beta vs Ic
0.01
0.1
1
10
100
1000
1.00E-13 1.00E-12 1.00E-11 1.00E-10 1.00E-09 1.00E-08 1.00E-07 1.00E-06 1.00E-05 1.00E-04 1.00E-03
Ic
Vce=0.75VVce=1.25VIrradiated Vce=0.75VIrradiated Vce=1.25V
We see the typical increase in post-rad at higher currents
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SiGe biCMOS for Next Gen Strip Readout 13E.N. SpencerSCIPP-UCSC
ATLASATLAS
Scaling by Current DensityScaling by Current Density
Beta vs Fluence Jc=10 A/m2
1
10
100
1000
1.00E+13 1.00E+14 1.00E+15 1.00E+16 1.00E+17
Fluence (p/cm^2)
bet
a
0.5X1
0.5x2.5
0.5x10
0.5x20
4x5
As expected radiation effects are nearly size independent when scaled by current density.
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SiGe biCMOS for Next Gen Strip Readout 14E.N. SpencerSCIPP-UCSC
ATLASATLAS
Annealing EffectsAnnealing Effects
Annealing repairs some of the damage,
especially since all device terminals were grounded during irradiation.
Annealing Effects on Beta for a 0.5x10 m2 SiGe Transistor at 1x1015 p/cm2
0.01
0.1
1
10
100
1000
1.00E-13 1.00E-11 1.00E-09 1.00E-07 1.00E-05 1.00E-03 1.00E-01
Ic (A)
Be
tanon-irrad
irrad
Anneal: 5 days @ roomtemp
Anneal: plus 6 days @roomtemp, 1 day @ 60 deg C
Anneal: plus 1 day @ 100deg C
Anneal: plus 6 days @ 100deg C
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SiGe biCMOS for Next Gen Strip Readout 15E.N. SpencerSCIPP-UCSC
ATLASATLAS
Feasibility Estimate for 5HPFeasibility Estimate for 5HP
As a quick estimate of feasibility and power savings, we can find an operating point with > 50.
At 1.3x1015 (radius ~20cm) the minimum size transistor can operate at 100 nA.
For R ~20 cm, bias at Ic = 10 A shows these effective betas:
Fluence: 1.34E15Ic=10A
Transistor Size m2 pre
irrad
anneal
0.5x1 242 35 1110.5x2.5 320 25 630.5x10 302 15 510.5x20 300 9 314x5 372 19 48
Fluence: 1.34E15=50 Required Current
Transistor Size m2 cirrad Ic anneal
0.5x1 3.E-05 1.E-070.5x2.5 7.E-05 4.E-060.5x10 4.E-04 1.E-050.5x20 6.E-054x5 1.E-04 1.E-05
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SiGe biCMOS for Next Gen Strip Readout 16E.N. SpencerSCIPP-UCSC
ATLASATLAS
IHP Design to Estimate Power Use of SCT Upgrade Front End
IHP has the SG25H1 200 Ghz Sige process available on Europractice. Beta is ~200. In parallel with radiation testing by Barcelona, UCSC is developing an eight channel amplifier/comparator with similar specifications to the present ABCD.
The x4 minimum transistor has base resistance of 51 m x 3.36 m. 0.25 m CMOS is also included. Extensive use is made of the 2.0 k/ square unsilicided polysilicon resistor structure, since this is expected to be radiation resistant.
The purpose of this FE design is to estimate the low current bias performance of SiGe, and to see whether it can produce significant power savings. The target voltage bias level is 2 V.
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SiGe biCMOS for Next Gen Strip Readout 17E.N. SpencerSCIPP-UCSC
ATLASATLAS
Design Procedure Details
IHP provides a Cadence Kit, with support for both Diva and Allegro.
The bipolar devices are complete as provided, no editing allowed, with some hidden layers to protect IHP intellectual property.
Radiation hard annular NMOS transistor drawing is well supported. This is done by allowing 135 degree bends of Poly lines on Active in the DRC. There are included Virtuoso utilities that are needed for successful DRC.
Cadence Spectre does not DC converge well. Mentor has Eldo utility “Artist Link” that enables Eldo to run with Cadence schematic Composer. Eldo converges vigorously. Overall, the Cadence Kit is complete enough, and with the help of Eldo, is a good toolset.
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SiGe biCMOS for Next Gen Strip Readout 18E.N. SpencerSCIPP-UCSC
ATLASATLAS
SCT-FE Sim Results
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SiGe biCMOS for Next Gen Strip Readout 19E.N. SpencerSCIPP-UCSC
ATLASATLAS
First Guess at Potential Power SavingsFirst Guess at Potential Power Savings
CHIP TECHNOLOGY FEATURE
0.25 m CMOS ABCDS/FE
J. Kaplon et al.,(IEEE Rome Oct 2004)
IHP SG25H1 SCT-FE Preliminary design
Power: Bias for all but front transistor
330 A 0.8 mW= 30 A(conservative)
.06 mW
Power: Front bias for 25 pF load 300 A 0.75 mW
150 A 0.30 mW
Power: Front bias for 7 pF load 120 A 0.3 mW A 0.10 mW
Total Power (7 pF) 2x1015
0.36 mWTotal Power (25 pF) 3x1014
1.1 mW
1.5 mW
0.16mW
Using similar estimates of bias settings and transistor counts, an estimate for power can be obtained.
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SiGe biCMOS for Next Gen Strip Readout 20E.N. SpencerSCIPP-UCSC
ATLASATLAS
ConclusionsConclusions
First tests of one SiGe biCMOS process indicate that the bipolar devices may be sufficiently rad-hard for the upgraded ATLAS tracker, certainly in the outer-radius region and even perhaps in the mid-radius region.
A simulation estimate of power consumption for such a SiGe front-end circuit indicates that significant power savings might be achieved.
More work is needed to both confirm the radiation hardness and arrive at more accurate estimates of power savings.
In particular, with so many potential commercial vendors available, it is important to understand if the post-radiation performance is generic to the SiGe technology or if it is specific to some versions.
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SiGe biCMOS for Next Gen Strip Readout 21E.N. SpencerSCIPP-UCSC
ATLASATLAS
Work AheadWork Ahead
Along with our collaborators, we plan two parallel paths of work.
First, we plan more irradiations with several SiGe processes. In particular, we plan to test at least the IBM 5HP, IBM enhanced 5HP, IBM 8HP, IHP SG25H1 and one from STm.
• CNM has obtained a first set of test structures from IHP and is proceeding.
• UCSC has recently received the IBM test structures.
• We have been promised test structures from STm but a schedule is not yet fixed.
To obtain a better handle on the true power savings, we will submit an IHP 8 channel amplifier/comparator early in 2006. This work is in parallel with IHP radiation characterization.