ELEN 468 Lecture 27 1

ELEN 468Advanced Logic Design

Lecture 27Interconnect Timing Optimization II

ELEN 468 Lecture 27 2

Wire Segmenting

Faster runtime

Better solution quality

ELEN 468 Lecture 27 3

Multiple Buffer Types

(v1, 1, 20)22 • r = 1, c = 1

• Rb = 1, Cb = 1, tb = 1

• Rb2 = 0.5, Cb2 = 2, tb2 = 0.5

• Rd = 1v1

(v2, 3, 16)

v1

(v2, 1, 12)

v1

(v2, 2, 14)

ELEN 468 Lecture 27 4

Using Inverters

Less cost

ELEN 468 Lecture 27 5

Handle Polarity

-NegativePositiv

e

-

-

-

-

-

-

ELEN 468 Lecture 27 6

Slew Constraints

When a buffer is inserted, assume ideal slew rate at its inputCheck slew rate at downstream buffers/sinksIf slew is too large, candidate is discarded

ELEN 468 Lecture 27 7

Capacitance Constraints

Each gate g drives at most C(g) capacitanceWhen inserting buffer g, check downstream capacitance. If > C(g), throw out candidate

Total cap = 500 ff

ELEN 468 Lecture 27 8

Consider Cost/Power

A solution is also characterized by cost w A solution is inferior if it is poor on all of c, q and wAt source, a set of solutions with tradeoff of q and ww can be total capacitance or the number of buffers

ELEN 468 Lecture 27 9

Cost-Slack Trade-off

-4000

-3000

-2000

-1000

0

1000

0 1 2 3 4 5 6 7

# of Buffers

Slac

k (p

s)

ELEN 468 Lecture 27 10

Data Organization

0

1

2

3

4

(c1, q1) (c2, q2) (c3, q3)

(c4, q4) (c5, q5) (c6, q6)

(c7, q7) (c8, q8)

(c9, q9) (c10, q10)

(c0, q0)

#buffers inserted

Sorted in ascending order of (c, q)

ELEN 468 Lecture 27 11

Pruning Considering Cost

(ci , qi , wi) is inferior to (ck , qk , wk) if ci > ck , qi < qk , wi > wk

0

1

2

(c1, q1) (c2, q2) (c3, q3)

(c4, q4) (c5, q5) (c6, q6)

(c0, q0)

w

Prune order

Pruning within a list is same as before

ELEN 468 Lecture 27 12

Continuous Wire Sizing

Min delay wire shape: w(x) = a(e-bx)

x

ELEN 468 Lecture 27 13

Two Types of Wire Sizing

Uniform Wire Sizing (UWS)

Wire Tapering (TWS)

ELEN 468 Lecture 27 14

TWS versus UWS

TWS

UWS

0354.12

22

)(_

)(_

eUWSVelocitySignal

TWSVelocitySignal

ELEN 468 Lecture 27 15

Why Uniform Wire Sizing?

Empirically, UWS almost as good as TWSTapering info hard to give to routerBetter congestion and space managementExtraction, detailed routing, verification?Can do it simultaneously with buffering

ELEN 468 Lecture 27 16

Wire Sizing to Minimize Weighted Delay Sum

Minimize iti

i weight, ti Elmore delay to sink i Properties Separability Monotone property Dominance property

ELEN 468 Lecture 27 17

Wire Sizing: Separability

For given wire sizing along a path, optimal wire sizing for each subtree off the path can be carried out independently

ELEN 468 Lecture 27 18

Wire Sizing: Monotone Property

Ancestor edges cannot be narrower than downstream edges

ELEN 468 Lecture 27 19

Wire Sizing: Dominance Property

For each edge, if its width in solution W its width in solution W’, then W dominates W’ Local refinement: size each edge independently to minimize delay sum while other edges are fixedAssume W* is the optimal solution If W dominates W* , then W still dominates W*

after local refinement If W is dominated by W* , then W is still

dominated by W* after local refinement

ELEN 468 Lecture 27 20

Optimal Wire Sizing

Maximum width solution Each edge starts with max width Perform local refinement

Minimum width solution Each edge starts with min width Perform local refinement

Enumerate possibilities between min and max width solutions

ELEN 468 Lecture 27 21

Wire Sizing to Maximize the Min Slack

Separability is not true hereCan be solved with dynamic programmingCan be integrated with buffer insertion

ELEN 468 Lecture 27 22

Simultaneous Buffer Insertion and Wire Sizing

ELEN 468 Lecture 27 23

Driver Sizing

ELEN 468 Lecture 27 24

Combine Buffering and Driver Sizing Directly?

Min delay

ELEN 468 Lecture 27 25

Impact To Previous Stage

Current stage

Previous stage

Small load

Large load

Large delay

Small delay

Cd

ELEN 468 Lecture 27 26

Input Load Penalty

Penalty = delay of min delay buffer chain driving Cd

Min buffer Cd

ELEN 468 Lecture 27 27

Driver Sizing Considering Impact to Previous Stage

Current stage

Previous stage

Small load

Large load

Large delay

Small delay

Cd

Large penalty

ELEN 468 Lecture 27 28

Driver Sizing in Van Ginneken’s Algorithm

Treat the buffer chain as a part of the net

Length = 0

Run van Ginneken’s algorithm with fixed driver and min sized buffer