ELEN 468 Lecture 251 ELEN 468 Advanced Logic Design Lecture 25 Built-in Self Test.
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ELEN 468 Lecture 25 1 ELEN 468 Advanced Logic Design Lecture 25 Built-in Self Test
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Transcript of ELEN 468 Lecture 251 ELEN 468 Advanced Logic Design Lecture 25 Built-in Self Test.
ELEN 468 Lecture 25 1
ELEN 468Advanced Logic Design
Lecture 25Built-in Self Test
ELEN 468 Lecture 25 2
BIST ( Built-in Self Test )PRPG: Pseudo Random Pattern GeneratorORA: Output Response AnalyzerCUT: Circuit Under Test
PRPG
CUT
ORA
Start
Pass/fail
PI PO
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BIST MotivationUseful for field test and diagnosis (less expensive than a local automatic test equipment)
ELEN 468 Lecture 25 4
Designand test
+ / -
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+ / -
Fabri-cation
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Manuf.Test
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Level
Chips
Boards
System
Maintenancetest
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Diagnosisand repair
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Serviceinterruption
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+ Cost increase - Cost saving+/- Cost increase may balance cost reduction
Benefits and Costs of BIST
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Economics – BIST Costs Chip area overhead for:
Test controller Hardware pattern generator Hardware response compacter Testing of BIST hardware
Pin overhead – at least 1 pin needed to activate BIST operation
Performance overhead – extra path delays
Reliability reduction – due to increased area and complexity
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BIST Benefits
Reduced testing and maintenance cost
Lower test generation cost Reduced storage / maintenance of
test patterns Simpler and less expensive ATE Can test many units in parallel Shorter test application times Can test at functional system speed
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BIST Types
On-line BIST Concurrent Non-concurrent
Off-line BIST Functional Structural
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BIST Architecture
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Pseudo-Random Pattern Generation through LFSR
Linear Feedback Shift Register (LFSR) Produces patterns algorithmically – repeatable Has most of desirable random # properties
Long sequences needed for good fault coverage
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Response Compaction
Severe amounts of data in CUT response to LFSR patterns – example: Generate 5 million random patterns CUT has 200 outputs 5 million x 200 = 1 billion bits response
Uneconomical to store and check all of these responses on chipResponses must be compacted
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LFSR for Response Compacter
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Signature AnalysisSignature – any statistical circuit property distinguishing between bad and good circuitsAliasing – due to information loss, signatures of good and some bad machines matchSignature analysis – compare good machine response into good machine signature. Actual signature generated during testing, and compared with good machine signature
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BILBO (Built-in Logic Block Observer)
Four modes:1. Flip-flop2. LFSR pattern generator3. LFSR response compacter4. Scan chain for flip-flops
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Example of BILBOCombined functionality of D flip-flop, pattern generator, response compacter and scan chain
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BILBO Serial Scan ModeB1 B2 = “00”
Dark lines show enabled data paths
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BILBO LFSR Pattern Generator Mode
B1 B2 = “01”
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BILBO in D-FF (Normal) Mode
B1 B2 = “10”
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BILBO in Response Compactor Mode
B1 B2 = “11”
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Exercises Exercises 77
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Problem 1
always @ ( … ) begin
for ( j = 0; j < n; j = j + 1 )
begin a[j] = 0;
for ( k = 0; k < j; k = k + 1 )
@ ( posedge clock )
a[j] = a[j] + x[k];
end end
always @ ( … ) begin
for ( j = 0; j < n; j = j + 1 )
begin
a[j] = 0;
for ( k = 0; k < j; k = k + 1 )
@ ( posedge clock )
a[j] = a[j] + x[k];
end
end
always @ ( … ) begin…
a[0] = 0; for ( j = 0; j < n; j = j +
1 ) begin
@ ( posedge clock ) a[j] = a[j-1] + x[j-1];end
end
always @ ( … ) begin…
a[0] = 0; for ( j = 0; j < n; j = j +
1 ) begin
@ ( posedge clock ) a[j] = a[j-1] + x[j-1];end
end
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Problem 2
Flip-flopa
y
x
b
c zLatch
clock
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Problem 3.1
+
Reg a
Reg b
Reg c
+
+
ELEN 468 Lecture 25 23
Problem 3.2
+
Reg a
Reg b
Reg c
+
+
