ELEN 468 Lecture 241 ELEN 468 Advanced Logic Design Lecture 24 Design for Testability.

ELEN 468 Lecture 24 1

ELEN 468Advanced Logic Design

Lecture 24Design for Testability


Test Cost

Test pattern generationFault simulationGeneration of fault sites informationTest equipmentTest processTest cost may overweight design cost


Why Design for Testability?

Testability is a design characteristic that influences various costs associated with testingIt allows for Device status to be determined Isolation of faults Reduce test time and cost


Controllability

Ability to establish a specific signal value at each node by setting circuit’s inputsCircuits typically difficult to control: decoders, circuits with feedback, oscillators, clock generators …


Observability

Ability to determine the signal value at any node in a circuit by controlling the circuit’s inputs and observing its output


Predictability

Ability to obtain known output values in response to given input stimuliFactors affecting predictability Initial state of circuit Races Hazards … …


Difficult Test Cases

Sequential logic is more difficult to test than combinational logicControl logic is more difficult to test than data-path logicRandom logic is more difficult to test than structured bus-oriented designsAsynchronous design is more difficult to test than synchronous design


Quantify TestabilityNeed approximate measure of: Difficulty of setting internal circuit lines to 0

or 1 by setting primary circuit inputs Difficulty of observing internal circuit lines by

observing primary outputs

Uses: Analysis of difficulty of testing internal circuit

parts – redesign or add special test hardware Guidance for algorithms computing test

patterns – avoid using hard-to-control lines Estimation of fault coverage Estimation of test vector length


Types of Measures SCOAP – Sandia Controllability and Observability

Analysis Program Combinational measures:

CC0 – Difficulty of setting circuit line to logic 0 CC1 – Difficulty of setting circuit line to logic 1 CO – Difficulty of observing a circuit line

Sequential measures – analogous: SC0 SC1 SO


Range of SCOAP Measures Controllabilities – 1 (easiest) to infinity

(hardest) Observabilities – 0 (easiest) to infinity

(hardest) Combinational measures:

Roughly proportional to # circuit lines that must be set to control or observe given line

Sequential measures: Roughly proportional to # times a flip-flop must be

clocked to control or observe given line


Controllability Examples


Observability Examples


Goal of Design for Testability (DFT)

Improve Controllability Observability Predictability


Design and Test Trade-off

Most DFT ( Design for Testability ) techniques need extra hardware, or modification to circuits that may affect performancesDFT need to consider the cost trade-off between design and test


DFT MethodsDFT methods for digital circuits: Ad-hoc methods Structured methods:

Scan Partial Scan Built-in self-test (BIST) Boundary scan


Ad-Hoc DFT MethodsGood design practices learnt through experience are used as guidelines:

Avoid asynchronous (unclocked) feedback Make flip-flops initializable Avoid redundant gates Avoid large fanin gates Provide test control for difficult-to-control signals Avoid gated clocks

Design reviews conducted by experts or design auditing toolsDisadvantages of ad-hoc DFT methods:

Experts and tools not always available Test generation is often manual with no guarantee of high

fault coverage Design iterations may be necessary


Scan DesignCircuit is designed using pre-specified design rulesTest structure (hardware) is added to the verified design: Add a test control (TC) primary input Replace flip-flops by scan flip-flops (SFF) and

connect to form one or more shift registers in the test mode

Make input/output of each scan shift register controllable/observable from PI/PO


Scan Design Rules

Use only clocked D-type of flip-flops for all state variablesAt least one PI pin must be available for test; more pins, if available, can be usedAll clocks must be controlled from PIs


Correcting a Rule ViolationAll clocks must be controlled from PIs

Comb.logic

Comb.logic

D1

D2

CK

Q

FF

Comb.logic

D1

D2CK

Q

FF

Comb.logic


Scan Storage Cell

DSiN/

T’Clk

Q, So

SSC

D Q

SSC


Scan Flip-Flop (SFF)

DN/T’

Si

Clk

Q

QMUX

D flip-flop

Master latch Slave latch

Logicoverhead


Scan Methods

C1

C2

C2

C1

MUX

Si


Boundary Scan

MUX


Integrated Serial Scan

SFF

SFF

SFF

Combinational

logic

PI PO

SCANOUT

SCANINControl

ELEN 468 Lecture 241 ELEN 468 Advanced Logic Design Lecture 24 Design for Testability.

Documents

Transcript of ELEN 468 Lecture 241 ELEN 468 Advanced Logic Design Lecture 24 Design for Testability.