Post on 20-Apr-2022
ECE 4510/5530Microcontroller Applications
Week 5 Lab 5
Dr. Bradley J. BazuinAssociate Professor
Department of Electrical and Computer EngineeringCollege of Engineering and Applied Sciences
ECE 2510 2
Lab 5 Element
• Hardware Development– Enhanced Capture Timer (ECT) (Chap. 8)
• Input Capture (external event timing)
– Pulse Width Modulator (PWM) (Chap. 8)– Serial Communication Interface (SCI) (Chap. 9)
• RS-232 Transceiver
• Software Development– Smoothing (filtering) measured data
SMOOTHING MEASURED DATA
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Measured Data Factors
• Microprocessors can capture measurements very quickly, but …
• If taken with poor resolution, the accuracy of the measurement may not be very great.
– Example: the ECT counting rate sets the “set size” for period and pulse width measurements.
– Big time steps relative to the value to be measured results in poor resolution. The time measurement lsb value is too big.
– Small time steps relative to the value may cause the CNT counter to overflow making the collected values “ambiguous” … how many times did the counter overflow?
• There is often a trade-off between speed and accuracy– The quicker the measurement, the poorer the resolution.
• The measurement rate of a microprocessor may in general be higher than the rate at which the measured values need to be used or displayed.
– If so, we can apply filters that provide higher accuracy using multiple “filtered” measurements.
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Simple Microprocessor Filters (1)
• Mean filter: the sum of multiple measurements divided by the number of elements.– Collect a “buffer” of data … for example 8 samples.– Sum the samples and divide by the number of samples. – Select a “divisor” that is a power of 2 and “shift right” to divide.
• You may want to apply wounding to the result– A new “buffer” of data can be collected after every 8 samples, overwriting
the original data buffer. The data rate is reduced by 8.
– Advantages: easy to implement (sum and shift), applicable to integers, maintains lsb magnitude, DSP operation easily described (filter-decimate)
– Concerns: numerical overflow in the summation, the size of the buffer.
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12
0
1221int
K
i
KKroundavg ixx
12
021 K
iKavg ixx
Simple Microprocessor Filters (2)
• Median filter: keep the sample in the middle.– Collect a “buffer” of data … for example 7 samples.– Sort the sample in order and use the middle one.
• Always collect an odd number of samples, insuring one-in-the-middle.
– Advantages: easy to implement (sorting algos well known), applicable to integers, maintains lsb magnitude, can deal with “bad data points”
– Concerns: sorting takes a ling time, no good DSP math equivalent for the process, biased measurement?
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Simple Microprocessor Filters (3)
• Infinite-Impulse Response (IIR) Filter: keep a running average.
– Form a weighted sum of the previous result with the new measurement.– If alpha is a “fractional” power of 2, computations is done by shifting and
adding.
– Advantages: easy to implement (shift, add, one extra memory location), applicable to integers, DSP operation easily described (z-domain)
– Concerns: initialize y(0), lsb’s of x(n) can be lost by shift operation.ECE 4510/5530
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nxnyny 11
n
k
k knxny0
1
111
zzX
zY
nxnynyny KK
211
211
Complex Microprocessor Filters
• Finite-Impulse Response (FIR) Filter:– Collect a “buffer” of data … for example 8 samples.– Perform a weighted sum of the samples
– Advantages: DSP operation easily described (z-domain), filtering shaping readily described/performed, linear phase ….
– Concerns: high multiply-accumulate count (N multiplies and N-1 adds for every sample), operations per sample can be expensive, N/2 output time delay
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1
0
N
k
knxkwny
1
0
N
k
kzkwzXzY
Lab 5
• Input capture data can be smoothed prior to display– Measurements taken at “period rate”, output requested every 2
seconds.– Try to use an IIR filter approach.
• For this “data collection” the sampling is not on a uniform interval, therefore DSP/mathematically not robust– For DSP you should use a fixed, periodic sample rate
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PULSE WIDTH MODULATOR
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Overview of PWM Functions
• Many applications require the generation of digital waveform.– Output compare function can be used to generate digital waveform
but incur too much overhead.– Pulse width modulation requires only the initial setup of period and
duty cycle for generating the digital waveform.
• PWM Applications– Motor Drive Systems– Waveform Generation– Periodic Clock Outputs– Low Cost Digital to Analog Converter (PWM and a Filter)
• The PWM shares the eight Port P pins (PWM0…PWM7).
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Pulse Width Modulation (PWM)
• Each PWM channel has a period register, a duty cycle register, a control register, and a dedicated counter.
• The clock input to PWM is programmable through a two-stage circuitry.
• There are four possible clock sources for the PWM module: clock A, clock SA, clock B, and clock SB.– Clock A and clock B are derived by dividing the E clock by a
power of 2. The power can range from 0 to 7.– Clock SA is derived by dividing the clock A by an even number
ranging from 2 to 512.– Clock SB is derived by dividing the clock B by an even number
ranging from 2 to 512.
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Pulse Width Modulation (PWM)
• Many applications require the generation of digital waveform.
• Output compare function can be used to generate digital waveform but incur too much overhead.
• Pulse width modulation requires only the initial setup of period and duty cycle for generating the digital waveform.
• The MC9S12DP512 has an 8-channel PWM module.
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Pulse Width Modulation (PWM)
• Each PWM channel has a period register, a duty cycle register, a control register, and a dedicated counter.
• The clock input to PWM is programmable through a two-stage circuitry.
• There are four possible clock sources for the PWM module: clock A, clock SA, clock B, and clock SB.– Clock SA is derived by dividing the clock A by an even number
ranging from 2 to 512.– Clock SB is derived by dividing the clock B by an even number
ranging from 2 to 512.– Clock A and clock B are derived by dividing the E clock by a
power of 2. The power can range from 0 to 7.
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Channel 7
Period and duty Counter
PWM Channels
Channel 6
Period and duty Counter
Channel 5
Period and duty Counter
Channel 4
Period and duty Counter
Channel 3
Period and duty Counter
Channel 2
Period and duty Counter
Channel 1
Period and duty Counter
Channel 0
Period and duty Counter
Clock select
Control
PWMclock
PWM Module
Enable
Polarity
Alignment
Bus clock
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Figure 8.38 HCS12 PWM block diagram
PWM Block Diagram
Making Clocks
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A ClockSA ClockChannels 0, 1, 4, 5
B ClockSB ClockChannels 2, 3, 6, 7
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7 6 5 4 3 2 1 0
0 PCKB2 PCKB1 PCKB0 0 PCKA2 PCKA1 PCKA0
reset: 0 00 0 0 0 0 0
Table 8.3 Clock B prescaler selects
PCKB2 PCKB1 PCKB0 value of clockB
00001111
00110011
01010101
E clockE clock/2E clock/4E clock/8E clock/16E clock/32E clock/64E clock/128
Table 8.4 Clock A prescaler selects
PCKA2 PCKA1 PCKA0 value of clockA
00001111
00110011
01010101
E clockE clock/2E clock/4E clock/8E clock/16E clock/32E clock/64E clock/128
Figure 8.41 PWM prescale clock select register (PWMPRCLK)
PWM Clock Prescale
• The prescale factors for clock A and clock B are determined by the PCKA2…PCKA0 and PCKB2…PCKB0 bits of the PWMPRCLK register.
– Clock SA is derived by dividing clock A by the value of the PWMSCLA register and then dividing by 2.
– Clock SB is derived by dividing clock B by the value of the PWMSCLB register and then dividing by 2.
• The clock source selection is controlled by the PWMCLK register.
Limited Choices
PWM Scale A/B
• Clock SA = Clock A / (2 * PWMSCLA)• Clock SB = Clock B / (2 * PWMSCLB)
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PWM Clock Source Selection
• PWM Channel to clock select– 0, 1, 4 and 5 use A or SA clock– 2, 3, 5 and 6 use B or SB clock
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7 6 5 4 3 2 1 0
PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0
reset: 0 00 0 0 0 0 0
Figure 8.42 PWM clock select register (PWMCLK)
PCLKx: PWM channel x clock select (x = 7, 6, 3, 2) 0 = clock B as the clock source 1 = clock SB as the clock sourcePCLKy: PWM channel y clock select (y = 5, 4, 1, 0) 0 = clock A as the clock source 1 = clock SA as the clock source
PWME: Turning a PWM Channel On
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GATE8-bit counter
PWMCNTx
8-bit compare=
PWMDTYx
clocksource
8-bit compare=
PWMPERx
T Q
QR
MUX
T
R
CAExQ
Q
MUX
to pindriver
PPOLx
From port PTPdata register(clock edge sync)
PWMEx
up/down re
set
Figure 8.44 PWM channel block diagram
PWM Channel Block Diagram
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PWM Channel Timers
• The main part of each PWM channel x consists of an 8-bit counter (PWMCNTx), an 8-bit period register (PWMPERx), and an 8-bit duty cycle register (PWMDTYx).– The waveform output period is controlled by the match between the
PWMPERx register and PWMCNTx register.– The waveform output duty cycle is controlled by the match of the
PWMDTYx register and the PWMCNTx register.
• The starting polarity of the output is selectable on a per channel basis by programming the PWMPOL register.
• The overall operation of the PWM module is shown in Figure 8.44 on the previous slide.
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7 6 5 4 3 2 1 0
PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0
reset: 0 00 0 0 0 0 0
Figure 8.43 PWM polarity register (PWMPOL)
PPOLx: PWM channel x polarity 0 = PWM channel x output is low at the start of a period, then goes high when the duty count is reached. 1 = PWM channel x output is high at the start of a period, then goes low when the duty count is reached.
PWMPOL
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PWM Waveform Alignment
• PWM output waveform can be left-aligned or center-aligned.
• The choice of alignment is controlled by the PWMCAE register.
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Left-Aligned Output
• The PWMCNTx counter is configured as a count-up counter.– PWMx frequency = Clock(A, B, SA, SB frequency) PWMPERx
– If Polarity = 0• PWMx duty cycle = [(PWMPERx – PWMDTYx) PWMPERx] 100%
– If Polarity = 1• PWMx duty cycle = [PWMDTYx PWMPERx] 100%
PWMDTYxPeriod = PWMPERx
PPOLx = 0
PPOLx = 1
Figure 8.47 PWM left-aligned output waveform
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Center-Aligned Mode
• PWM counter is configured to operates as an up/down counter and is set to count up whenever the counter is equal to $00.
• When the counter matches the duty register the output flip-flop changes state causing the PWM output to also change state.
• A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count.
• When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the PWM output to also change state.
• When the PWM counter decrements to 0, the counter direction changes from a down-count back to an up-count and the period and duty registers are reloaded from their buffers.
Regular: a sawtooth count and compareCenter: up and down count with compare. (period is 1/2x sawtooth)
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PWMx frequency = Clock (A, B, SA, or SB) frequency (2 PWMPERx)
When polarity = 0,PWMx duty cycle = [(PWMPERx – PWMDTYx) PWMPERx] 100%
When polarity = 1,PWMx duty cycle = [PWMDTYx PWMPERx] 100%
PPOLx = 0
PPOLx = 1PWMDTYx PWMDTYx
PWMPERx PWMPERx
Period = PWMPERx * 2Figure 8.48 PWM center aligned output waveform
In Aligned Mode
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PWM 16-bit Mode (1 of 2)
• Two adjacent PWM channels can be concatenated into a 16-bit PWM channel.
• The concatenation of PWM channels are controlled by the PWMCTL register.
• The 16-bit PWM system is illustrated in Figure 8.49. • When channel k and k+1 are concatenated, channel k is the
high-order channel, whereas channel k+1 is the lower channel. (k is even number). A 16-bit channel outputs from the lower-order channel pin and is also enabled by the lower-order channel.
• Both left-aligned and center-aligned mode apply to the 16-bit mode.
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7 6 5 4 3 2 1 0
CON67 CON45 CON23 CON01 PSWAI PFRZ 0 0
reset: 0 00 0 0 0 0 0
Figure 8.40 PWM control register (PWMCTL)
CONjk: concatenate channels j and k (j = 0, 2, 4, or 6; k = j+1) 0 = channel j and k are separate 8-bit PWMs 1 = Channels j and k are concatenated to create one 16-bit PWM channel. Channel j becomes the high order byte and channel k becomes the low order byte. Channel k output pin is used as the output for this 16-bit PWM. Channel k clock select bit determines the clock source, channel k polarity bit determines the polarity, channel k enable bit enables the output and channel k center aligned enable bit determines the output mode.PSWAI: PWM stops in wait mode 0 = allow the clock to the prescaler to continue while in wait mode 1 = stop the input clock to the prescaler whenever the MCU is in wait modePFRZ: PWM counters stop in freeze mode 0 = allow PWM to continue while in freeze mode 1 = disable PWM input clock to the prescaler whenever the part is in freeze mode.
PWM 16-bit Mode (2 of 2)
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PWMCNT6 PWMCNT7
Period/Duty compare PWM7
Clock source 7
PWMCNT4 PWMCNT5
Period/Duty compare PWM5
Clock source 5
PWMCNT2 PWMCNT3
Period/Duty compare PWM3
Clock source 3
PWMCNT0 PWMCNT1
Period/Duty compare PWM1
Clock source 1
high
high
high
high
low
low
low
low
Figure 8.49 PWM 16-bit mode
PWM 16-bit Block Diagram
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#include “c:\miniide\hcs12.inc”…movb #0,PWMCLK ; select clock A as the clock source for PWM0movb #1,PWMPRCLK ; set clock A prescaler to 2movb #1,PWMPOL ; channel 0 output high at the start of the periodmovb #0,PWMCAE ; select left-aligned modemovb #$0C,PWMCTL ; 8-bit mode, stop PWM in wait and freeze modemovb #120,PWMPER0 ; set period valuemovb #60,PWMDTY0 ; set duty valuemovb #0,PWMCNT0 ; reset the PWM0 counterbset PWMEN,PWME0 ; enable PWM channel 0
• Write an instruction sequence to generate a 100KHz waveform with 50% duty cycle from the PWM0 pin (PP0). Assume that the E clock frequency is 24 MHz.
• Solution: Use the following setting:– Select clock A as the clock source to PWM0 and set its prescaler to 2.– Select left-aligned mode.– Load the value 120 into the PWMPER0 register (= 24000000 100000 2)– Load the value 60 into the PWMDTY0 register (= 120 50%)
Example 8.21
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movb #0,PWMCLK ; select clock A as the clock sourcemovb #1,PWMPOL ; set PWM0 output to start with high levelmovb #1,PWMPRCLK ; set the PWM0 prescaler to clock A to 2movb #1,PWMCAE ; select PWM0 center-aligned modemovb #$0C,PWMCTL ; select 8-bit mode, stop PWM in wait modemovb #120,PWMPER0 ; set period valuemovb #72,PWMDTY0 ; set duty valuebset PWME,PWME0 ; enable PWM channel 0
• Write an instruction sequence to generate a square wave with 20 ms period and 60% duty cycle from PWM0 and use center-aligned mode.
• Solution: – Select clock A as the clock source and set its prescaler to 2.– Load the value 120 into PWMPER0 register.– PWMPER0 = (20 24,000,000 1000,000) 2 2 = 120– PWMDTY0 = PWMPER0 60% = 72.
Example 8.22
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movb #0,PWMCLK ; select clock A as the clock sourcemovb #2,PWMPOL ; set PWM0:PWM1 output to start with high levelmovb #4,PWMPRCLK ; set prescaler to 16movb #$1C,PWMCTL ; concatenate PWM0:PWM1, stop PWM in wait modemovb #0,PWMCAE ; select left align modemovw #30000,PWMPER0 ; set period to 30000movw #24000,PWMDTY0 ; set duty to 24000bset PWME,PWME1 ; enable PWM0:PWM1
• Write an instruction sequence to generate a 50 Hz digital waveform with 80% duty cycle using the 16-bit mode from the PWM1 output pin.
• Solution: Using the following setting:– Select clock A as the clock source and set its prescaler to 16.– Select left aligned mode and select polarity 1.– Load the value 30000 into the PWMPER0:PWMPER1 register.– Load the value 24000 into the PWMDTY0:PWMDTY1 register.
Example 8.23
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#include “c:\egnu091\include\hcs12.h”#include “c:\egnu091\include\delay.c”
• Use PWM to dim the light bulb. Assume that we use the PWM0 output to control the brightness of a light bulb. Write a C program to dim the light to 10% brightness gradually in five seconds.
• The E clock frequency is 24 MHz.• Solution:
– Set duty cycle to 100% at the beginning.– Dim the brightness by 10% in the first second and then 20% per second in the following
four seconds.– Load 100 into the PWMPER0 register at the beginning. – Decrement PWMPER0 by 1 every 100 ms during the first second and decrement
PWMPER0 by 2 every 100 ms in the following four seconds.
Example 8.24
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void main (){
int dim_cnt;pwm_init(); // initialize the pwm
/* reduce duty cycle 1 % per 100 ms in the first second */for (dim_cnt = 0; dim_cnt < 10 ; dim_cnt ++) { delayby100ms(1);
PWMDTY0--;}
/* reduce duty cycle 2% per 100 ms in the next 4 seconds */for (dim_cnt = 0; dim_cnt < 40; dim_cnt ++){ delayby100ms(1);
PWMDTY0 -= 2;}while(1);
}
C Codevoid pwm_init(void){
PWMCLK = 0; /* select clock A as the clock source */PWMPOL = 1; /* make waveform to start with high level */PWMCTL = 0x0C; /* select 8-bit mode */PWMPRCLK = 2; /* set clock A prescaler to 4 */PWMCAE = 0; /* select left-aligned mode */PWMPER0 = 100; /* set period of PWM0 to 0.1 ms */PWMDTY0 = 100; /* set duty cycle to 100% */PWME |= 0x01; /* enable PWM0 channel */
}
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DC Motor Control (1 of 4)
• The DC motor has a permanent magnetic field and its armature is a coil. – When a voltage and a subsequent current flow are applied to the
armature, the motor begins to spin. – The voltage level applied across the armature determines the speed
of rotation. – Changing the speed requires varying the effective voltage level of
the input to the motor. (Use PWM duty cycles)
• Almost every application that uses a DC motor requires it to reverse its direction of rotation or vary its speed.– Reversing the direction is done by changing the polarity of voltage
applied to the motor.
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DC Motor Control (2 of 4)
• Changing the voltage level can be achieved by varying the pulse width of a digital signal input to the DC motor. – The HCS12 can interface with a DC motor through a driver as
shown in Figure 8.52. – A suitable driver must be selected to take control signals from the
HCS12 and deliver the necessary voltage and current to the motor.
• An example of DC motor driver is shown in Figure 8.53.– The L293 has two supply voltages: VSS and VS. VSS is logic
supply and can be from 4.5 to 36V. VS is analog and can be as high as 36 V.
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HCS12
PP7
PP3
PT0feedback
direction
speedon/off
Driver DC motor
Figure 8.52 Simplified circuit for DC motor control
DC Motor Control (3 of 4)
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12
34
5678 9
101112
1314
1516CE1
IN1
OUT1GND
GNDOUT2
IN2VS CE2
IN3
OUT3
GND
GND
IN4
OUT4
VSS
(a) Pin Assignment
M
M
M10
1010
10
0101 1
2
3
45
6
7
8
1615
141312
11
109
VSS
VS(b) Motor connection
Figure 8.53 Motor driver L293 pin assignment and motor connection
L293L293
1
2
3
4
DC Motor Control (4 of 4)
DC Motor Control (4 of 4)
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DC Motor Feedback (1 of 2)
• The DC motor speed must be fed back to the microcontroller so that it can be controlled. – The motor speed can be fed back by using an optical encoder, infrared
detector, or a Hall-effect sensor.– Basing on the speed feedback, the microcontroller can make adjustment to
increase or decrease the speed, reverse the direction, or stop the motor.
• Assume two magnets are attached to the shaft (rotor) of a DC motor and a Hall-effect transistor is mounted on the armature (stator). – As shown in Figure 8.54, every time the Hall-effect transistor passes
through the magnetic field, it generates a pulse.
• The input capture function of the HCS12 can capture the passing time of the pulse. The time between two captures is half of a revolution. Thus the motor speed can be calculated.
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t
T/2T is the time for one revolution
Magnets
Hall-effecttransistor
Figure 8.54 The output waveform of the Hall effect transistor
DC Motor Feedback (2 of 2)
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VCC
PWM3PP7
4591011NC
10K
VCC
1827
VCC
163
6.8F
614
151312
0.33 F
6.8F
M
VCC
301373 2
1
Hall-effectswitch
All diodes are the same and could be any one of the 1N4000 series
Figure 8.55 Schematic of a HCS12-based motor-control system
PT0
HCS12
L293
A Motor Control System (1 of 4)
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A DC Motor Control System (2 of 4)
• The PWM output from the PP3 pin is connected to one end of the motor whereas the PP7 pin is connected to the other end of the motor. – The circuit is connected so that the motor will rotate clockwise
when the voltage of the PP7 pin is 0 while the PWM output is nonzero (positive).
– The direction of motor rotation is illustrated in Figure 8.56.
• By applying appropriate voltages on PP7 and PP3 (PWM3), the motor can rotate clockwise, counterclockwise, or even stop.
A DC Motor Control System (3 of 4)
• PWM duty cycle controls speed, PTP.7 direction– PTP.7 = 0: clockwise from 0-100% duty cycle, 0 to full speed– PTP.7 = 1; counterclockwise from 100-0% cycle, 0 to full speed
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Motor
L293
A
B
PWM (PP3)
Port Pin (PP7)
clockwise
off off
counterclockwise
A
B
When A = B, torqueapplied to motor = 0
When A B, motor runs
Figure 8.56 The L293 motor driver
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A DC Motor Control System (4 of 4)
• Input capture channel 0 is used to capture the feedback from the Hall-effect transistor.
• When a DC motor is first powered, it takes time for the motor to reach its final speed.
• When a load is added to the motor, it will be slowed down and hence the duty cycle of the PWM3 should be increased to keep the speed constant.
• When the load is reduced, the speed of the motor will be increased and hence the duty cycle of the PWM3 should be decreased.
• A DC motor does not respond to the change of the duty cycle instantaneously. Several cycles must be allowed for the microcontroller to determine if the change of the duty cycle has achieved its effect.
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Example 8.25
• Write a subroutine in C language to measure the motor speed (in rpm) assuming E clock is 16 MHz.
• Solution: – Two consecutive rising edges on the PT0 pin must be captured in
order to measure the motor speed.– Let diff be the difference of two captured edges and the period is
set to 1 ms, then • Speed = 60 × 106 ÷ (2 × diff)
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#include “c:\egnu091\include\hcs12.h”
unsigned int motor_speed (void){
unsigned int edge1, diff, rpm;long int temp;
TSCR1 = 0x90; /* enable TCNT and fast flag clear */TIOS &= IOS0; /* select IC0 function */TSCR2 = 4; /* set TCNT prescale factor to 16 */TCTL4 = 0x01; /* select to capture the rising edge of PT0 */ TFLG1 = C0F; /* cleared C0F flag */while (!(TFLG1 & C0F)); /* wait for the first edge */edge1 = TC0;while (!(TFLG1 & C0F)); /* wait for the second edge */diff = TC0 - edge1;temp = 1000000l / (long)(2 * diff);rpm = temp * 60;return rpm;
}
C Code to Compute Speed