Design and Performance of Prototype Telescope for NuTel project
FED Overview VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Compact Flash Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided.
PPIB and ODMB Status Report Rice University April 19, 2013.
FED Overview
Road to SiD Test beam at LNF (Frascati) BTF 23 – 30 June.
