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Virtual Memory
Chapter 8
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Key Characteristics of Paging/SegmMemory references are dynamically translated into physical addresses at run time
– implication: a process may be moved in and out of main memory and occupy different regions
A process may be broken up into pieces that
– do not need to located contiguously in main memory
– do not need to be all present in main memory during execution
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Execution of a Program
When a process is started, OS brings into main memory a few pieces of the process
Resident set = portion of process that is in main memory
An interrupt is generated when a logical address is needed that is not in main memory
Operating system puts the process in a blocking state
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Execution of a Program [2]
To bring the piece of process that contains the logical address needed into main memory:
– OS issues a disk Read request
– another process is dispatched to run while the disk I/O takes place
– an interrupt is issued when disk I/O completes which causes the operating system to place the affected process in the Ready state
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Advantages of Breaking a Process
More processes may be maintained in main memory– Only load in some of the pieces of each process– With so many processes in main memory, it is
very likely a process will be in the Ready state at any particular time
A process may be larger than all of main memory
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Types of Memory
Real memory– Main memory
Virtual memory– Memory on disk– Allows for effective multiprogramming and relieves
the user of tight constraints of main memory
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Thrashing
To bring a piece of process into main memory, OS must move out a piece of the same/different process
A piece of a process may be moved out just before it is needed
Too high frequency of in/out movements = thrashing
Under thrashing, processor spends most of its time moving pieces rather than executing user instructions
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Principle of Locality
Experience: program and data references within a process tend to clusterOnly a few pieces of a process will be needed over a short period of timePossible to make intelligent guesses about which pieces will be needed in the near future, hence avoid thrashingThis suggests that virtual memory may work efficiently
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Support for Virtual Memory
Hardware– support paging/segmentation-based addressing
Operating system– manage the movement of pages and/or segments
between secondary memory and main memory
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Virtual and physical addressesProgram uses virtual addresses– Addresses local to the
process– Hardware translates
virtual address to physical address
Translation done by the Memory Management Unit– Usually on the same chip
as the CPU– Only physical addresses
leave the CPU/MMU chipPhysical memory indexed by physical addresses
CPU chipCPU
Memory
Diskcontroller
MMU
Virtual addressesfrom CPU to MMU
Physical addresseson bus, in memory
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0–4K4–8K8–12K12–16K16–20K20–24K24–28K28–32K
Paging and page tablesVirtual addresses mapped to physical addresses– Unit of mapping is called a page– All addresses in the same virtual
page are in the same physical page
– Page table entry (PTE) contains translation for a single page
Table translates virtual page number to physical page number– Not all virtual memory has a
physical page– Not every physical page need be
usedExample:– 64 KB virtual memory– 32 KB physical memory
70–4K44–8K
8–12K12–16K
016–20K20–24K24–28K
328–32K32–36K36–40K
140–44K544–48K648–52K-52–56K
56–60K-60–64K
Virtualaddressspace
Physicalmemory
-
------
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Page TableOS keeps a page table for each processEach page table entry contains (at least):– a ‘presence’ bit to indicate whether the page is
present in main memory or not• if present, the number of the frame in main
memory which stores the page– a ‘modify’ bit to indicate if the page has been
altered since it was last loaded into main memory• If its contents have not been changed, the page
does not have to be written to the disk when it needs to be removed from main memory
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Page Table Entries
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Two-Level Scheme [32-bit Address]
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Two-Level Paging Example
A logical address (on 32-bit machine with 4K page size) is divided into:– a page number consisting of 20 bits– a page offset consisting of 12 bitsSince the page table is paged, the page number is further divided into:– a 10-bit page number – a 10-bit page offsetThus, a logical address is as follows:where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table
page number page offset
pi p2 d
10 10 12
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Address Translation in a Two-Level Paging System
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884960
955
...
220657
401
...
1st levelpage table
2nd levelpage tables
...
...
...
...
...
...
...
...
...
mainmemory
...
125613
961
...
Two-level page tablesProblem: page tables can be too large– 232 bytes in 4KB pages
need 1 million PTEsSolution: use multi-level page tables– “Page size” in first page
table is large (megabytes)– PTE marked invalid in first
page table needs no 2nd level page table
1st level page table has pointers to 2nd level page tables2nd level page table has actual physical page numbers in it
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More on two-level page tablesTradeoffs between 1st and 2nd level page table sizes– Total number of bits indexing 1st and 2nd level
table is constant for a given page size and logical address length
– Tradeoff between number of bits indexing 1st and number indexing 2nd level tables
• More bits in 1st level: fine granularity at 2nd level
• Fewer bits in 1st level: maybe less wasted space?
All addresses in table are physical addressesProtection bits kept in 2nd level table
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Two-Level Page-Table Scheme
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Address-Translation Scheme
Address-translation scheme for a two-level 32-bit paging architecture
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Page Table Location
The entire page table may take up too much main memory
Page tables may also be stored in virtual memory
When a process is running, part of its page table is in main memory
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Hashed Page Tables
Common in address spaces > 32 bits
The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location.
Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.
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Hashed Page Table
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Inverted Page Table
One entry for each real page of memoryEntry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that pageDecreases memory needed to store each page table, but increases time needed to search the table when a page reference occursUse hash table to limit the search to one —or at most a few — page-table entries
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Inverted Page TablePer-process page tables may be fairly large– many entries not used
Alternative: inverted page table– common to all processes– one entry for each frame of memory
• process id, VA of page in that frameOS keeps a hash table for each process with mappage no → inverted page table offsetHash collisions must be taken into account
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Inverted Page Tablepage number portion of VA mapped into a hash table using simple hashing functionhash table contains a pointer to inverted page tableone entry in hash table and inverted page table for each real memory page rather than one per virtual page
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Implementing page tables in hardware
Page table resides in main (physical) memoryCPU uses special registers for paging– Page table base register (PTBR) points to the page table– Page table length register (PTLR) contains length of page
table: restricts maximum legal logical addressTranslating an address requires two memory accesses– First access reads page table entry (PTE)– Second access reads the data / instruction from memory
Reduce number of memory accesses– Can’t avoid second access (we need the value from
memory)– Eliminate first access by keeping a hardware cache (called a
translation lookaside buffer or TLB) of recently used page table entries
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Translation Lookaside BufferWith page tables, each virtual memory reference can cause two physical memory accesses– one to fetch the page table– one to fetch the data
Consequence: significant access time overhead
To reduce this performance penalty, modern CPUs contain a high-speed associative memory which stores most recent page# → frame# mappings
This memory is called the Translation LookasideBuffer (TLB)
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TLB OperationGiven a virtual address, processor associatively searches the TLB
If page table entry is present (a hit), the frame number is retrieved and the real address is formed
If page table entry is not found in the TLB (a miss)
– the page number is used to index the process page table
– if page not present in main memory, page fault issued
The TLB is updated to include the new page entry
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Page Size Determinationfactors
– page table size (large pages are better)
– internal fragmentation (small is better)
– characteristics of secondary-memory devices (disks; large is better)
– page fault rate (see next page)
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Page Size AlternativesMultiple page sizes provide the flexibility needed to effectively use a TLB
Large pages can be used for program instructions
Small pages can be used for threads
Most operating system support only one page size
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Example Page Sizes
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Shared PagesShared code– One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems).
– Shared code must appear in same location in the logical address space of all processes
Private code and data– Each process keeps a separate copy of the code and
data– The pages for the private code and data can appear
anywhere in the logical address space
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Shared Pages Example
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SegmentationMemory-management scheme that supports user view of memory A program is a collection of segments. A segment is a logical unit such as:
main program,procedure, function,method,object,local variables, global variables,common block,stack,symbol table, arrays
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Segment Table Entries
Typical Memory Management Format(b) Segmentation only (Stallings Fig 8.2)
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User’s View of a Program
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Logical View of Segmentation
1
3
2
4
1
4
2
3
user space physical memory space
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Segmentation Architecture Logical address consists of a two tuple:
<segment-number, offset>,Segment table – maps two-dimensional physical addresses; each table entry has:– base – contains the starting physical address where the
segments reside in memory– limit – specifies the length of the segment
Segment-table base register (STBR) points to the segment table’s location in memorySegment-table length register (STLR) indicates number of segments used by a program;
segment number s is legal if s < STLR
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Segmentation Architecture (Cont.)
Relocation.– dynamic– by segment table
Sharing.– shared segments– same segment number
Allocation.– first fit/best fit– external fragmentation
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Segmentation Architecture (Cont.)
Protection. With each entry in segment table associate:– validation bit = 0 ⇒ illegal segment– read/write/execute privileges
Protection bits associated with segments; code sharing occurs at segment levelSince segments vary in length, memory allocation is a dynamic storage-allocation problemA segmentation example is shown in the following diagram
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Address Translation Architecture
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Address Translation in a Segmentation System
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Example of Segmentation
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Sharing of Segments
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Combined Paging and Segmentation
Paging is transparent to the programmerPaging eliminates external fragmentationSegmentation is visible to the programmerSegmentation allows for growing data structures, modularity, and support for sharing and protectionEach segment is broken into fixed-size pages
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Combined Segmentation and Paging
Typical Memory Management Format(c) Combined segmentation and paging (Stallings Fig 8.2)
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Address Translation in a Segmentation/Paging System(Stallings Fig 8.13)
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Virtual Memory Policies
key issue: performance (minimize page fault rate)factors affecting performance– fetch policy– replacement policy– resident set management– cleaning policy– load control policy
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Protection Relationshipsbetween Segments
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Fetch PolicyFetch Policy– Determines when a page should be brought into
memory– Demand paging only brings pages into main
memory when a reference is made to a location on the page
• Many page faults when process first started– Prepaging brings in more pages than needed
• More efficient to bring in pages that reside contiguously on the disk
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Replacement Policy
Which page should be selected for replacement?
Page removed should be the page least likely to be referenced in the near future
Most policies predict the future behavior on the basis of past behavior
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Replacement Policy: Frame Locking
Frame Locking– If frame is locked, it may not be replaced– Kernel of the operating system– Control structures– I/O buffers– Associate a lock bit with each frame
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Replacement Algorithms: OptimalOptimal policy– Selects for replacement that page for which the
time to the next reference is the longest– Impossible to have perfect knowledge of future
events
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Replacement Algorithms: LRULeast Recently Used (LRU)– Replaces the page that has not been referenced
for the longest time– By the principle of locality, this should be the page
least likely to be referenced in the near future– Each page could be tagged with the time of last
reference. This would require a great deal of overhead.
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Replacement Algorithms: FIFOFirst-in, first-out (FIFO)– Treats page frames allocated to a process as a
circular buffer– Pages are removed in round-robin style– Simplest replacement policy to implement– Page that has been in memory the longest is
replaced– These pages may be needed again very soon
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Replacement Algorithms: ClockClock Policy– Additional bit called a use bit– When a page is first loaded in memory, the use bit
is set to 0– When the page is referenced, use bit is set to 1– When it is time to replace a page, the first frame
encountered with the use bit set to 0 is replaced.– During the search for replacement, each use bit
set to 1 is changed to 0
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use = 1
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Replacemt Algorithm: Page BufferingLRU, Clock algorithms superior but complexAlternative: page buffering– Replaced page is added to one of two FIFO lists
• free page list if page has not been modified• modified page list
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Resident Set SizeBasic VM issue: how much memory should be allocated to a processFixed-allocation– gives a process a fixed number of pages within
which to execute– when a page fault occurs, one of the pages of that
process must be replacedVariable-allocation– number of pages allocated to a process varies
over the lifetime of the process
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Variable Allocation,Global Scope
Easiest to implement
Adopted by many operating systems
Operating system keeps list of free frames
Free frame is added to resident set of process when a page fault occurs
If no free frame, replaces one from another process
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Variable Allocation,Local Scope
When new process added, allocate number of page frames based on application type, program request, or other criteria
When page fault occurs, select page from among the resident set of the process that suffers the fault
Reevaluate allocation from time to time
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Working Set of a Processworking set with parameter Λ for a process at virtual time t, W(t, Λ), is the set of pages that the process referenced in the last Λ virtual time unitscan consider virtual time as being measured in instruction cyclesconsider each of the variables:– Λ is a window of time over which the process is
observed– the working set size will be a nondecreasing
function of the window size
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Working Set Illustration
2 3
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Basic Working Set StrategyBasic guide for a strategy for resident set size:
– monitor working set of each process
– periodically remove those pages not in the working set of a resident process
– process can only execute if its working set is in main memory
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Working Set Strategy ProblemsFundamental problems:
– the past does not always predict the future
– impractical to obtain true measurement of working set (time stamp every page reference?)
– optimal value of Λ is unknown and is variable
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Page Fault Frequency Strategy
associates a bit with each page in memory and set to 1 when page accessedon page fault,– OS determines the virtual time of last page fault
for the process– if the time is less than some threshold F, then add
a page to resident set of process else discard all pages with a use bit of zero and shrink resident set of process
– reset the use bit on all remaining pages of process to zero
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PFF Strategy [2]can also use two thresholds:– upper threshold to trigger a growth in resident set
size– a lower threshold to trigger a contraction in
resident set sizepoor performance during transient periods when a shift to a new locality– can cause resident set of process to grow before
pages of old locality are expelled
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VSWS StrategyVariable-Interval Sampled Working Set (VSWS)
evaluate working set of process at sampling instances based on virtual timeat start of sampling interval, reset use bits of process’s resident pagesat end of sampling interval, only pages with use bits set are retained for the next interval, all others are discardedduring interval, any faulted pages are added to resident set– set size grows or remains fixed during the interval
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VSWS Strategy [2]
three drivers:
– M: minimum duration of sampling interval
– L: maximum duration of sampling interval
– Q: number of page faults allowed to occur between sampling instances
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VSWS Strategy [3]basic policy:– if virtual time since last sampling instance reaches
L, suspend process and scan bits– if before L is reached, Q page faults occur:
• if virtual time since last sampling instance is less than M, then wait until M is reached to suspend process and scan use bits
• if virtual time since last sampling instance is greater than or equal to M, suspend process and scan use bits
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Cleaning Policydetermine when a modified page should be written to secondary memory:– Demand cleaning
• a page is written out only when it has been selected for replacement
– Precleaning• pages are written out in batches
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Page BufferingBest approach uses page buffering– Replaced pages are placed in two lists
• Modified and unmodified– Pages in the modified list are periodically written
out in batches– Pages in the unmodified list are either reclaimed if
referenced again or lost when its frame is assigned to another page
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Load ControlDetermines the number of processes that will be resident in main memoryToo few processes, many occasions when all processes will be blocked and much time will be spent in waiting/swappingToo many processes will lead to thrashingPr
oces
sor U
tiliz
atio
n
Multiprogramming level
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Process Suspension
If too many processes, which one should be suspended?
Alternatives:
– Lowest priority process
– Faulting process• this process does not have its working set in
main memory so it will be blocked anyway
– Last process activated• this process is least likely to have its working
set resident
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Process Suspension [2]
Alternatives cont’d:– Process with smallest resident set
• this process requires the least future effort to reload
– Largest process• obtains the most free frames
– Process with the largest remaining execution window
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UNIX/Solaris Memory ManagementPaging System
– Page table– Disk block descriptor– Page frame data table– Swap-use table
Page Replacement– refinement of the clock policy
Kernel Memory Allocator– most blocks are smaller than a typical page size
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Data Structures
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Data Structures [2]
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