7/29/2019 Thrmla Modling of Icpackages
1/112
Modeling IC Packages with FLOTHERM & FLOPACK
Package Level Modeling Goals and Challenges
Basic Packaging Concepts
Package Characterization
Introduction to FLOPACK
7/29/2019 Thrmla Modling of Icpackages
2/112
Modeling Goals
Why is package level modeling necessary ? The only reliable way to obtain accurate case temperature
The only reliable way of obtaining accurate junction temperature
Junction temperature drives reliability; Case temperature provided to end-user
7/29/2019 Thrmla Modling of Icpackages
3/112
Modeling Challenges
Keeping up with the rapidly changing field of ICpackaging is difficult, especially for systemdesigners (end-users).
Some modeling assumptions are not obvious Do I model my trace layers in a PBGA discretely?
Can I neglect the bond wires in modeling a PQFP?
Can I represent my thermal vias as a lumped block?
Generating component models is time consumingand tedious
Information about the internal details of a packagemay be difficult to obtain
7/29/2019 Thrmla Modling of Icpackages
4/112
Basic Packaging Concepts
What is an electronics package?
The combination of engineering and manufacturingtechnologies required to convert an electronic circuitinto a manufactured assembly
Martin Miller, Electronic Packaging, Microelectronicsand Interconnection Dictionary
What is an electronics package? (Intelligibledefinition)
An intermediary between the IC chip (die) and thePCB
7/29/2019 Thrmla Modling of Icpackages
5/112
Basic Packaging Concepts
Highly multi-disciplinary field:
Materials
Manufacturing
Thermal Electrical
Functions of a package:
Electrical
Power distribution
Interconnection
Mechanical
Die protection
Thermal
Heat dissipation
7/29/2019 Thrmla Modling of Icpackages
6/112
Basic Packaging Concepts
DieDie enclosure
Substrate
Level 1 interconnect
Level 2 interconnect
PCB
A package need not have all of the above elements
The die, of course, is always present!
7/29/2019 Thrmla Modling of Icpackages
7/112
Basic Packaging Concepts
More expensive
More reliable
Best electrical characteristics (fine
line widths, multiple layers)
Hermetic
Excellent thermal performance
Small number of packages in use
Applications: High-power
processors
Generally, more challenging to
modelCheaper
Less reliable
Non-hermetic
Often need thermal enhancements
Majority of the worlds packages
Applications:ASICs, Logic
chips, Memory chips, low power-
processors
Ceramic PackagesPlastic Packages
Package Classifications:
7/29/2019 Thrmla Modling of Icpackages
8/112
Standard test methods defined by JEDEC areprovided as a basis for comparison betweenvarious packages and devices.
Well defined environments are used to ensurereliability and consistency between vendors.
The thermal resistance values are not meantto and will not predict the performance of a
package in an application-specificenvironment.
Package Characterization
7/29/2019 Thrmla Modling of Icpackages
9/112
Thermal Resistance of a Package:
Defined as the resistance to heat transfer betweentwo specified points.
Tj = temperature at active surface of die (junction)
Tx = temperature at some reference point
P = package power
Package Characterization
P
TT xjjx
7/29/2019 Thrmla Modling of Icpackages
10/112
Package Characterization
ja (Natural Convection)
Most common concept
Defined by JEDEC 51_2 :
Ta = ambient temperature, taken inside aspecific enclosure defined by JEDEC (Still-AirTest)
Measurements taken either with a High-k(2S2P) and Low-k (1S0P) board
P
TT ajja
7/29/2019 Thrmla Modling of Icpackages
11/112
Package Characterization
jma (Forced Convection)
Speeds from 0-1000 LFM
Defined by JEDEC 51_6 :
Ta = ambient temperature, taken upstream inthe wind tunnel
Board orientation is an important factor
P
TT ajjma
7/29/2019 Thrmla Modling of Icpackages
12/112
jc (junction to case resistance) The thermal resistance from the junction to the outside
surface of the package (case) closest to the chip mountingarea when that same surface is properly heat sunk so as tominimize temperature variation across that surface.
Package Characterization
Die
Substrate
PCB
JunctionCase
Ambient
P
TT cjjc
7/29/2019 Thrmla Modling of Icpackages
13/112
Thermal Resistance of a Package
Package Characterization
Convection/Radiation
Convection/Radiation
Conduction
Convection
Conduction
Radiation
Conduction
Junction
Case
qjc
7/29/2019 Thrmla Modling of Icpackages
14/112
jb (junction to case resistance)
The thermal resistance from the junction to theboard.
Package Characterization
P
TT bjjb
7/29/2019 Thrmla Modling of Icpackages
15/112
Thermal Resistance of a Package jc tries to represent the many complex heat flow paths with a single thermal
resistance
Problem is most problematic with PBGAs
Plastic Encapsulant exaggerates temperature gradient on surface
Solder balls and vias increase parasitic losses to the board
Package Characterization
7/29/2019 Thrmla Modling of Icpackages
16/112
Compact Models
Generates Compact Models (Two-resistor and DELPHI)
7/29/2019 Thrmla Modling of Icpackages
17/112
SmartParts Available Today
21 Package Families
5 Ancillary Parts
7/29/2019 Thrmla Modling of Icpackages
18/112
Plastics/Resins Epoxy, FR-4, Polyimide, BT, die attach materials
Metals/Alloys Copper, Solders (Pb/Sn alloys), Kovar, Alloy-42,
Aluminum, Gold, Tungsten, etc.
CeramicsAlumina (Al2O3), AlN, BeO
Semiconductors Silicon, Gallium Arsenide (GaAs)
Packaging Materials
7/29/2019 Thrmla Modling of Icpackages
19/112
Relevant properties of packaging materials:
Conductivity - Usually invariant with temperature Exceptions :Silicon, AlN, BeO
Glass transition temperature for organic materials
(Tg) - Temperature above which material loses its laminatecharacteristics. Typical values: FR-4 = 125 C, BT = 200 C
Coefficient of Thermal Expansion (CTE) - Must matchfor reliability. Particularly bad combinations: Si-FR4, Si-BT, Si-Cu. Goodcombinations: Cu-FR4, Si-Ceramics
Specific Heat
Density
Packaging Materials
Silicon die
BT substrate
Underfill
7/29/2019 Thrmla Modling of Icpackages
20/112
Interconnections
Recall the basic structure of a package:
Die level interconnections (Level 1) Wire Bonding, Tape Adhesive Bonding, Flip Chip
Board level interconnections (Level 2) Pins, Peripheral Leads, Solder Balls
DieDie enclosure
Substrate
Level 1 interconnect
Level 2 interconnect
PCB
7/29/2019 Thrmla Modling of Icpackages
21/112
Interconnections: Level 1
Level 1 Interconnect is the coupling between thedie and the substrate
Objective: to route signals and power to die whileminimizing electrical degradation
Three types of Level 1 Interconnect:
Wire Bonding
Tape Adhesive Bonding (TAB)
Flip-Chip (C4)
7/29/2019 Thrmla Modling of Icpackages
22/112
Interconnections: Level 1Wire Bonding
Traditional technology
Bond wires typically
0.8 - 1.2 mil in diameter
Gold or AluminumAdvantages:
Mature, low cost technology
Reliable
Disadvantages: Peripheral, not area array; low I/O density
Pitch on die limited to usually of 3 mils
Large signal lengths; high self-inductance
Substrate
Die
Bond Wire Pad
on Substrate
7/29/2019 Thrmla Modling of Icpackages
23/112
Modeling Bond Wires Can be ignored in ceramic packages
May be significant in plastic packages with low metal content
Suggested modeling approach: Represent as cuboid with equivalent (volume averaged) orthotropic
conductivity
Interconnections: Level 1Wire Bonding
7/29/2019 Thrmla Modling of Icpackages
24/112
Technology introduced in the 1970s
Popular in Japan, not much in the U.S.
Leadframe is directly bonded to the I/O pads on dieperiphery, in a process known as Inner Lead Bonding
Leadframe is normally attached to a (usuallypolyimide) tape, hence the name
Interconnections: Level 1Tape Adhesive Bonding (TAB)
Die
Bumped die
Polyimide Tape
Cu leadframe
7/29/2019 Thrmla Modling of Icpackages
25/112
Disadvantages:
More expensive today than wire-bonding
Peripheral array, I/O density not high
Advantages:
Short interconnect length, excellent electricalperformance
Can handle up to 2 mil pitch on die periphery
Modeling:
This interconnection can usually be ignored in CFDmodeling (insignificant thermal resistance)
Interconnections: Level 1Tape Adhesive Bonding (TAB)
7/29/2019 Thrmla Modling of Icpackages
26/112
Interconnections: Level 1Flip-Chip Bonding
Has its roots in an IBM technology of the 1960s (called C4)
Did not become popular till late 1980s
Die connected with substrate through solder balls Usually not in regular array
Common solders: 37Pb/63Sn, 95Pb/5Sn
Typical dia ~ 3 mils
Die
Substrate
C4Underfill
7/29/2019 Thrmla Modling of Icpackages
27/112
Disadvantages:
Can have major CTE mismatch problems
Underfill makes rework practically impossible
Higher cost (although this is dropping)
Advantages: Best electrical performance of all methods
Area array leads to highest I/O density
Modeling: Usually have a small, but significant thermal resistance,
especially for ceramic packages.
Negligible spreading in Flip-chip layer
Best modeled as collapsed cuboid with volume averagedconductivity
Interconnections: Level 1Flip-Chip Bonding (C4)
Collapsed Cuboid
Die
Substrate
7/29/2019 Thrmla Modling of Icpackages
28/112
Level 2 interconnect: coupling between thepackage substrate and PCB
Can generally be classified by mechanical
attachment method and I/O arrangement: Surface mount (SMT) : I/Os rest (usually soldered) onPCB surface.
Through-hole(TH): I/O physically penetrate the PCBthrough holes
Interconnections: Level 2
Surface Mount/Peripheral leaded
Through Hole/Area Array
7/29/2019 Thrmla Modling of Icpackages
29/112
Interconnections: Level 2
Three ways of coupling substrate and board:
Pins
Peripheral leads
Solder balls
Interconnect method Mechanical I/O Arrangement
Solder Balls
Peripheral Leads
Pins
Surface Mount,
Through Hole
Surface Mount
Through Hole
Area Array
Peripheral
Area Array
7/29/2019 Thrmla Modling of Icpackages
30/112
These are most commonly surface mounted (exception,Dual In-line Package) in PQFPs, SOPs etc.
Pitches have shrunk to as low as 16 mils (0.4 mm)
I/O counts up to ~ 400
Mature, low cost technology
I/O limits due to peripheral array, co-planarity problems
Leads typically of Copper (older packages, Alloy-42)
Peripheral Leads
7/29/2019 Thrmla Modling of Icpackages
31/112
Advantages: Low cost, mature technology
Easy to inspect for faults
No CTE mismatch problems with FR-4 boards
Disadvantages Long interconnect lengths, high self-inductance
Lead co-planarity problem
Peripheral array; low I/O density
Modeling Peripheral Leads
Gull-wing leads J-leads
7/29/2019 Thrmla Modling of Icpackages
32/112
Modeling advice: Form a critical heat transfer path for peripheral leaded packages
Model as equivalent cuboid of volume averaged orthotropic conductivity.
Modeling leads discretely does not improve model accuracy significantly forpackages with a large number of leads.
Modeling Peripheral Leads
7/29/2019 Thrmla Modling of Icpackages
33/112
Package using solder balls is knownas Ball Grid Array (BGA)
Technology pioneered by IBM in the1960s,
Found wide acceptance in the1990s
BGA use is rising almost
exponentially, especially in the U.S.Array can be peripheral, with
additional central balls
Underfill rarely present
Solder Balls
Solder balls typically of95Pb/5Sn or 37Pb/63Snsolder
Peripheral BallsCentral/Thermal
Balls
7/29/2019 Thrmla Modling of Icpackages
34/112
Advantages of solder ball interconnect:
High I/O density
Excellent electrical performance (low self-inductance)
Self-aligning during reflow, low manufacturing defectrate
Disadvantages:
Difficult to inspect for defects
Possible CTE mismatch
Not cheap (although cost is dropping)
Solder Balls
7/29/2019 Thrmla Modling of Icpackages
35/112
Modeling choices:
Each solder ball discretely, as a cuboid:
Modeling Solder Balls
Actual
solder balls
FLOPACK discrete
solder balls modeled as
cuboids with
equivalent cross-
sectional
area
7/29/2019 Thrmla Modling of Icpackages
36/112
Modeling choices:
As full cuboid (orthotropic)
Modeling Solder Balls
Full Cuboid
Low conductivity
in in-plane directionsHigh conductivity
in through-plane
direction
7/29/2019 Thrmla Modling of Icpackages
37/112
Package using pins is called a Pin GridArray (PGA). (More on PGAs later.....)
Pins are typically made of Kovar (an alloy)
They are often by means of a socket,connecting with the PCB through its ownpins
Pins
Socket
Package pins
Socket pins
7/29/2019 Thrmla Modling of Icpackages
38/112
Most pins have pitches of 50 mils or 100 milsand diameters of about 15 mils
I/O counts of up to ~ 800
Modeling approach:
Ceramic packages: can model as equivalent volumeaveraged cuboid, as ceramic substrate is a good heatspreader
Plastic packages: may need to model as discrete pins,
especially if die size is small
Modeling Pins
7/29/2019 Thrmla Modling of Icpackages
39/112
Modeling ICs
Component Building Blocks
Boards
Heatsinks
JEDEC standard test configurations
7/29/2019 Thrmla Modling of Icpackages
40/112
Term for the piece of semiconductor on which allthe active circuits lie
Usually made of Silicon
Gallium Arsenide is used in some special
applications (microwave/high speed)
Circuitry present within a thin layer on one sideonly, known as active surface
The Die
Active surface
Die body
(typically silicon)
Circuitry
7/29/2019 Thrmla Modling of Icpackages
41/112
Modeling advice: Model as a cuboid with temperature dependent conductivity (for Silicon)
Place collapsed source on active surface to represent heat dissipation
Do not forget to set the source direction inwards, within the die!
The Die
Cuboid
Collapsed source
7/29/2019 Thrmla Modling of Icpackages
42/112
Die Flag: The die is often placed (usually in plastic packages) on a thin metal plate known as
the die flagordie pad.
The die flag serves either a manufacturing or a thermal function, or both.
The die flag is usually made of copper, and is typically larger than the die
Die Flag
DieDie Flag
7/29/2019 Thrmla Modling of Icpackages
43/112
Die Flag:
Because the die flag is metallic, it can act as a veryeffective heat spreader
Modeling the Die Flag:
It is recommended that the die flag be modeleddiscretely
Spreading within the die flag can reduce the thermalresistance of a package by ~ 15 %
This is small, but not insignificant!
Die Flag
7/29/2019 Thrmla Modling of Icpackages
44/112
Die Attach:
The die is often attached to the substrate or thedie pad by an adhesive known as the die attach
It is often made of an epoxy based compound Typical values for die attach: Thickness = 1-2
mils, Conductivity = 1- 2 W/mK
Die Attach
DieDie pad
Die Attach
7/29/2019 Thrmla Modling of Icpackages
45/112
Modeling the Die Attach: Negligible spreading, but thermal resistance can be significant
Model as collapsed cuboid
Die Attach
7/29/2019 Thrmla Modling of Icpackages
46/112
The die is fragile and needs protection (although packageswith bare dies do exist)
Two common means of protection: Overmolding
Capping
Die Protection
7/29/2019 Thrmla Modling of Icpackages
47/112
Overmolding:
Overmold is almost always an epoxy based
compound Low conductivity (0.6 - 0.8 W/mK)
A significant contributor to thermal resistance
To reduce this resistance, a metallic slug issometimes placed inside a plastic package
Overmolding
Overmold
Die
Metal SlugAdhesive
7/29/2019 Thrmla Modling of Icpackages
48/112
Die Capping:
In ceramic packages
Capping seals off the die cavity Cap usually made of aluminum
Model cap as cuboid
May need to consider effects of radiation betweencap and die
Capping
Ceramic substrate
Die
Cap
7/29/2019 Thrmla Modling of Icpackages
49/112
Leadframes:
A characteristic of all peripheral leaded packages
Most packages with leadframes are plastic (PQFP,
SOP, PLCC), but ceramic ones do exist (CQFP) Leadframes normally made of Copper, although
Alloy-42 (a Ferrous alloy) can be found in olderdesigns
Leadframes
Die
Internal
Leadframe
External
Leadframe
Die Flag
7/29/2019 Thrmla Modling of Icpackages
50/112
Leadframe attachment:
Leadframe typically wire bonded to die
TAB bonded in TAB packages When wire bonded, gap between die flag and
leadframe is an important thermal bottleneck
Leadframes
Thermal bottleneck
Bond wire
Die
Die flag
Die attachLeadframe
7/29/2019 Thrmla Modling of Icpackages
51/112
Leadframe modeling: Can be modeled as cuboid blocks with volume averaged, orthotropic conductivity
Take average extent for internal leadframe
Modeling Leadframes
7/29/2019 Thrmla Modling of Icpackages
52/112
Substrates
A substrate is an element on which the die ismounted to and which routes the I/Os from die toPCB
Critical element from thermal standpointPackages without a substrate: PQFP, SOP (e.g)
Substrates:
Ceramic
Organic
7/29/2019 Thrmla Modling of Icpackages
53/112
Ceramic Substrates:
Most commonly made of Alumina (k = 20 W/mK)
For better thermal performance, AlN or BeO also used(k ~ 200 W/mK)
BeO is hazardous, requires special handling Ceramic layers placed together and fired in high
temperature oven
Metal traces usually made of Tungsten orMolybdenum
Ceramic Substrates
7/29/2019 Thrmla Modling of Icpackages
54/112
Ceramic substrate
Ceramic Substrates
7/29/2019 Thrmla Modling of Icpackages
55/112
Advantages:
Hermetic; highly reliable
Fine line widths
Excellent thermal performance
Many (20 +) trace layers possible
Good CTE match with silicon die
Disadvantages:
Require specialized, expensive manufacturingtechnique
CTE mismatch with FR-4 PCB, large packages needunderfill
Ceramic Substrates
7/29/2019 Thrmla Modling of Icpackages
56/112
Applications: High power, heavy duty packages such as processors
Modeling Ceramic Substrates: Relatively high conductivity
Model simply as cuboid blocks
Metal traces can be usually ignored Vias can be usually ignored
Ceramic Substrates
7/29/2019 Thrmla Modling of Icpackages
57/112
Organic substrates:
Present only in plastic packages e.g. Plastic Ball GridArray (PBGA), Plastic Pin Grid Array (PPGA)
Challenging to model
Dielectric made of a plastic based laminate resin;metal is usually copper
Organic Substrates
Metallization
Resin
Die
Organic Substrate
7/29/2019 Thrmla Modling of Icpackages
58/112
Advantages:
Lower dielectric constant than ceramic substrates
Manufacturing technology similar to that for PCBs
Less expensive to manufacture
Excellent CTE match with PCB
Disadvantages:
Limited number of layers
Need thermal enhancements
Poor CTE match with silicon die
Applications:
ASICs, low power processors etc.
Organic Substrates
7/29/2019 Thrmla Modling of Icpackages
59/112
Traces:
Cu traces can be signal layers or power/groundplanes
Typical organic substrates are either 2-layer or 4-layer
2-layer substrate often (but not always) has signallayers only (no power and grounds)
Organic Substrates
Two signal traces
Die
Bond wire
Die Flag
7/29/2019 Thrmla Modling of Icpackages
60/112
Traces: 4-layer substrates have two additional power and ground planes
Organic Substrates
Die
Bond wire
Die Flag
Additional power
and ground planes
7/29/2019 Thrmla Modling of Icpackages
61/112
Modeling traces:
Lumping traces and resin together as a singlecuboid or block-and-plate is not recommended!
Model traces as discrete layers
Within each layer, volume average based on Cucoverage
Organic SubstratesModeling Traces
Cuboids
7/29/2019 Thrmla Modling of Icpackages
62/112
Vias
Originally created for increasing interconnectiondensity in multiple layer PCBs
Technology migrated to organic packages
Today, also used for thermal enhancement(thermal vias)
Organic SubstratesVias
Substrate
Cu plating
Air
7/29/2019 Thrmla Modling of Icpackages
63/112
Via classification: Signal vias
electrical function
can be blind/buried
Thermal vias
serve purely thermal function
usually thru-hole
Organic SubstratesVias
7/29/2019 Thrmla Modling of Icpackages
64/112
Modeling vias:
Typically model only thermal vias
Difficult to model signal vias!
Signal vias may be thermally significant in somepackages (e.g. flip-chip), need investigation.......
Modeling approaches for thermal vias:
as discrete
most refined approach
accounts for constriction resistance
Takes up more grid; introduces large aspect ratio gridcells
Organic SubstratesModeling Thermal Vias
7/29/2019 Thrmla Modling of Icpackages
65/112
Technology for manufacturing organic substratesand PCBs is similar
Compatibility - Detailed Model and Board Model
Need to pay attention to:
Copper Planes
Vias
Connectors
Radiation important in natural convection
Modeling Boards
7/29/2019 Thrmla Modling of Icpackages
66/112
Modeling Boards
FLOPACK PCB macro can create amodel with an arbitrary number of
layers as well as compact or discretevia groups.
Copper Planes Dielectric
7/29/2019 Thrmla Modling of Icpackages
67/112
Heatsinks
If a heatsink is present on detailed packagemodel, it must be modeled accurately forconsistency
Heatsinks:
Parallel Fin Can use FLOTHERM SmartPart, or FLOPACK
Pin Fin
Can use FLOTHERM SmartPart, or FLOPACK
Disk-fin FLOPACK generator
7/29/2019 Thrmla Modling of Icpackages
68/112
Heatsinks: Gridding Tips
Proper gridding important for resolvingboundary layers within heatsinks
Focus on extruded heatsinks (mostcommon)
Transverse and streamwise directions arekey
Transverse direction: Use 3 cells between fins
No extra grid needed within fins
2 cells sufficient to resolve base
7/29/2019 Thrmla Modling of Icpackages
69/112
Heatsinks: Gridding Tips
3 Grid Cells
between Fins
2 Cells
in BaseKeypoint Cells
within Fins
7/29/2019 Thrmla Modling of Icpackages
70/112
Heatsinks: Gridding Tips
Streamwise direction:
Losses = Skin friction + Contraction/Expansion
Transverse gridding resolves Skin Friction Losses
Streamwise gridding critical to resolving
Contraction/Expansion Losses Cluster cells at entrance and exit of extruded heatsink
Normal direction:
Less critical
3-4 cells are usually sufficient
7/29/2019 Thrmla Modling of Icpackages
71/112
Heatsinks: Gridding Tips
Grid clustered at heatsink entrance and exit
Fins
7/29/2019 Thrmla Modling of Icpackages
72/112
Heatsinks: Miscellaneous
Model radiation on heatsink surfaces in natural convection
Do not forget thermal grease (model as collapsed cuboid)
7/29/2019 Thrmla Modling of Icpackages
73/112
JEDEC Test Configurations
JEDEC JC 15.1 subcommittee
Standards to provide Figures of Merit forcomparing package performance(http:///www.jedec.org)
Examples of Standards available:
Still Air Test for Theta-JA (Rja)
Forced Air Test for Theta-JMA (Rjma)
Ring Cold Plate for Theta-JB (Rjb)
Low Conductivity Test Board (1S Board)
High Conductivity Test Board (2S2P Board)
7/29/2019 Thrmla Modling of Icpackages
74/112
JEDEC Test Configurations
Standards being discussed: Cold Plate for Theta-JC
Various standards for new test boards
Other:
Validation beds for computational models
Reporting format for detailed models
Standards for compact modeling
7/29/2019 Thrmla Modling of Icpackages
75/112
JEDEC Standard Test Configurations
7/29/2019 Thrmla Modling of Icpackages
76/112
Ring Cold Plate
Example: Standard for Theta-JB (Ring Cold Plate)
C t M d li
7/29/2019 Thrmla Modling of Icpackages
77/112
Compact Modeling
Introduction
Compact Model Topologies
Deriving 2-Resistor Models
Deriving DELPHI Compact Models
7/29/2019 Thrmla Modling of Icpackages
78/112
Detailed Models
Recall that .....A Detailed Model attempts to capture thermal
behavior of a package by reproducing thephysical structure of the package ascompletely as possible
Wh C t M d l ?
7/29/2019 Thrmla Modling of Icpackages
79/112
Why Compact Models?
Limitations of Detailed Models
Reveal internal (proprietary) construction details of packages
Are computationally demanding due to large grid required
A Compact Model seeks to capture the thermalbehavior of the package accurately ....
... at pre-determined (critical) points (junction, case etc.)
.... by using a reduced set of parameters to represent thepackage
These parameters need not be geometricThe most popular approaches use some sort of thermal
resistance network representation
7/29/2019 Thrmla Modling of Icpackages
80/112
2-Resistor Compact Models:
A significant improvement oversingle-resistor metrics
Simple topology
Can be used in System/Board-level/EDA tools (via IDF 3.0)
Can be derived experimentally orcomputationally
Typical accuracy for most cases is
Top Related