External Use
External Use
Roll-to-Roll Production of Next Generation Display Devices
Neil Morrison Manager R&D, R2R PVD/CVD, Web Coating Group, AEP, Applied Materials
Aimcal, Prague, Czech Republic Date: June 11th, 2012
External Use
Outline Flexible Electronic Devices
– Applications – R2R Cost Reduction Opportunities – Flexible Displays
Substrate Requirements for Flexible Displays – Temperature Stability & Water Absorption – Roughness
R2R Patterning Technologies for TFT Backplanes
Scalable R2R Thin Film Deposition Technologies – SmartWeb PVD Platform – Linear PECVD Sources for Device Grade Silicon Layers
TFT Device Processing & Characterization
Summary
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NREL/ Unisolar
USDC
External Use
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Flexible Electronics, Displays & Energy
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Applications driven by form factor (e.g. shape, size, weight etc.) High throughput low cost manufacturing = R2R Processing
Touch screen (Visual Planet) RFID (PolyIC)
Display (ASU) PV (Unisolar)
OLED (GE)
Battery (IPS)
R2R
R&D
R&D
R&D Underway Capability Evolving
R&D R2R Full Scale Production
R2R
R2R R2R
R2R
External Use
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Flex Electronics - Cost Per Function
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Cost Per Function Critical for Most Applications!
Cost Function
Cost Area
Function
Area
Consumables Cost
Productivity
Utilities Cost
Materials Innovation
Process Innovation
Function Yield
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What is “Flexible Display”? Flexible display can be defined as a technology for manufacturing flat
panel displays on thin, lightweight and flexible substrates
The display is addressed using a backplane – Segmented – Passive Matrix – Active Matrix
The display “effect” is generated by the frontplane – Reflective
• Electrophoretic (E-Text Books & Digital Signage) • Electrowetting
– Emissive • LCD • OLED
The substrate form permits the generation of a new range of products – Conformal, bendable, rugged and potentially rollable.
Samsung
HML
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Substrate Requirements for Flex Display Substrate properties define nature of manufacturing process
– Low Tg → reduces process temperature range for device quality material • Best “lab results” for PV/TFT devices obtained at temperatures > Tg • Substrates undergo dimensional shrinkage especially at T > Tg
– High CTE → influences choice of patterning process • Shrinkage & stress induced deformation of substrate limits patterning accuracy
– High levels of water absorption/roughness → barrier/planarization required
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Property Glass PET PEN PI St. Steel Comments Thickness (mm) 0.05-0.15 0.05-0.15 0.05-0.15 0.05~0.15 0.05-0.18 Transmittance (%) 92 90 87 30-60 - Tg* (℃) 670 80 170 > 300 680 CVD Density (g/cm3) 2.5 1.37 1.36 1.42 7.75 CTE** (PPM / ℃) 3.2 33 20 8-20 17.3 Patterning H2O Absorption (%) - 0.16 0.3 0.4~1.8 - Cost($/m2 ) ?? 2 6 8 5 Application EPD, LCD,
OLED Touch Panel PV, Transp.
Display PV, Emissive Display
(BE OLED / LCD)
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Influence of Surface Roughness on CVD Defects Surface Roughness Can Lead to Growth of Nodules
– Parabolic Shape Explained by Geometrical Shadowing Model • Isotropic Coating Flux • Seed Small Compared with Coating Thickness • Shadowing Described by Conformality Factor
– Through Film “Grain Boundary“ Leads to Current Leakage Path • Reduction in Breakdown Field • Increase in Shunt Density
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Ref:- L. Dubost, et al.: Growth of Nodular Defects During Film Deposition, Journal of Applied Physics, 78 (1995) 3784-3791.
𝐷 =8𝑒𝑒𝑒 + 2𝑒 𝛼𝑒 + 𝑒 1 + 𝛼2
D
d
e
Nodule in Thick Dielectric Layer
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Photolithographic Device Patterning Winding system can be incorporated
in existing tool sets Step & repeat process
– Similar througput to conventional lithography
– Difficult to obtain high resolution pattern alignment due to changes in substrate dimension between individual process steps
– For CTE of 16 ppm/K for PI substrate ∆l = 16 mm/m c.f. 3.3 mm/m for glass
– Alignment further hindered by bowing of substrate in response to layer stress
– Best case resolution currently x 2 worse than on glass
– TFT’s Require ≥ 3 Mask Process – Expensive toolset
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Source : Anvik
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Imprint Lithography:- Paradigm Shift in R2R Patterning
deposit etch imprint
etch mask
Conventional Photo-Lithography SAIL
Source : HP, 2009
deposit
spin resist
align/expose
develop
strip/clean
etch
Vacuum deposition of all
layers
5μm
Multiple mask levels imprinted as single 3D structure
Patterning w/ wet & dry etch
processes
Deposition Imprint Etch
Single Mask, Single Imprint Process with Perfect Source, Gate & Drain Alignment!
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Basic Imprint Lithography Process
~40nm lines on 50μ polyimide
Multilevel structures on flex at 5m/min
5: release
3: emboss
4: cure with UV
1: coated substrate
2: coat with polymer
1μm
4 levels in 0.5 μ step heights
20 µm
0 1 2 3
6: etch
Pixel speed depends linearly on mobility but inversely with the square of channel length
Source : HP, 2009
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Primary Process Module (up to 6 cathodes around
temp controlled drum)
Unwinder Module
Rewinder Module
Interleaf Take-Up
Interleaf Pay-Out
Load Locks
Separately pumped process zones for
excellent gas separation
Expansion Module (thermal process or backside cathodes)
Standardized interfaces for wide variety of cathode choices
SmartWeb® Modular Platform Architecture
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Inline Process Monitoring & Control
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R
Photometry
T
Inline Process Monitoring & Control Necessary for Yield Enhancement in R2R!
Measuring Roller(- Potential)
R F I F
U F
Measurement Roller
Measurement Roller
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PECVD Source Technology for Flex TFT Plasma Requirements
– ne ~ 109-1010 cm-3 for a-Si:H process – ne ~ 1010-1011 cm-3 for μc-Si:H process – Te < 3 eV – Ion Energy < 30 eV
High Dynamic Deposition Rates – a-Si:H process > 10 nm m/min – μc-Si:H process > 35 nm m/min – Other materials > 250 nm m/min
VHF CCP Source (40.68 MHz) – Simulated Performance with CFD
Simple Linear Design – High level of 1D uniformity (< 3 %) – Efficient process gas utilization
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Typical Amorphous Silicon Channel Layer Properties
Sample Hydrogen
Content (at. %) Microstructure Parameter (%)
SiH2/SiH Ratio
Refractive Index
Extinction Coefficient Thickness (nm)
a-Si:H @ 200o C 12.9 12 0.1390 4.109 0.0324 567
a-Si:H @ 250o C 10.4 7 0.0764 4.105 0.0545 447
a-Si:H @ 250o C with H2 Dilution 12.2 5 0.0562 4.114 0.0422 476
Low microstructure parameter necessary for high mobility, high stability TFT´s
a-Si:H @250oC with H2 Dilution
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Microcrystalline N+ Contact Layer
500
1 000
1 500
2 000
2 500
3 000
3 500
4 000
4 500
5 000
5 500
6 000
6 500
7 000
7 500
8 000In
tens
ity (c
nt)
400 420 440 460 480 500 520 540 560 580 600Raman Shift (cm-1)
481
.4
508
.0
520
.0
Xc ~ 57 %, H ~ 5.3 %, ρ ~ 39 Ohm cm
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Typical Layer Properties for PECVD Gate Nitride
Sample Area Si-N
Area Si-H
Area N-H
Bonding Density Si-N
(cm-3)
Bonding Density Si-H
(cm-3)
Bonding Density N-H
(cm-3) Thickness (nm) Refractive
Index
Hydrogen Content (at.%)
SiNx @ 200o C 78.42 1.72 10.4 7.62E+22 4.75E+21 4.01E+22 490 1.764 34.07
SiNx @ 250o C 51.67 0.84 6.02 8.07E+22 3.74E+21 3.72E+22 305 1.783 29.74
2.90 at. %
3.22 at. %
Low Si-H bond density necessary for high performance, high stability TFT´s
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Gate Nitride Breakdown Characteristics
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Breakdown Strength for MIM Structures on Si Wafers ~ 11.7 MV/cm
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Source, Gate and Drain Material Characteristics
Metal Resistivity (µΩ cm) Al 3.2
AlNd 4.5
Cr 20
Cu 2.2
Mo 13
Ti 42
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Ref:- http://www.kobelco.co.jp/english/ktr/pdf/ktr_26/098-102.pdf
Source, Gate & Drain Requirements – Low Resistivity for Reduced RC Delay – Smooth Morphology (No Hillocks) – Low Stress – Good Adhesion – Good Step Coverage – Low Electro-migration
Gate Metal Hillocks
– Al Hillocks Formed at Temps > 200oC • CVD Processes Induce Hillock Growth
– Hillock Density Increases with Tdep
– Hillock Size Increases with Tdep
– Formed in Response to Thermal Strain – Hillock Density Reduced on Alloying
• AlNd Typically Used as Gate Bus Metal – Shunt Density Proportional to Hillock Density
• Increased Yield with Alloyed Al Gate Metals
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Initial Process Baseline on Si Wafers Bottom Gate Device Architecture
– Wafers Pre-Patterned Using Photolithography
– Cr Source, Gate and Drain Used – Typical Channel Dimensions
• W/L ~40/10 & ~80/20 µm – CVD Process Temperature 200oC
High Device Performance – On/Off Current Ratios > 4 x 106 – Threshold Voltage Levels ~ 2.5 V – Mobility ~ 0.7 cm2/Vs – Subthreshold Swing~1 V/Decade
Key CVD Processes Succesfully Baselined!
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External Use
R2R Device Development on PI Foil High Grade, Low Surface Roughness 50 µm PI Foil Used
– Bakeout Required for Mechanical Stabilization and Outgassing – Foil Plasma Pretreated to Enhance Layer Stack Adhesion
TFT Layer Stack Deposition
– Gate Metal Layer Deposited in SmartWeb PVD Tool – CVD Layer Stack Deposited in CVD Lab Tool – Source/Drain Metal Layer Deposited in SmartWeb PVD Tool
Device Patterning
– Imprint Lithography Used to Pattern Stack in Single Step • Coplanar Device Architecture
– Dry/Wet Etch Steps Used to Provide Final Device Structure
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Preliminary R2R Device Performance
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Initial Device Performance Sufficient for Flexible Display Applications!
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Preliminary R2R Device Performance Very Good Device Performance
– On/Off Current Ratio’s ~1.4 x 107 to 2.2 x 108 @ Vg = 20 V • Good Ohmic Contact from n+ to Source/Drain Electrodes
– Low Leakage Currents Typically 10-13 to 10-12 A • Indicative of a High Quality Gate Dielectric
– Threshold Voltage Levels High ~ 5 to 7.5 V • Thicker aSi Channel Layer & Improved Interface Passivation Should Reduce Vt
– Very High Linear Mobility Especially From Short Channel Devices • Up to 0.95 cm2/Vs
– Subthreshold Slope ~ 0.6-1 V/Decade • Further Device Optimization Required
– Moderate Negative Gate Bias Vth Shift • Up to 4 V After 5000 s • Improvement of SiNx/aSi Interface Reqd.
– Charge Trapping at Interface
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Summary R2R manufacturing provides low cost, high throughput route towards
production of flexible electronic devices.
Thermal & mechanical properties of substrate dictate the mode of processing (substrate shrinkage, stress based deformation etc).
Major advances made in R2R device patterning (e.g. imprint lithography).
PVD production platform scaled from 0.4 m up to 1.4 m for flexible electronic device applications.
Production worthy, linear 40.68 MHz plasma source developed for high rate, high uniformity R2R PECVD of aSi, µc-Si and SiNx on a variety of flexible substrates.
High performance flexible TFT devices manufactured using R2R CVD/PVD technology on 50µm thick polyimide.
Yield dependent on particle control and substrate surface roughness.
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Acknowledgements
Andreas Lopp Manuel Campo Armin Reus Uwe Hermanns
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Ulrich Kroemer Tobias Stolley Heike Landgraf Dong Kil Yim
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Roll-to-Roll Processing Fundamentals High productivity processing
– Substrates several km long – Substrate thickness 50-188 μm – Typical width 0.4-1.4 m
Batch based inline coating process – PVD, CVD & thermal evaporation
processes used – Coating drum for substrate
temperature control
Inline process monitoring & control
necessary to maximise productivity – Typical roll speed 0.5-10.0 m/min
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Roll Roll
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