Download - Micro-Controller 8051 Overview MicroProcessor Part II2 MCS-51 Family Overview 3 Pin Compatible 80C51 Family Products.

Micro-Controller 8051Micro-Controller 8051

OverviewOverview

MicroProcessor Part II 2

MCS-51 Family OverviewMCS-51 Family Overview

Pin Compatible

Internal MemoryDEVICE

Program Memory Data MemoryTimer Interrupt

8031AH NONE 128x8 RAM 2 x 16 -Bit 5

8051AH 4Kx8 ROM 128x8 RAM 2 x 16 –Bit 5

8051AHP 4Kx8 ROM 128x8 RAM 2 x 16 –Bit 5

8751H 4Kx8 EPROM 128x8 RAM 2 x 16 –Bit 5

8751H-8 4Kx8 EPROM 128x8 RAM 2 x 16 –Bit 5

8751BH 4Kx8 EPROM 128x8 RAM 2 x 16 –Bit 5

8032AH NONE 256x8 RAM 3 x 16 -Bit 6

8052AH 8Kx8 ROM 256x8 RAM 3 x 16 –Bit 6

8752BH 8Kx8 EPROM 256x8 RAM 3 x 16 –Bit 6

80C51 Family Products80C51 Family Products



OSCILLATOROSCILLATOR&&

TIMMINGTIMMING

CPUCPU

ROM ROM / EPROM/ EPROM RAMRAM

TWO 16-BITTWO 16-BITTIMER/EVENTTIMER/EVENT

COUNTERSCOUNTERS

• PROGRAMMABLEPROGRAMMABLE SERIAL PORTSERIAL PORT• FULL DUPLEX UARTFULL DUPLEX UART• SYNCHRONOUS SHIFTERSYNCHRONOUS SHIFTER

64K BYTE BUS64K BYTE BUSEXPANSIONEXPANSIONCONTROLCONTROL

CONTROL PARALLEL PORTSADDRESS DATA BUS

I/O PINSSERIAL IN / SERIAL OUT

COUNTERSFREQUENCY REFERENCE

PROGRAMM-PROGRAMM-ABLE I/OABLE I/O

Architectural Structure of the 8051 FamilyArchitectural Structure of the 8051 Family

Ext INTERRUPTS

Int INTERRUPTS



Internal Block DescriptionInternal Block Description

Part Contents

Interrupt Control Ext / Internal Interrupts, Masking, Priority

Central Processing Unit Arithmetic / Logical Operation , Control

ROMInternal Program Memory4KB or 8KB : ROM ( = 805X ), EPROM ( = 875X )

RAM Internal Data Memory

4 x 8bit I/O port 4Byte I/O port ( P0 ~ P3 )

Serial Port Rcv/Snd 1 bit data.

Timer / CounterController - Periodic OperationEvent Counting, Check PulseWidthSend periodic Interrupt to CPU

PSEN(Program Strobe Enable )

External Program Control Signal

ALE (Address Latch Enable) Separate Address & Data

EA (External Access)0V : Read PRG from External Memory5V : Read PRG from Internal Memory

RST ( ReSeT) Reset port



Main Features of 8051Main Features of 8051

Part Function

Data Bit-Width 8 Bit

ComputationArithmetic Operation.Logical Operation

Memory SizeData – External Memory 64KB , Internal Memory 128BPGM – External Memory 64KB , Internal Memory 4KB

CommunicationParallel I/O port – 32 ( 4 x 8 Bit )Serial I/O port – Full Duplex UART

Etc2 x 16-Bit Timer , Clock Generator5 Interrupts

UART : Universal Asynchronous Receiver/Transmitter



External Pin DescriptionExternal Pin Description

P0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.0P1.7P1.6P1.5P1.4P1.3P1.2P1.1P1.0

P2.7P2.6P2.5P2.4P2.3P2.2P2.1P2.0

P3.7P3.6P3.5P3.4P3.3P3.2P3.1P3.0

/PSEN

ALE

/EA

/RST

AD7AD7AD6AD6AD5AD5AD4AD4AD3AD3AD2AD2AD1AD1AD0AD0

A15A15A14A14A13A13A12A12A11A11A10A10A9A9A8A8

RDRDWRWRT1T1T0T0

INT1INT1INT0INT0TXDTXDRXDRXD

AAddress/ddress/DData ata BusBusBidirection Bidirection I/O PortI/O Port

AAddress ddress BusBusBidirection Bidirection I/O PortI/O Port

Bidirection Bidirection I/O PortI/O Port

BidirectionBidirection I/O PortI/O Port



TimingTiming

1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4

Bus Cycle

CLK

ALE

/PSEN

PORT2

PORT0

LATCH

Executing From External Program MemoryExecuting From External Program Memory




8051

EPROM

P3 P2

P1 P0

/EA

ALE

LATCH

Addr

/OE/PSEN

DATA(AD7~AD0)

Upper Addr. (A15~A8)

A7~A0

StructureStructure

Lower Addr.



Read Address 0421h(87h)

8051

EPROM

P3 P2

P1 P0

/EA

ALE

LATCH

Addr

/OE/PSEN

Upper Address : 04h

Lower Address : 21h

87h

EA : High : Internal Data MemoryEA : Low : External Data Memory


P0 : Address / Data I/O Port P2 : Address Bus

ExampleExample



8051

RAM

P3 P2

P1 P0

ALE

LATCH

Addr( 0~64KB)

WR /OE

Executing From External Data MemoryExecuting From External Data Memory

RDWR

/CE

216

= 64KB

DECODING

StructureStructure



Timing - ReadTiming - Read 　　

1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4

Bus Cycle

CLK

ALE

PSEN

／ＲＤ

PORT2

PORT0

LATCH




Timing - WriteTiming - Write 　　

1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4

Bus Cycle

CLK

ALE

PSEN

／WR

PORT2

PORT0

LATCH




Instruction DecoderInstruction Decoder

ACCUMULATORACCUMULATOR

ACCUMULA-ACCUMULA-TOR LATCHTOR LATCH

TEMP REG

ARITHMETICARITHMETICLOGICLOGIC UNITUNIT

DECIMALDECIMALADJUSTADJUST

INSTRUCTIONREGISTER

AND DECODER

CO

ND

ITIO

N

CO

ND

ITIO

N

BR

AN

CH

LO

GIC

BR

AN

CH

LO

GIC

FLAGFLAG

INT0INT1CARRYACCTIMER….…

1. Store the OP Code2. Decoding3. Output Control Signal





TEMP REG



INSTRUCTIONREGISTER

AND DECODER

CO

ND

ITIO

N

CO

ND

ITIO

N

BR

AN

CH

LO

GIC

BR

AN

CH

LO

GIC

FLAGFLAG

INT0INT1CARRYACCTIMER….…

Input : 1 or 2 x 8bit data Output : 8bit result data 1. +, - (carry) 2. Increment, Decrement 3. Bit Complement 4. Rotate Left/Right 5. Nibble Exchange 6. *, /

Arithmetic Logic UnitArithmetic Logic Unit





TEMP REG



INSTRUCTIONREGISTER

AND DECODER

CO

ND

ITIO

N

CO

ND

ITIO

N

BR

AN

CH

LO

GIC

BR

AN

CH

LO

GIC

FLAGFLAG

INT0INT1CARRYACC.TIMER…....

AccumulatorAccumulator

1. Store Input Data2. Store Result Data3. Transfer data to Memory and I/O



CPU Timing (I)CPU Timing (I)

Machine Cycle consists of six statessix states ( 12 oscillator periods)

OSCOSC(xtal1)(xtal1)

ALEALE

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6STATESTATE

1-BYTE, 1-CYCLE Instruction (INC a )

2-BYTE, 1-CYCLE Instruction (ADD a , #data )

READ OPCODE READ NEXT OPCODE ( DISCARD)

READ NEXT OPCODE AGAIN

READ OPCODE READ 2nd BYTE

READ NEXT OPCODE




ALEALE


1-BYTE, 2-CYCLE Instruction (INC DPTR )

READ OPCODEREAD NEXT OPCODE ( DISCARD )

READ NEXT OPCODEAGAIN

CPU Timing (II)CPU Timing (II)




ALEALE


1-BYTE, 2-CYCLE Instruction (MOVX)

READ OPCODEREAD NEXT OPCODE ( DISCARD )

NO FETCH NO FETCH

ACCESS EXTERNAL MEMORY

CPU Timing (III)CPU Timing (III)



Memory Organization Memory Organization

Logical Separation of Program and Data Memory

PROGRAM MEMORYPROGRAM MEMORY(READ ONLY)(READ ONLY)

DATA MEMORYDATA MEMORY(READ/WRITE ONLY)(READ/WRITE ONLY)

/EA=0/EA=0ExtExt

/EA=1/EA=1IntInt

ExtExt

ExtExt

/ PSEN/ PSEN / RD/ RD / WR/ WR

00000000

FFFFFFFF FFFFFFFF

0000

FFFF0FFF0FFF

4KB4KB=4096B=4096B

216

IntInt

IntInt IntInt



After reset, the CPU begins execution from location 0000hlocation 0000h

The interrupt causes the CPU to jumpjump to that location, where it

commences execution of the service routinethe service routine

Ex) External Interrupt = 0003h

The lowest 4K bytes of program memory can be either in the On-chip On-chip

ROMROM or in an External ROMExternal ROM ( /EA (=External Access ))( /EA (=External Access ))

The read Strobe to external ROM, /PSEN, is used for all external program fetches. /PSEN is not activate for internal program fetches/PSEN is not activate for internal program fetches.

Program MemoryProgram Memory



0000000000030003

000B000B

00130013

001B001B

00230023

002B002B

8 BYTE8 BYTE

INTERRUPTINTERRUPTLOCATIONSLOCATIONS

RESETRESET

Internal Program Memory Internal Program Memory :: Lower 4KB region of the program memoryLower 4KB region of the program memory

0FFF0FFF

PROGRAMPROGRAMLOCATIONSLOCATIONS

Program MemoryProgram Memory

Longer service routines can be jumpinstruction

If an interrupt service routine is short enough ( as is often the case in controlapplications), it can reside entirely within that the 8-byte interval.



Internal Data Memory space is shown divided into three blocks, which are generally refereed to as the lower 128, the Upper 128, and SFR space

Internal Data Memory Address are always 1 byte wide ( 256Byte )

Data MemoryData Memory

Accessible by indirect Addressing only

0000

FFFF

80807F7F

UPPER 128UPPER 128

LOWER 128LOWER 128

Accessible by direct Addressing

Accessible by direct and indirect addressing

PORTSSTATUS BITCONTROL BITTIMERREGISTERSSTACK POINTACCUMULATOR(ETC..)

Special Function Registers



00 ~ 0700 ~ 07

08 ~ 0F08 ~ 0F

10 ~ 1710 ~ 17

18 ~ 1F18 ~ 1F

20 ~ 2F20 ~ 2F

3F ~ 7F3F ~ 7F

BANKBANKSELECTSELECTBIT INBIT INPSWPSW

1111

1010

0101

0000

4 BANKS OF REGISTER (R0~R7)

BIT-ADDRESSABLE SPACE

The Lower 128 Byte of internal RAMThe Lower 128 Byte of internal RAM

STACK

The Lower 128 Byte of internal RAMThe Lower 128 Byte of internal RAM



R7R6R5R4R3R2R1R0

R7R6R5R4R3R2R1R0

1st REG. BANK1st REG. BANK

2nd REG. BANK2nd REG. BANK

3rd REG. BANK3rd REG. BANK

4th REG. BANK4th REG. BANK

4 X 8 REGISTER BANK4 X 8 REGISTER BANK

4 Banks Of Register4 Banks Of Register



0707 0606 0505 0404 0303 0202 0101 0000 20h20h

0F0F 0E0E 0D0D 0C0C 0B0B 0A0A 0909 0808 21h21h

7777 7676 7575 7474 7373 7272 7171 7070 2Eh2Eh

7F7F 7E7E 7D7D 7C7C 7B7B 7A7A 7979 7878 2Fh2Fh Boolean Instruction ( Bit Operation )Boolean Instruction ( Bit Operation )

AND, OR, CLEAR, SETCOMPLEMENT, MOVE BIT …..

Ex) ANLANL CY, Bit AddressCY, Bit Address

CYCY

Bit AddressBit AddressANDAND CYCY

ANLANL CY, 27h.CY, 27h.33

Before : CY Before : CY 11 (27h) 0 0 1 0 1 1 1 0(27h) 0 0 1 0 1 1 1 0

11CYCYAfter :After :

Bit-Addressable RegisterBit-Addressable Register



Special Function Register (Special Function Register (SFRSFR) - (I)) - (I)

Register MnemonicInternalAddress

Bit/ByteAccess

Port 0 Latch P0 80 Bit

Stack Point SP 81 Byte

Data point ( Word ) DPTR 82 ~ 83 Word

Data point Low Byte DPL 82 Byte

Data point High Byte DPH 83 Byte

Power Control PCON 87 Byte

Timer/Counter Control TCON 88 Bit

Timer/Counter Mode Control TMOD 89 Byte

Timer/Counter 0 Low Byte TL0 8A Byte

Timer/Counter 1 Low Byte TL1 8B Byte

Timer/Counter 0 High Byte TH0 8C Byte

Timer/Counter 0 High Byte TH1 8D Byte

1. Software Control/Operation ( Acc, B, DPTR, PSW, SP )2. Internal Unit Control



Register MnemonicInternalAddress

Bit/ByteAccess

Port 1 Latch P1 90 Bit

Serial Port Control SCON 98 Bit

Serial Data Port SBUF 99 Byte

Port 2 Latch P2 A0 Bit

Interrupt Enable IE A8 Bit

Port 3 Latch P3 B0 Bit

Interrupt Priority Control IP B8 Bit

Program Stats Word PSW D0 Bit

Accumulator Acc or A E0 Bit

B Regster B F0 Bit

Special Function Register (Special Function Register (SFRSFR) - (II)) - (II)



Acc : 8 Bit Accumulator ( Arith./Logical Operation)

B : General Purpose Register : X , /

DPTR : 16Bit Register , 8-bit accessable.

( using address pointer in the transmit External Data transfer )

PSW : 8 Bit -Register,

( carry, Overflow, Parity Flag, Selection of the Register Bank )

SP : Stack Point , 8-Bit Register

Special Function Register (Special Function Register (SFRSFR) - (III) - ) - (III) - Software Control/Operation



Timer/Count

: TH1, TL1, TH0, TL0, TMOD, TCON

Serial Port

: SBUF, SCON, PCON

Interrupt control

: IE, IP

I/O Port

: P0, P1, P2, P3

Special Function Register (Special Function Register (SFRSFR) - (III) - ) - (III) - Internal Unit Control


Chap2 . The Instruction of 8051 FamilyChap2 . The Instruction of 8051 Family

1. Data Transfers Instructions1. Data Transfers Instructions

2. Arithmetic Instructions2. Arithmetic Instructions

3. Logical Instructions3. Logical Instructions

4. Boolean Instructions4. Boolean Instructions

5. Jump Instructions5. Jump Instructions

Instruction SetInstruction Set

5 Groups - 51 Instructions5 Groups - 51 Instructions



Instruction CodeInstruction Code

OP CodeOP Code + + Operand Operand

(Specification of the Operation) (Specification of the Address)

The length of an Instruction depends on 1. The number of operands it involves2. The Way it specifies each operands

The Concepts of OPCODE & OPERANDThe Concepts of OPCODE & OPERAND

1 Byte Instr.



Some Inst. Formats of the Intel 8085Some Inst. Formats of the Intel 8085

Single-byte zero address Instruction

Single-byte one address Instruction

Single-byte two address Instruction

Two-byte one address Instruction

Three-byte one address Instruction

Operand field 1

Operand field 2

Opcode



Every general-purpose computer has its own unique instructionown unique instruction. The Instruction Code is a group of bitsa group of bits that tell the computer to perform

a specific operation.

Operation CodeOperation Code : It define such operations as add, subtract, multiply, shift, and complem

ent. Total number of operations obtained determines the set of machine othe set of machine o

perationsperations. Opcode must consist of at least n bits for a given 2n (or less) distinct o

perations.

Instruction (=Macro-Instruction) = The Sequences of Micro-Instruction



1. The 1. The ImmediateImmediate Addressing Mode Addressing Mode

2. The 2. The DirectDirect Addressing Mode Addressing Mode

3. The 3. The RegisterRegister Addressing Mode Addressing Mode

4. The 4. The Register-SpecificRegister-Specific Addressing Mode Addressing Mode

5. The 5. The Register IndirectRegister Indirect Addressing Mode Addressing Mode

6. The 6. The Register IndexedRegister Indexed Addressing Mode Addressing Mode

1. The 1. The ImmediateImmediate Addressing Mode Addressing Mode

2. The 2. The DirectDirect Addressing Mode Addressing Mode

3. The 3. The RegisterRegister Addressing Mode Addressing Mode

4. The 4. The Register-SpecificRegister-Specific Addressing Mode Addressing Mode

5. The 5. The Register IndirectRegister Indirect Addressing Mode Addressing Mode

6. The 6. The Register IndexedRegister Indexed Addressing Mode Addressing Mode

1. Data Transfer Instructions1. Data Transfer Instructions



The Immediate Addressing ModeThe Immediate Addressing Mode

: Immediate addressing, or perhaps more explicitly, immediate constant addressing, refers to the source being a constant embedded into code.

MovMov a , #1a , #1 ;; { { 7474 0101h } = {h } = { OpcodeOpcode ++ OperandOperand }}

Org 8000h ; set the origin

mov a, #0h ; put 0 into the accumulator

mov a, #11h ; put 11h into the accumulator

mov a, #27 ; put 27(Dec) = 1bh into the accumulator

• Start Addressing : 8000h of external RAM• The sequence of Accumulator : ??h > 00h > 11h > 1bh

Include Data

Register(Acc, SFR), Memory

1.Data Transfer Instruction1.Data Transfer Instruction - - The Immediate Addressing ModeThe Immediate Addressing Mode



Ex ) MOV A , #33h

33h33h

ACC

74743333 IMMEDIATE DATA

OP CODE

MOV DPTR , #1234h

12h 34h12h 34h

PROGRAMPROGRAM MEMORYMEMORY

DPTR

90901212 IMMEDIATE DATA

OP CODE

3434

PROGRAMPROGRAM MEMORYMEMORY DPH DPL

1. Data Transfer Instruction1. Data Transfer Instruction - - The Immediate Addressing ModeThe Immediate Addressing Mode




mov psw, #0 ; select register bank 0

mov r0, #0 ; put 0 into register0


mov psw, #8 ; select register bank 1




mov 70h, #0 ; put 0 into internal register 70

mov 71h, #1 ; put 1 into internal register 71


mov DPTR, #1234h ; place 12h into DPH and 34h DPL

1. Data Transfer Instruction1. Data Transfer Instruction - - The Immediate Addressing ModeThe Immediate Addressing Mode

Ex )



The Direct Addressing ModeThe Direct Addressing Mode : The Direct addressing mode refers to specifying an internal data register or an SFR by its address.

1. Data Transfer Instruction1. Data Transfer Instruction - - The Direct Addressing ModeThe Direct Addressing Mode


mov a, 70h ; copy contents of internal register 70h to a

mov a, #0 ; clear the accumulator

movmov 90h, a90h, a ; copy the accumulator contents to SFR 90h

MOV ……. , ……..

Internal Data Memory Acc, Reg ..Internal Data Memory Internal Data Memory



Ex )

mov A , 33hmov A , 33h

D1D1

ACC

33h33h

DATA

mov 30h , R7mov 30h , R7

R7R7

DATA

DATA DATA MEMORYMEMORY

D1D1 DEDE


30h


DEDE

< Instr. Code >< Instr. Code >mov A , #33h :mov A , #33h : 74 3374 33mov A , 33h :mov A , 33h : E5 E5 E0E0



Ex )

mov 30h , 35hmov 30h , 35h

DATA

PROGRAM PROGRAM MEMORYMEMORY

30h30h

D1D135h35h

3030

3535

D1D1


mov 06h , 00hmov 06h , 00h

DATA


8585 00h00h

DEDE06h06h

0606

0000

DEDE



8585



Port 4 equ 0E8h ; port 4

Port 1 equ 090h ; port 1


mov a, Port4 ; copy the contents of port 4 (= E8h)

mov Port1, a ; copy the acc. contents to contents of po

rt 1

ljmp 8000h ; repeat


Ex )



The Register Addressing ModeThe Register Addressing Mode : The Register addressing mode refers to either the source or the

destination being one of the eight registers of the currently selected register bank.

1. Data Transfer Instruction1. Data Transfer Instruction - - The Register Addressing ModeThe Register Addressing Mode

MOV PSW, #00010000B ; BANK SELECT (BANK1)MOV A, #30h ; Immediate Addressing ModeMOV R1, A ; R1 = 30h

MOV R0, R1 ; REG REG (X)

MOV R3, #20h 1010 1011011 0010 0000



The PSW contains several status bit that reflect the current state of the CPU.

Cf )Cf ) P Program rogram SStatus tatus WWord (ord (PSWPSW))

CY AC F0 RS1 RS0 OV P

PSW7CARRY FLAG RECEIVES CARRY OUTFROM BIT 1 OF ALU OPERANDS

PSW6AUXILARY CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERANDS

PSW5GENERAL PURPOSE STSTUS FLAG

PSW4REGISTER BANK SELECT BIT 1

PSW0PARITY OF ACCUMULATOR SET BY HARDWARE TO 1 IF IT CONTAINSAN ODD NUMBER OF 1S, OTHERWISEIT IS RESET TO 0

PSW1USER DEFINABLE FLAG

PSW2OVERFLOW FLAG SET BY ARITHMETIC OPERATIONS

PSW3REGISTER BANK SELECT BIT 0



The Register-Specific Addressing ModeThe Register-Specific Addressing Mode

: : Some instructions are specific to the registers used.

org 8000h ; set the origin

mov a, #1 ; move the contents 1 into the accumulator

mov 0E0h,#1 ; move the contents 1 into SFR E0h

ljmp 0 ; return to the monitor

1. Data Transfer Instruction1. Data Transfer Instruction - - The Register-Specific Addressing ModeThe Register-Specific Addressing Mode

inc a ; increase contents of accumulator

; 04h

inc DPTR ; increase contents of DPTR

; A3h



movmov a, #1a, #1 ;; move the contents 1 into the accumulatormove the contents 1 into the accumulator

7474

0101


“take the following byte and place in the accumulator”

= the accumulator being the destination is implicitlyimplicitly codedcoded in the instruction





movmov 0E0h, #1 0E0h, #1 ;; move the contents 1 into SFR E0hmove the contents 1 into SFR E0h

7575E0E0


the following 2 bytes

0101

0101

first is the address of register

put the second byte to E0h ( = SFR )

E0hE0h= SFR= SFR



The Register Indirect Addressing ModeThe Register Indirect Addressing Mode : The address of the source or destination is not given explicitly. Instead, the contents of a register is used as the target address.

org 8000h ; set the origin

mov PSW, #0 ; select register 0

mov R0, #78h ; move 78h into register 0

mov @R0, #1 ; set the register whose address is specified in

; the R0 register to the constant 1

ljmp 0 ; return to the monitor

1. Data Transfer Instruction1. Data Transfer Instruction - - The Register Indirect Addressing ModeThe Register Indirect Addressing Mode



mov R0, # 40hmov A, @R0


353540h40h

3535

AccAcc

mov R1, # 50hmov @R1, #ADh


ADAD50h50h

1. Data Transfer Instruction1. Data Transfer Instruction - - The Register Indirect Addressing ModeThe Register Indirect Addressing Mode



1.Data Transfer Instruction1.Data Transfer Instruction - - The Register Indirect Addressing ModeThe Register Indirect Addressing Mode

mov @R0, 40hmov @R0, 40h


555540h40h

5555R1R1



Addressing Mode - Addressing Mode - The Source & Destination of MOV InstructionThe Source & Destination of MOV Instruction

AccAcc

7Fh7Fh

00h00h

FFhFFh

80h80h

R7R6R5R4R3R2R1R0

SFRSFR

REGISTERsREGISTERs

INTERNALINTERNALDATADATAMEMORYMEMORY

mov 10h, 77h

mov a, 77h

mov a, R3

mov 77h, DPL

mov b, a

mov a, 88h

mov 33h, R7



Addressing Mode - Addressing Mode - The Source & Destination of MOV InstructionThe Source & Destination of MOV Instruction

DirectDirect AddressingAddressing

RegisterRegisterR0 ~ R1 R0 ~ R1

AccAcc ImmediateImmediateDataData

IndirectIndirect AddressingAddressing

mov 10h, 77h

mov 33h, R7

mov @R1, #33h

mov a, #33h

mov 3Fh, #33h



The Register Indexed Addressing ModeThe Register Indexed Addressing Mode In this mode, the source or destination address is obtained by adding the value held in the accumulator to the base address. The base address may either be the data pointer DPTR, or the program counter PC.

mov a , @a + DPTRmov a , @a + PC

Base RegisterBase Register + + Index RegisterIndex Register

DPTR, PC Acc

@

Register Indirect Addressing

1. Data Transfer Instruction1. Data Transfer Instruction - - The Register Indexed Addressing ModeThe Register Indexed Addressing Mode




3A

1E73

3F

mov a , @a + DPTR

+

PROGRAM PROGRAM MEMORYMEMORYAccAcc

DPTRDPTR

AccAcc

1EADh1EADh 3F

mov a , #1mov DPTR, #1000hmov a, @a + DPTR

1

1000

31

+


AccAcc

DPTRDPTR

AccAcc

32

30

34

31

33

1000h1000h




Org 2000hmov a , #10hmovc a, @a + PC

10h

2003h

+

AccAcc

PCPC

2000h2000h


83

74

102001h2001h

2002h2002h

2003h2003h

2013h2013h 55

mov mov a , #10ha , #10h

movc movc a , @a+PCa , @a+PC

Current PCCurrent PC

55h55h



1. Data Transfer Instruction1. Data Transfer Instruction - The Stack Oriented Data Transfer - The Stack Oriented Data Transfer

The Stack Oriented Data TransferThe Stack Oriented Data Transfer

: Another form of register indirect addressing is implemented with push and pop instructions. These instructions use the SFR stack pointer (SP)


mov SP , #4Fh ; initialize stack point

mov a, #45h ; put 45h in the accumulator

push acc ; push the accumulator

mov b, #0 ; clear the B register

pop b ; pop top of stack into the B register

push accpush a

; Note that the operand acc is the symbol define to be 0E0h.; ( X )( X ) : it uses the register-specific addressing mode.



The Stack Oriented Data TransferThe Stack Oriented Data Transfer Micro-Controller often manipulates single-bit data signals ( Ex ) pushbutton , a motor driver, Bit-Addressable Access)

1. Data Transfer Instruction1. Data Transfer Instruction - The Bit Oriented Data Transfer - The Bit Oriented Data Transfer


mov C , P1.0 ; move the button state into carry flag

mov P1.1, C ; move the carry flag to the LED

ljump 8000h ; repeat

Architecture

..

..

P1.2P1.1P1.0

..

..

Vcc



Exchange InstructionExchange Instruction

: Exchange Instructions perform powerful two-way data transfers without the need for a temporary storage byte.

Two Exchange operations :

1. Byte-wise XCH

2. Nibble-wise XCHD (exchange digit)

2. Exchange Instruction2. Exchange Instruction

XCH XCH a ,a , <Source><Source>

R0~R7@R0,@R1Direct Address Mode

XCHD a , RRii

@R0,@R1

AccAcc SourceSource

AccAcc SourceSource

ByteByte NibbleNibble



XCH a , 30h

XCH a , R5

15

aa R5R5

aa (30h)(30h)

BeforeBefore

AfterAfter 1578

78

37A5

37 A5

BeforeBefore

AfterAfter

XCH a , @R1

aa @R1@R1

3412

34 12

BeforeBefore

AfterAfter

XCHD a , @R0

78

58 76

aa @R1@R1

56BeforeBefore

AfterAfter

2. Exchange Instruction2. Exchange Instruction



2. Data Processing Instruction2. Data Processing Instruction - Arithmetic Instructions - Arithmetic Instructions

INC/DEC InstructionINC/DEC Instruction

: Register-specific, Register, Direct, Register Indirect Addressing

: Loop Counters, Pointers

Mnemonic :

INC Source Operand : Source Data = Source Data + 1

DEC Source Operand : Source Data = Source Data - 1

INC a

BeforeBefore

AfterAfter

AccAcc CYCY ACAC OVOV PP

FFFF ---- ---- ---- XX

0000 ---- ---- ---- 00



DEC a

BeforeBefore

AfterAfter


0000 ---- ---- ---- XX

FFFF ---- ---- ---- 11

INC 30h INC DPTR DEC DPTR DEC DPLDEC DPH





ADD/SUB InstructionsADD/SUB Instructions

1. ADD a, Source Operand

2. ADDC a, Source Operand

3. SUBB a, Source Operand

AccAcc AccAcc Src DataSrc Data



CYCY

CYCY

Acc, R0~R7Acc, R0~R7@R0, XXh@R0, XXh

#XXh#XXh

16BitC 8BitC8BitC

Multi-Byte AddingMulti-Byte Adding




Ex ) ADD a, #32h

BeforeBefore

AfterAfter


7676 ---- ---- ---- ----

A8A8 ---- ---- 11 00

00111 0110 (76h) 111 0110 (76h) (+)(+) + + 00011 0010 (32h) 011 0010 (32h) (+)(+)-------------------------------------------------------- 11010 1000 (A8h)010 1000 (A8h)

Sign BitSign Bit

Over Flow FlagOver Flow Flag (+)(+) + + (+ )(+ )

-128 ~ + 127-128 ~ + 127

Result Result ( - )( - ) ? ?

PSWPSW




Ex ) ADD a, @R1

BeforeBefore

AfterAfter


8686 ---- ---- ---- ----

E8E8 ---- ---- 00 00

11000 0110 (86h) 000 0110 (86h) (-)(-) + + 00110 0010 (62h) 110 0010 (62h) (+)(+)-------------------------------------------------------- 11110 1000 (E8h)110 1000 (E8h)

Sign BitSign Bit

(-) + (+) = (-)(-) + (+) = (-)O.K.O.K.

Result ( - ) Result ( - )

@R1 = 62h@R1 = 62h



Ex ) ADDC a, 50h

BeforeBefore

AfterAfter


5555 1 1 ---- ---- ----

A3A3 00 00 11 00

00101 0101 (55h) 101 0101 (55h) (+)(+) + + 00100 1110 (4Eh) 100 1110 (4Eh) (+)(+) ++ 1 (+) 1 (+)-------------------------------------------------------- 11010 0011 (A3h)010 0011 (A3h)

Sign BitSign Bit

Result ( - ) Result ( - )

Addr 50h = 4EhAddr 50h = 4Eh

Over Flow FlagOver Flow Flag -128 ~ + 127-128 ~ + 127


For Multi-Byte Add



Ex ) ADDC a, R5

BeforeBefore

AfterAfter


E9E9 0 0 ---- ---- ----

4141 11 11 00 00

11110 1001 (E9h) 110 1001 (E9h) (-)(-) + + 00101 1000 (58h) 101 1000 (58h) (+)(+) ++ 0 (..) 0 (..)-------------------------------------------------------- 1 1 00100 0001 (41h)100 0001 (41h)

Sign BitSign Bit

Result (+ ) Result (+ )

R5 = 58hR5 = 58h

Over Flow FlagOver Flow Flag -128 ~ + 127-128 ~ + 127





Ex ) SUBB a, @R0

BeforeBefore

AfterAfter


5353 1 1 ---- ---- ----

1B1B 0 0 11 00 00

00101011 00110011 (53h) (53h) (+)(+) - - 00011 0111 (37h) 011 0111 (37h) (+)(+) - 1 (+)- 1 (+)-------------------------------------------------------- 00001 1011 (1Bh)001 1011 (1Bh)

Result (+ ) Result (+ )

R0 = 37hR0 = 37h

(+) - (+) = (+)(+) - (+) = (+)O.K.O.K.

For Multi-Byte Sub

01011010 00 1111111010

BarrowBarrow




Multiplication InstructionsMultiplication Instructions

MUL AB AccAccBBAccAccBB

MSB LSB

OV Flag = Set ( if Acc > 255 )

mov a , #31h ; move the 31 into Accumulator

mov b , #10h ; move the 10 into B registermul ab ; Acc X B

3131101010100303

MSB LSB

AccAccBBAccAccBB



DIV AB AccAcc BBAccAcc

BB

OV Flag = Set ( if B Reg = 0 )

mov a , #118 ; move the 31 into Accumulator

mov b , #5 ; move the 10 into B registerdiv ab ; B / Acc

55171733

BBAccAccBB

Division InstructionsDivision Instructions

/

/

Result(portion)

Remainder

7676

AccAcc




Byte-wise Logical OperationsByte-wise Logical Operations

2. Data Processing Instruction2. Data Processing Instruction - Logical Instructions - Logical Instructions

ANLANLORLORLXRLXRL

ANLANLORLORLXRLXRL

CPLCPLCLRCLR

SWAPSWAP

Acc , Acc ,

Direct Addressing ,Direct Addressing ,

AccAcc

R0 ~ R7R0 ~ R7@R0, @R1 ..@R0, @R1 ..Direct AddressingDirect Addressing# Data# Data

AccAcc# Data# Data

DestinationDestination SourceSourceInst.Inst.




CLR ACLR A CPL ACPL A

(CLear Acc ) (ComPlement Acc)

CLR ACLR ACLR ACLR A

ANL ANL Dest, SrcDest, Src

ANL ANL Dest, SrcDest, Src

ANL 37h , #11110000 bANL 37h , #11110000 b

Before (37h) # 01110111 b(37h) # 01110111 b

#11110000 b#11110000 b

After (37h)(37h) #01110000 b#01110000 b

ORL a , R4ORL a , R4

Before (Acc) # 01110111 b(Acc) # 01110111 b

#11110000 b#11110000 b

After (Acc)(Acc) #11110111 b#11110111 b

ORL ORL Dest, SrcDest, Src

ORL ORL Dest, SrcDest, Src

(R4)(R4)

CPL ACPL ACPL ACPL A

Before 10110101 b (B5h) 10110101 b (5Bh)Before

After 00000000 b (00h) 01001010 b (4Ah)After




XRL XRL Dest, SrcDest, Src

XRL XRL Dest, SrcDest, Src

XRL a , @R0XRL a , @R0

Before (Acc) # 10010001 b(Acc) # 10010001 b

(@R0) # 11100011 b(@R0) # 11100011 b

After (Acc)(Acc) # 01110010 b# 01110010 b

XRL P1 , #51hXRL P1 , #51h

Before (P1) # 01010011 b(P1) # 01010011 b

# 01010001 b# 01010001 b

After (P1)(P1) # 00000010 b# 00000010 b




RL AccRL Acc

RL AccRL Acc

RR AccRR Acc

RR AccRR Acc

(Rotate Acc Left ) (Rotate Acc Right )

MOV a , # 37hMOV a , # 37hRL aRL aRL aRL aRL aRL aRL a RL a

MOV a , # 37hMOV a , # 37hRR aRR aRR aRR aRR aRR aRR a RR a

a = # 73h a = # 73h a = # 73h a = # 73h




RLC AccRLC Acc

RLC AccRLC Acc

(Rotate Acc & Carry Left )

RRC AccRRC Acc

RRC AccRRC Acc

(Rotate Acc & Carry Right )

CY CY

BeforeAfter

CY Acc

1 000110010 00110011

CY Acc

1 100110000 11001100

BeforeAfter




SWAP AccSWAP Acc

SWAP AccSWAP Acc

(SWAP Acc)

BeforeAfter

Acc

1100001100111100



2. Data Processing Instruction2. Data Processing Instruction - Boolean Instructions - Boolean Instructions

• Bit Operation = Bit Operation = Carry FlagCarry Flag ( CY ) = ( CY ) = Bit AccumulatorBit Accumulatorcf) Byte Operation = Accumulatorcf) Byte Operation = Accumulator

Bit OperationBit Operation

ANLANL C, Bit AddressC, Bit Address Ex) ANL C, 20h.5Ex) ANL C, 20h.5

ORLORL C, Bit AddressC, Bit Address Ex) ORL C, A.7Ex) ORL C, A.7

CPLCPL C C Ex) CPL CEx) CPL CBit AddressBit Address Ex) CPL 23h.7Ex) CPL 23h.7

SETSET CC Ex) SET CEx) SET CBit AddressBit Address Ex) SET 40hEx) SET 40h

CLRCLR CC Ex) CLR CEx) CLR CBit AddressBit Address Ex) CLR 28h.0Ex) CLR 28h.0

Bit Addressable RangeCY



2. Data Processing Instruction2. Data Processing Instruction - Boolean Instructions - Boolean Instructions

Bit TransferBit Transfer Direct AddressCY

MOVMOV C, Bit AddressC, Bit Address Ex) MOV C, 20h.5Ex) MOV C, 20h.5

Before CY Before CY 00(20h) 10(20h) 10110110001100

After CY After CY 11

MOVMOV Bit Address, CBit Address, C Ex) MOV 26h.0, C Ex) MOV 26h.0, C

Before CY Before CY 11 (26h.0) 1100001(26h.0) 110000100

After (26h.0) 1100001After (26h.0) 110000111



2. Data Processing Instruction2. Data Processing Instruction

Program CounterProgram Counter

On Power-On-Reset : PC is RESET ( 0000h )On Power-On-Reset : PC is RESET ( 0000h )

1 Byte Instruction Fetch : PC = Current PC + 11 Byte Instruction Fetch : PC = Current PC + 1

The address pointer of next instructionThe address pointer of next instruction

1. Branch Instructions1. Branch Instructions2. Subroutine Calls2. Subroutine Calls3. Interrupts3. Interrupts

Program Flow Control InstructionsProgram Flow Control Instructions



2. Data Processing Instruction2. Data Processing Instruction - Unconditional Jump Instructions - Unconditional Jump Instructions

1. SJMPSJMP < Realtive Address > : Short Jump2. AJMPAJMP < Address 11 > : Absolute Jump3. LJMPLJMP < Address 16 > : Long Jump4. JMPJMP @A+DPTR : Long Jump ( Indexed Addressing )

1. Unconditional Jump Instructions1. Unconditional Jump Instructions



1. SJMPSJMP < Realtive Address > : Short Jump


Signed 8 Bit (-128 ~ +127)

PROGRAMPROGRAM MEMORYMEMORY

8080

0606

????

051Eh

051Fh

0520h

0526h

0520h +

0526h

SJMP 06h




Org 0300h

SSJMPJMP BOT BOT

…

CAACAA : MOVE A, R1

…

…

BOTBOT : INC A

….

….

RANGE-128 ~ 127

User : User : JMPJMP

Compiler Compiler ( If Range (-128 ~ 127 ))( If Range (-128 ~ 127 ))

SJMPSJMP


Compiler Compiler ( If Range (-128 ~ 127 ))( If Range (-128 ~ 127 ))

SJMPSJMP





2. AJMPAJMP < Address 11 > : Absolute Jump

2121

D2D2

????

083Fh

0840h

0841h

09D2h

AJMP 01D2h

01D2 = 0000 0001 1101 0010

0841 = 0000 1000 0100 0001

09D2 <= 0000 1001 1101 0010


11 Bit Address => Jump range ( ~ 2KB )Saving 1 Byte ( cf. LJMP : 2 Byte )



3. LJMPLJMP < Address 16 > : Long Jump


0202

0A0A

3E3E

0056h

0057h

0058h

0A3Eh

0A3Fh

LJMP 0A3Eh

3BYTE

PC : 0A3EPC : 0A3E



Org 0300h

LLJMPJMP BOT BOT

…

CAACAA : MOVE A, R1

…

…

BOTBOT : INC A

….

….

RANGE

~ xxx


Compiler Compiler ( If Range :( If Range : over -128 ~ 127 )over -128 ~ 127 )

LJMPLJMP


Compiler Compiler ( If Range :( If Range : over -128 ~ 127 )over -128 ~ 127 )

LJMPLJMP





4. JMPJMP @A+DPTR : Long Jump ( Indexed Addressing )

737303A7

041C

JMPJMP @A+DPTR

0C 0C 0410 0410

+

AccAcc DPTRDPTR

PCPC



2. Data Processing Instruction2. Data Processing Instruction - - Conditional Jump InstructionsConditional Jump Instructions

2. Conditional Jump Instructions2. Conditional Jump Instructions

1. JZJZ < Relative Address > : 2. JNZJNZ < Relative Address > : 3. JCJC < Relative Address > : 4. JNCJNC < Relative Address > : 5. JBJB < Bit > , < Relative Address > :6. JNBJNB < Bit > , < Relative Address > :7. JBCJBC < Bit > , < Relative Address > :8. CJNECJNE A , Direct , < Relative Address > :9. CJNECJNE A, #Data , < Relative Address > :10. CJNECJNE Rn , #Data , < Relative Address > :11. CJNECJNE @Ri , #Data , < Relative Address > :12. DJNZDJNZ Rn , < Relative Address > :13. DJNZDJNZ Direct , < Relative Address > :



2. Data Processing Instruction2. Data Processing Instruction - - Call & Return InstructionsCall & Return Instructions

3. Call & Return Instructions3. Call & Return Instructions

1. ACLLACLL < Address 11 > : ( Range : 2KByte )2. LCALLLCALL < Address 16 > : ( Range : 64KByte )3. RETRET : Pop program counter off the stack4. RETIRETI : Pop program counter off the stack

: and reset interrupt hardware.


Chap3. Timer Interrupt & OptimizeChap3. Timer Interrupt & Optimize

0000000000030003

000B000B

00130013

001B001B

00230023

002B002B

8 BYTE8 BYTE

INTERRUPTINTERRUPTTABLETABLE

RESETRESET

0FFF0FFF

PROGRAMPROGRAMLOCATIONSLOCATIONS

Timer InterruptTimer Interrupt

Longer service routines can be jumpinstruction

If an interrupt service routine is short enough ( as is often the case in controlapplications), it can reside entirely within that the 8-byte interval.IE0

TF0

IE1

TF1

RI+TI



TCON RegisterTCON Register

Function

IE0TF1 TR1 TF0 TR0 IE1 IT1 IT0

(MSB) (LSB)

NAME

TFx

Timer x over flow Flag

Set by hardware on timer/counter overflow

Cleared by hardware

when processor vectors to interrupt routine

TRxTimer x Run control bit

Set/Cleared by software to turn timer/counter on/off



TCON Register TCON Register

Function

TF1 TR1 TF0 TR0 IE0IE1 IT1 IT0

(MSB) (LSB)

NAME

IExInterrupt x Edge flag

Set by hardware when external interrupt edge detected

Cleared when interrupt processed.

ITx

Interrupt 1 Type control bit

Set/Cleared by software to specify

Falling edge/low level triggered external interrupts



TMOD Register - Operation ControlTMOD Register - Operation Control

TIMER1 TIMER2

M1 M1M0GATE C/T GATE C/T M0

(MSB) (LSB)

GATE Gating Control

When Set Timer/Counter “x”is enabled

Only while “INTx”pin is high and “TRx” control pin is set

When Cleared Timer “x” is enabled

Whenever “TRx” control bit is set

C/T Timer or Counter Selector

Cleared for Timer operation (input from internal system clock).

Set for Counter operation (input from “Tx” input pin)



TMOD Register - Operating Mode Control (0 , 1, 2 )TMOD Register - Operating Mode Control (0 , 1, 2 )

TIMER1 TIMER2

GATE C/T GATE C/TM1 M1M0 M0

(MSB) (LSB)

8048 TIMER : ”TLx” serves as 5-bit prescaler.

16-bit Timer/Counter : “THx” and “TLx” are cascaded

“THx” hold a value which is to be Reloaded into “TLx” each time it overflows

M1 M0 Function

0 0

0 1

1 0



TMOD Register - Operating Mode Control (Mode 3)TMOD Register - Operating Mode Control (Mode 3)

TIMER1 TIMER2

GATE C/T GATE C/TM1 M1M0 M0

(MSB) (LSB)

TL0 is an 8-bit timer-counter

Controlled by the standard Timer 0 control bits

TH0 is an 8-bit timer

Only Controlled by Timer 1 control bits (TCON.TR1)

Timer Function

Timer 0

Timer-counter 1 stoppedTimer 1



osc 12

1/ TC CONTROL

TL1

(5BITS)

TH1

(8BITS)TF1 INTERRUPT

GATE

PININT1

TR1

T1 PIN

0/ TC

Timer/Counter 1 Mode 0:13-bit Counter

Timer Mode - Mode 0



osc 12

1/ TC CONTROL

TL1

(8BITS)

TH1


GATE

PININT1

TR1

T1 PIN

0/ TC

Timer/Counter 1 Mode 1:16-bit Counter

Timer Mode - Mode 1


TL1


TH1

(8BITS)

RELOAD

osc 12

1/ TC CONTROL

GATE

PININT1

TR1

T1 PIN

0/ TC

Timer/Counter 1Mode 2:8-bit Auto-Reload


Timer Mode - Mode 2



Timer Mode - Mode 3

TH0

(8BITS)

CONTROLTR1

1/12 fOSCINTERRUPT

TL0

(8BITS)INTERRUPT

osc 12

1/ TC CONTROL

GATE

PININT0

TR0

T0 PIN

0/ TCTimer/Counter 0 Mode 3 : Two 8-bit Counters

TF1

TF0



0000000000030003

000B000B

00130013

001B001B

00230023

INTERRUPT VECTOR TABLEINTERRUPT VECTOR TABLE

EXTERNAL PROGRAMEXTERNAL PROGRAMMEMORY (ROM)MEMORY (ROM)

Vector Table (Single Board Case)Vector Table (Single Board Case)

IE0

TF0

IE1

TF1

LJMP 80F0H

LJMP 80F3H

LJMP 80F6H

LJMP 80F9H

In Our Single - Board Case, Actual interrupt service routinehave to be exist in the data memory area(RAM address range: 8000H ~ 9FFFH)