Micro-Controller 8051 Overview MicroProcessor Part II2 MCS-51 Family Overview 3 Pin Compatible 80C51...

download Micro-Controller 8051 Overview MicroProcessor Part II2 MCS-51 Family Overview 3 Pin Compatible 80C51 Family Products.

of 97

  • date post

    04-Jan-2016
  • Category

    Documents

  • view

    214
  • download

    0

Embed Size (px)

Transcript of Micro-Controller 8051 Overview MicroProcessor Part II2 MCS-51 Family Overview 3 Pin Compatible 80C51...

  • Micro-Controller 8051Overview

    MicroProcessor Part II

  • MCS-51 Family Overview Pin Compatible 80C51 Family Products

    MicroProcessor Part II

    DEVICE

    Internal Memory

    Timer

    Interrupt

    Program Memory

    Data Memory

    8031AH

    NONE

    128x8 RAM

    2 x 16 -Bit

    5

    8051AH

    4Kx8 ROM

    128x8 RAM

    2 x 16 Bit

    5

    8051AHP

    4Kx8 ROM

    128x8 RAM

    2 x 16 Bit

    5

    8751H

    4Kx8 EPROM

    128x8 RAM

    2 x 16 Bit

    5

    8751H-8

    4Kx8 EPROM

    128x8 RAM

    2 x 16 Bit

    5

    8751BH

    4Kx8 EPROM

    128x8 RAM

    2 x 16 Bit

    5

    8032AH

    NONE

    256x8 RAM

    3 x 16 -Bit

    6

    8052AH

    8Kx8 ROM

    256x8 RAM

    3 x 16 Bit

    6

    8752BH

    8Kx8 EPROM

    256x8 RAM

    3 x 16 Bit

    6

  • MCS-51 Family OverviewOSCILLATOR&TIMMING

    CPU

    ROM / EPROM

    RAM

    TWO 16-BITTIMER/EVENTCOUNTERS PROGRAMMABLE SERIAL PORT FULL DUPLEX UART SYNCHRONOUS SHIFTER64K BYTE BUSEXPANSIONCONTROLCONTROLPARALLEL PORTSADDRESS DATA BUSI/O PINSSERIAL IN / SERIAL OUTCOUNTERSFREQUENCY REFERENCE

    PROGRAMM-ABLE I/O

    Architectural Structure of the 8051 FamilyExt INTERRUPTSInt INTERRUPTS

    MicroProcessor Part II

  • MCS-51 Family OverviewInternal Block Description

    MicroProcessor Part II

    Part

    Contents

    Interrupt Control

    Ext / Internal Interrupts, Masking, Priority

    Central Processing Unit

    Arithmetic / Logical Operation , Control

    ROM

    Internal Program Memory

    4KB or 8KB : ROM ( = 805X ), EPROM ( = 875X )

    RAM

    Internal Data Memory

    4 x 8bit I/O port

    4Byte I/O port ( P0 ~ P3 )

    Serial Port

    Rcv/Snd 1 bit data.

    Timer / Counter

    Controller - Periodic Operation

    Event Counting, Check PulseWidth

    Send periodic Interrupt to CPU

    PSEN

    (Program Strobe Enable )

    External Program Control Signal

    ALE (Address Latch Enable)

    Separate Address & Data

    EA (External Access)

    0V : Read PRG from External Memory

    5V : Read PRG from Internal Memory

    RST ( ReSeT)

    Reset port

  • MCS-51 Family OverviewMain Features of 8051UART : Universal Asynchronous Receiver/Transmitter

    MicroProcessor Part II

    Part

    Function

    Data Bit-Width

    8 Bit

    Computation

    Arithmetic Operation.

    Logical Operation

    Memory Size

    Data External Memory 64KB , Internal Memory 128B

    PGM External Memory 64KB , Internal Memory 4KB

    Communication

    Parallel I/O port 32 ( 4 x 8 Bit )

    Serial I/O port Full Duplex UART

    Etc

    2 x 16-Bit Timer , Clock Generator

    5 Interrupts

  • MCS-51 Family OverviewExternal Pin DescriptionP0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.0P1.7P1.6P1.5P1.4P1.3P1.2P1.1P1.0P2.7P2.6P2.5P2.4P2.3P2.2P2.1P2.0P3.7P3.6P3.5P3.4P3.3P3.2P3.1P3.0/PSEN

    ALE

    /EA

    /RSTAD7AD6AD5AD4AD3AD2AD1AD0A15A14A13A12A11A10A9A8RDWRT1T0INT1INT0TXDRXDAddress/Data BusBidirection I/O PortAddress BusBidirection I/O PortBidirection I/O PortBidirection I/O Port

    MicroProcessor Part II

  • MCS-51 Family OverviewTiming1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4Bus CycleCLK

    ALE

    /PSEN

    PORT2

    PORT0LATCHExecuting From External Program Memory

    MicroProcessor Part II

  • MCS-51 Family OverviewExecuting From External Program Memory8051EPROM

    P3P2P1P0/EA

    ALELATCHAddr/OE/PSENDATA(AD7~AD0)Upper Addr. (A15~A8)A7~A0StructureLower Addr.

    MicroProcessor Part II

  • MCS-51 Family OverviewRead Address 0421h(87h)Upper Address : 04hLower Address : 21h87hEA : High : Internal Data MemoryEA : Low : External Data MemoryExecuting From External Program MemoryP0 : Address / Data I/O Port P2 : Address BusExample

    MicroProcessor Part II

  • MCS-51 Family Overview8051RAM

    P3P2P1P0ALELATCHAddr( 0~64KB)WR /OEExecuting From External Data MemoryRDWR/CE 216= 64KBDECODINGStructure

    MicroProcessor Part II

  • MCS-51 Family OverviewTiming - Read1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4Bus CycleCLK

    ALE

    PSEN

    PORT2

    PORT0LATCHExecuting From External Data Memory

    MicroProcessor Part II

  • MCS-51 Family OverviewTiming - Write1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4Bus CycleCLK

    ALE

    PSEN

    WR

    PORT2

    PORT0LATCHExecuting From External Data Memory

    MicroProcessor Part II

  • MCS-51 Family OverviewInstruction DecoderACCUMULATORACCUMULA-TOR LATCHTEMP REG

    ARITHMETICLOGIC UNIT

    DECIMALADJUSTINSTRUCTIONREGISTERAND DECODERCONDITION BRANCH LOGICFLAGINT0INT1CARRYACCTIMER.

    1. Store the OP Code2. Decoding3. Output Control Signal

    MicroProcessor Part II

  • MCS-51 Family OverviewACCUMULATORACCUMULA-TOR LATCHTEMP REG

    ARITHMETICLOGIC UNIT

    DECIMALADJUSTINSTRUCTIONREGISTERAND DECODERCONDITION BRANCH LOGICFLAGINT0INT1CARRYACCTIMER.

    Input : 1 or 2 x 8bit data Output : 8bit result data 1. +, - (carry) 2. Increment, Decrement 3. Bit Complement 4. Rotate Left/Right 5. Nibble Exchange 6. *, /Arithmetic Logic Unit

    MicroProcessor Part II

  • MCS-51 Family OverviewAccumulator1. Store Input Data2. Store Result Data3. Transfer data to Memory and I/O

    MicroProcessor Part II

  • MCS-51 Family OverviewCPU Timing (I)Machine Cycle consists of six states ( 12 oscillator periods)OSC(xtal1)ALES1 S2 S3 S4 S5 S6S1 S2 S3 S4 S5 S6STATE1-BYTE, 1-CYCLE Instruction (INC a )2-BYTE, 1-CYCLE Instruction (ADD a , #data )READ OPCODEREAD NEXT OPCODE ( DISCARD)READ NEXT OPCODE AGAIN READ OPCODEREAD 2nd BYTEREAD NEXT OPCODE

    MicroProcessor Part II

  • MCS-51 Family OverviewOSC(xtal1)ALES1 S2 S3 S4 S5 S6S1 S2 S4 S3 S5 S6STATE1-BYTE, 2-CYCLE Instruction (INC DPTR )READ OPCODEREAD NEXT OPCODE ( DISCARD )READ NEXT OPCODEAGAINCPU Timing (II)

    MicroProcessor Part II

  • MCS-51 Family OverviewOSC(xtal1)ALES1 S2 S3 S4 S5 S6S1 S2 S4 S3 S5 S6STATE1-BYTE, 2-CYCLE Instruction (MOVX)READ OPCODEREAD NEXT OPCODE ( DISCARD )NO FETCHNO FETCHACCESS EXTERNAL MEMORYCPU Timing (III)

    MicroProcessor Part II

  • MCS-51 Family OverviewMemory Organization Logical Separation of Program and Data Memory PROGRAM MEMORY(READ ONLY)DATA MEMORY(READ/WRITE ONLY)/EA=0Ext/EA=1IntExtExt/ PSEN/ RD/ WR0000FFFFFFFF00FF0FFF4KB=4096B216IntIntInt

    MicroProcessor Part II

  • MCS-51 Family OverviewAfter reset, the CPU begins execution from location 0000h

    The interrupt causes the CPU to jump to that location, where it commences execution of the service routine Ex) External Interrupt = 0003h

    The lowest 4K bytes of program memory can be either in the On-chip ROM or in an External ROM ( /EA (=External Access ))

    The read Strobe to external ROM, /PSEN, is used for all external program fetches. /PSEN is not activate for internal program fetches.Program Memory

    MicroProcessor Part II

  • MCS-51 Family Overview00000003000B0013001B0023002B8 BYTEINTERRUPTLOCATIONSRESETInternal Program Memory : Lower 4KB region of the program memory0FFFPROGRAMLOCATIONSProgram MemoryLonger service routines can be jumpinstructionIf an interrupt service routine is short enough ( as is often the case in controlapplications), it can reside entirely within that the 8-byte interval.

    MicroProcessor Part II

  • MCS-51 Family OverviewInternal Data Memory space is shown divided into three blocks, which are generally refereed to as the lower 128, the Upper 128, and SFR spaceInternal Data Memory Address are always 1 byte wide ( 256Byte )Data MemoryAccessible by indirect Addressing only00FF807FUPPER 128LOWER 128Accessible by direct AddressingAccessible by direct and indirect addressingPORTSSTATUS BITCONTROL BITTIMERREGISTERSSTACK POINTACCUMULATOR(ETC..)Special Function Registers

    MicroProcessor Part II

  • MCS-51 Family Overview00 ~ 0708 ~ 0F10 ~ 1718 ~ 1F20 ~ 2F3F ~ 7FBANKSELECTBIT INPSW111001004 BANKS OF REGISTER (R0~R7)BIT-ADDRESSABLE SPACEThe Lower 128 Byte of internal RAMSTACKThe Lower 128 Byte of internal RAM

    MicroProcessor Part II

  • MCS-51 Family OverviewR7R6R5R4R3R2R1R0R7R6R5R4R3R2R1R01st REG. BANK2nd REG. BANK3rd REG. BANK4th REG. BANK4 X 8 REGISTER BANK4 Banks Of Register

    MicroProcessor Part II

  • MCS-51 Family Overview070605040302010020h0F0E0D0C0B0A090821h77767574737271702Eh7F7E7D7C7B7A79782FhBoolean Instruction ( Bit Operation )AND, OR, CLEAR, SETCOMPLEMENT, MOVE BIT ..Ex)ANLCY, Bit AddressANLCY, 27h.3Before : CY 1 (27h) 0 0 1 0 1 1 1 01CYAfter :Bit-Addressable Register

    MicroProcessor Part II

  • MCS-51 Family OverviewSpecial Function Register (SFR) - (I)1. Software Control/Operation ( Acc, B, DPTR, PSW, SP )2. Internal Unit Control

    MicroProcessor Part II

    Register

    Mnemonic

    Internal Address

    Bit/Byte Access

    Port 0 Latch

    P0

    80

    Bit

    Stack Point

    SP

    81

    Byte

    Data point ( Word )

    DPTR

    82 ~ 83

    Word

    Data point Low Byte

    DPL

    82

    Byte

    Data point High Byte

    DPH

    83

    Byte

    Power Control

    PCON

    87

    Byte

    Timer/Counter Control

    TCON

    88

    Bit

    Timer/Counter Mode Control

    TMOD

    89

    Byte

    Timer/Counter 0 Low Byte

    TL0