IRFR3707ZPbF IRFU3707ZPbF
VDSS 30V
RDS(on) max 9.5m
Qg 9.6nC
1 2016-5-31
Absolute Maximum Ratings Symbol Parameter Max. Units
VDS Drain -to-Source Voltage 30 V
VGS Gate-to-Source Voltage ± 20 V
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 56
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 39 A IDM Pulsed Drain Current 220
PD @TC = 25°C Maximum Power Dissipation 50 W
PD @TC = 100°C Maximum Power Dissipation 25 W
Linear Derating Factor 0.33 W/°C
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds (1.6mm from case) 300
D- Pak IRFR3707ZPbF
G D S
Gate Drain Source
Applications High Frequency Synchronous Buck Converters for Computer Processor Power High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial Use
G
I- Pak IRFU3707ZPbF
HEXFET® Power MOSFET
Base part number Package Type Standard Pack
Form Quantity
IRFU3707ZPbF I-Pak Tube 75 IRFU3707ZPbF
IRFR3707ZPbF D-Pak Tube 75 IRFR3707ZPbF
Tape and Reel Left 3000 IRFR3707ZTRLPbF
Orderable Part Number
S G
D D
S D
Benefits Very Low RDS(on) at 4.5V VGS Ultra - Low Gate Impedance Fully Characterized Avalanche Voltage and Current Lead-Free
Thermal Resistance Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 3.0
°C/W RJA Junction-to-Ambient ( PCB Mount) ––– 50
RJA Junction-to-Ambient ––– 110
Notes through are on page 2.
IRFR/U3707ZPbF
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Notes: Repetitive rating; pulse width limited by max. junction temperature starting TJ = 25°C, L = 0.58mH, RG = 25, IAS = 12A. Pulse width 400µs; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 30A. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994.
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 30 ––– ––– V VGS = 0V, ID = 250µA V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.023 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 7.5 9.5
mVGS = 10V, ID = 15A
––– 10 12.5 VGS = 4.5V, ID = 12A
VGS(th) Gate Threshold Voltage 1.35 1.80 2.25 V VDS = VGS, ID = 25µA
VGS(th)/TJ Gate Threshold Voltage Temp. Coefficient ––– -5.0 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0
µA VDS = 24V, VGS = 0V
––– ––– 150 VDS = 24V,VGS = 0V,TJ =125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100
nA VGS = 20V
Gate-to-Source Reverse Leakage ––– -100 VGS = -20V gfs Forward Trans conductance 71 ––– ––– S VDS = 15V, ID = 12A Qg Total Gate Charge ––– 9.6 14
nC
Qgs1 Pre-Vth Gate-to-Source Charge ––– 2.6 ––– VDS = 15V Qgs2 Post-Vth Gate-to-Source Charge ––– 0.90 ––– VGS = 4.5V Qgd Gate-to-Drain Charge ––– 3.5 ––– ID = 12A Qgodr Gate Charge Overdrive ––– 2.6 ––– See Fig. 16 Qsw Switch Charge (Qgs2 + Qgd) ––– 4.4 –––
Qoss Output Charge ––– 5.8 ––– nC VDS = 15V, VGS = 0V
td(on) Turn-On Delay Time ––– 8.0 –––
ns
VDD = 16V,VGS = 4.5V tr Rise Time ––– 11 ––– ID = 12A td(off) Turn-Off Delay Time ––– 12 ––– Clamped Inductive Load tf Fall Time ––– 3.3 ––– Ciss Input Capacitance ––– 1150 –––
pF VGS = 0V
Coss Output Capacitance ––– 260 ––– VDS = 15V Crss Reverse Transfer Capacitance ––– 120 ––– ƒ = 1.0MHz Avalanche Characteristics
EAS Single Pulse Avalanche Energy 42 mJ IAR Avalanche Current 12 A EAR Repetitive Avalanche Energy 5.0 mJ
Parameter Max. Units
Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current
––– ––– 56 A
MOSFET symbol (Body Diode) showing the
ISM Pulsed Source Current
––– ––– 220 integral reverse
(Body Diode) p-n junction diode. VSD Diode Forward Voltage ––– ––– 1.0 V TJ = 25°C,IS = 12A,VGS = 0V trr Reverse Recovery Time ––– 25 38 ns TJ = 25°C ,IF = 12A, VDS = 15V Qrr Reverse Recovery Charge ––– 17 26 nC di/dt = 100A/µs ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
IRFR/U3707ZPbF
3 2016-5-31
Fig. 2 Typical Output Characteristics
Fig. 3 Typical Transfer Characteristics Fig. 4 Normalized On-Resistance vs. Temperature
Fig. 1 Typical Output Characteristics
0.1 1 10
VDS, Drain-to-Source Voltage (V)
0.001
0.01
0.1
1
10
100
1000
10000
I D, D
rain
-to-
Sou
rce
Cur
rent
(A
)
2.2V
20µs PULSE WIDTHTj = 25°C
VGSTOP 10V
6.0V4.5V4.0V3.3V2.8V2.5V
BOTTOM 2.2V
0.1 1 10
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D, D
rain
-to-
Sou
rce
Cur
rent
(A
)
2.2V
20µs PULSE WIDTHTj = 175°C
VGSTOP 10V
6.0V4.5V4.0V3.3V2.8V2.5V
BOTTOM 2.2V
0 2 4 6 8
VGS, Gate-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
I D, D
rain
-to-
Sou
rce
Cur
rent
)
TJ = 25°C
TJ = 175°C
VDS = 10V
20µs PULSE WIDTH
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
RD
S(o
n) ,
Dra
in-t
o-S
ourc
e O
n R
esis
tanc
e
(
Nor
mal
ized
)
ID = 30A
VGS = 10V
IRFR/U3707ZPbF
4 2016-5-31
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 8. Maximum Safe Operating Area Fig. 7 Typical Source-to-Drain Diode
Forward Voltage
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
1 10 100
VDS, Drain-to-Source Voltage (V)
100
1000
10000
C, C
apac
itanc
e(pF
)
VGS = 0V, f = 1 MHZCiss = Cgs + Cgd, C ds SHORTED
Crss = Cgd Coss = Cds + Cgd
Coss
Crss
Ciss
0 2 4 6 8 10 12
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VG
S, G
ate-
to-S
ourc
e V
olta
ge (
V) VDS= 24V
VDS= 15V
ID= 12A
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
VSD, Source-to-Drain Voltage (V)
0.10
1.00
10.00
100.00
1000.00
I SD
, Rev
erse
Dra
in C
urre
nt (
A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0 1 10 100 1000
VDS, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D,
Dra
in-t
o-S
ourc
e C
urre
nt (
A)
1msec
10msec
OPERATION IN THIS AREA LIMITED BY R DS(on)
100µsec
Tc = 25°CTj = 175°CSingle Pulse
IRFR/U3707ZPbF
5 2016-5-31
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Threshold Voltage vs. Temperature
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
10
20
30
40
50
60
I D,
Dra
in C
urre
nt (
A)
Limited By Package
-75 -50 -25 0 25 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
VG
S(t
h) G
ate
thre
shol
d V
olta
ge (
V)
ID = 250µA
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
The
rmal
Res
pons
e (
Z th
JC )
0.20
0.10
D = 0.50
0.020.01
0.05
SINGLE PULSE( THERMAL RESPONSE )
Notes:1. Duty Factor D = t1/t22. Peak Tj = P dm x Zthjc + Tc
Ri (°C/W) i (sec)
1.698 0.000845
0.481 0.016503
0.823 0.000128 J
J
1
12
23
3
R1
R1R2
R2R3
R3
C
C
Ci= iRiCi= iRi
IRFR/U3707ZPbF
6 2016-5-31
Fig 12a. Unclamped Inductive Test Circuit
Fig 12b. Unclamped Inductive Waveforms
RG
IAS
0.01tp
D.U.T
LVDS
+- VDD
DRIVER
A
15V
20V
tp
V(BR)DSS
IAS
Fig 13b. Gate Charge Test Circuit
Fig 13a. Gate Charge Waveform Fig 14a. Switching Time Test Circuit
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
140
160
180
200
EA
S ,
Sin
gle
Pul
se A
vala
nche
Ene
rgy
(mJ) ID
TOP 3.7A5.6A
BOTTOM 12A
Fig 12c. Maximum Avalanche Energy vs. Drain Current
Fig 14b. Switching Time Waveforms
VGS
Pulse Width < 1µsDuty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
VGS
VDS90%
10%
td(on) td(off)tr tf
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRFR/U3707ZPbF
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Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
IRFR/U3707ZPbF
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Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a subelement of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Id max at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependent (non-linear) capacitance’s Cds and Cdg when multiplied by the power supply input buss voltage.
Ploss Irms2 Rds(on)
I Qgd
ig
Vin f
I
Qgs2
ig
Vin f
Qg Vg f Qoss
2Vin f
Synchronous FET
The power loss equation for Q2 is approximated by; *dissipated primarily in Q1 For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transferred to Q1 and in-crease the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitive coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be min-imized to reduce the potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
Ploss Pconduction Pdrive Poutput*
Ploss Irms
2 Rds(on)
Qg Vg f Qoss
2Vin f
Qrr Vin f
IRFR/U3707ZPbF
9 2016-5-31
Note: For the most current drawing please refer to Infineon’s web site www.infineon.com
D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))
INTERNATIONAL
ASSEMBLED ON WW 16, 2001
IN THE ASSEMBLY LINE "A"
OR
Note: "P" in assembly line position
EXAMPLE:
LOT CODE 1234
THIS IS AN IRFR120WITH ASSEMBLY
indicates "Lead-Free"
PRODUCT (OPTIONAL)P = DESIGNATES LEAD-FREE
A = ASSEMBLY SITE CODE
PART NUMBER
WEEK 16
DATE CODE
YEAR 1 = 2001RECTIFIER
INTERNATIONAL
LOGO
LOT CODEASSEMBLY
3412
IRFR120
116A
LINE A
34
RECTIFIERLOGO
IRFR120
12
ASSEMBLYLOT CODE
YEAR 1 = 2001
DATE CODE
PART NUMBER
WEEK 16
"P" in assembly line position indicates"Lead-Free" qualification to the consumer-level
P = DESIGNATES LEAD-FREEPRODUCT QUALIFIED TO THECONSUMER LEVEL (OPTIONAL)
IRFR/U3707ZPbF
10 2016-5-31
I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
78
LINE A
LOGO
INTERNATIONALRECTIFIER
OR
PRODUCT (OPTIONAL)P = DESIGNATES LEAD-FREE
A = ASSEMBLY SITE CODE
IRFU120
PART NUMBER
WEEK 19
DATE CODE
YEAR 1 = 2001RECTIFIER
INTERNATIONAL
LOGO
ASSEMBLYLOT CODE
IRFU120
56
DATE CODE
PART NUMBER
LOT CODEASSEMBLY
56 78
YEAR 1 = 2001
WEEK 19
119A
indicates Lead-Free"
ASSEMBLED ON WW 19, 2001
IN THE ASSEMBLY LINE "A"
Note: "P" in assembly line position
EXAMPLE:WITH ASSEMBLYTHIS IS AN IRFU120
LOT CODE 5678
Note: For the most current drawing please refer to Infineon’s web site www.infineon.com
IRFR/U3707ZPbF
11 2016-5-31
Note: For the most current drawing please refer to Infineon’s web site www.infineon.com
TR
16.3 ( .641 )15.7 ( .619 )
8.1 ( .318 )7.9 ( .312 )
12.1 ( .476 )11.9 ( .469 )
FEED DIRECTION FEED DIRECTION
16.3 ( .641 )15.7 ( .619 )
TRR TRL
NOTES :1. CONTROLLING DIMENSION : MILLIMETER.2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches)
IRFR/U3707ZPbF
12 2016-5-31
Revision History
Date Comments
5/31/2016 Updated datasheet with corporate template. Added disclaimer on last page.
Qualification Information†
Qualification Level Industrial
(per JEDEC JESD47F) ††
D-Pak MSL1
I-Pak (per JEDEC J-STD-020D) ††
RoHS Compliant Yes
Moisture Sensitivity Level
† Qualification standards can be found at Infineon’s web site www.infineon.com †† Applicable version of JEDEC standard at the time of product release.
Trademarks of Infineon Technologies AG µHVIC™, µIPM™, µPFC™, AU‐ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI‐POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my‐d™, NovalithIC™, OPTIGA™, Op MOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO‐SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™ Trademarks updated November 2015
Other Trademarks All referenced product or service names and trademarks are the property of their respec ve owners.
Edi on 2016‐04‐19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG. All Rights Reserved.
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Document reference
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IMPORTANT NOTICE The informa on given in this document shall in no event be regarded as a guarantee of condi ons or characteris cs (“Beschaffenheitsgaran e”) . With respect to any examples, hints or any typical values stated herein and/or any informa on regarding the applica on of the product, Infineon Technologies hereby disclaims any and all warran es and liabili es of any kind, including without limita on warran es of non‐infringement of intellectual property rights of any third party. In addi on, any informa on given in this document is subject to customer’s compliance with its obliga ons stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applica ons. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended applica on and the completeness of the product informa on given in this document with respect to such applica on.
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