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Week 5
Finite State Machine design examples
ENGN3213/6213
Digital Systems and Microprocessors
8/18/2019 In Class - Finite State Machine Examples
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What’s on today
• Three complete examples of finite state
machine designs
– An alarm system – A pedestrian traffic controller
– A vending machine
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Resources
• Wakerly Ch. 7.7 for yet another example
of FSM design
• Wakerly Ch. 7.13 describes standards forVerilog coding of state machines
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Example 1: An alarm system
• Problem statement:
– The alarm should sound when the sensor istriggered by the burglar walking through
– The sound stops upon pressure of a reset
button (but only if the sensor at that time is not
picking up any intruders).
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Example 1: An alarm system (2)
• First we identify the inputs and outputs
– Inputs:
• The trigger (binary signal (triggered/non triggered))
• The reset button (also binary (pressed/depressed))
– States:
• Quiet ( Armed )
• Sound alarm (Sound )
– Outputs:
• Alarm bell (on/off)
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Example 1: An alarm system (3)
• The FSM is a Moore machine
• The output is a function of the state alone
– When the state is Sound the output is 1 (Alarm ON)
– When the state is Armed the output is 0 (Alarm OFF)
Trigger
Reset
State
Memory Alarm
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Example 1: An alarm system (4)
• The state diagram
S1
Sound
1
S0
Armed
0
Reset AND
NOT(Trigger)
Trigger
ResetTrigger
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Example 1: An alarm system (4)
• Next state table
– A=Armed
– S=Sound – T=Trigger signal
– R=Reset signal
State Input Next
state
Output
A T’R’ A OFF
A T’R A OFF
A TR’ S OFF
A TR S OFF
S T’R’ S ON
S T’R A ON
S TR’ S ON
S TR S ON
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Example 1: An alarm system (5)
• Next state table withbinary inputs – Note that I use the
Gray code – I can use this table as
a Karnaugh Map tofind a function which
associates the inputswith the next state.
– Next state equation:
S* = T + R’∙S
inputs
TR
stateS
00 01 11 10
0 0 0 1 1
1 1 0 1 1
T
TR’∙S
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Example 1: An alarm system (6)
• We are now ready to turn this into a circuit!
– 1 binary state = 1 flip flop
– output = state (the output logic is trivial)
– next state logic as per previous slide
D Q
CK Q’ T
RSS*
clk
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Example 1: An alarm system (7)
• Now the Verilog code
module MyAlarm(input wire T, R, clk,
output wire alarm_ON);
reg state, Snext;
always @(*) Snext=T|(~R & state); //next-state logic
always @( posedge clk) state<=Snext; //state memory (flip flop)
assign alarm_ON=state; //output logic, trivial
endmodule
/*Design Finished! Hooray!*/
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Example 2: A pedestrian traffic controller
• Problem statement:
– Design a traffic light controller with an input button:‘request’. There are 5 lights (outputs): WALK/HALT
for pedestrians and GREEN/ORANGE/RED for cars.
– The pedestrian will press the request button and the
lights will shift for the cars until RED, then the WALK
sign will be illuminated. After some time, WALK will
shift to HALT and the cars will get a GREEN light until
the next pedestrian button press.
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Example 2: A pedestrian traffic controller (2)
• Identifying the main features
– Inputs
• Request button (we’ll also need a ‘reset’ input… we’ll see this shortly)
– Outputs• The 5 lights: R,O,G, WALK, HALT
– States
• S0: GREEN, HALT
• S1: ORANGE, HALT
• S2: RED, WALK• S3: RED, HALT
– Note how the states correspond to output combinations (the input
button has no direct effect on the lights).
• This is how I can tell right away that it is a Moore Machine!
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Example 2: A pedestrian traffic controller (3)
• The state diagram
• Note that the transition between s0 and s1 depends on the requestbutton, while s1s2s3s0 is going to be a timed sequence ofstates. (for which we will use an event sequencer acting as a timer)
• Note the reset function, it means that at any time if the system isreset it will go to state 3, regardless of the state it is in.
s000
G, HALT
ResetRequest
s101
O, HALT
s211
R,WALK
s310
R,HALT
Request Timer Timer
Timer
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Example 2: A pedestrian traffic controller (4)
• Next state table
– Again note the use of
Gray code
State
S[1:0]
Input Next
state
Output
00 Req 01 G,H
01 Req 11 O,H
11 Req 10 R,W
10 Req 00 R,H
00 Req’ 00 G,H01 Req’ 11 O,H
11 Req’ 10 R,W
10 Req’ 00 R,H
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Example 2: A pedestrian traffic controller (5)
• Karnaugh Maps for next
state logic
– One for each state!
state
S
input
Req
00 01 11 10
0 0 1 0 0
1 1 1 0 0
state
S
input
Req
00 01 11 10
0 0 1 1 0
1 0 1 1 0
Table for S[0]*
Table for S[1]*
S[0]* = S[1]’(Req+S[0])
S[1]* =S[0]
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Example 2: A pedestrian traffic controller (6)
• Circuit diagram for state transitions (with reset)
D Q
CK C
Req S[0]S*[0]
CK
D S Q
CK
S[1]S*[1]
Reset
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Example 2: A pedestrian traffic controller (7)
• Output logic (a simple decoder)
S[0]
S[1] R
O
G
W
H
State
S[1:0]
Output
00 G,H
01 O,H
11 R,W
10 R,H
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Example 2: A pedestrian traffic controller (8)
• Delayed state transitions
– The only problem with the design shown is that once the request
button is pressed the system will cycle through all the other
states in a matter of 4 clock cycles.
– With a MHz clock that is not long enough to cross the road ! – We need to introduce the last part of the circuit: the event
sequencer .
• Implemented as a counter attached
to a decoder which maps desired
count values with a ‘1’ output.• This output can be used to
‘enable’ the flip-flops.
• Only on those pre-determined
counts will the transition be
allowed to occur.
D Q
CK
Counter
CK
de
co
der
0
1 SS*
EN
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Example 2: A pedestrian traffic controller (9) module Traffic(input wire Req, Reset, clk,
output reg R,O,G,W,H);reg [1:0] S, Snext;
reg [31:0] count; //a 32-bit counterreg En;
always @(*) begin //next-state logicSnext[0]=~S[1]&(Req|S[0]);
Snext[1]=S[0];end
always @( posedge clk) begin //state memory (flip flop)
if (Reset) S<=2’b10;
else if (En||(S==2’b00)) S<=Snext;end
always @( posedge clk) begin //counter logicif(S==2’b00||Reset) count<=32’d0; //reset at s0 or reset btn push else count<=count+1;
end
/*continues in the next slide*/
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Example 2: A pedestrian traffic controller (10)
always @(*) begin //decoder logiccase(count)
32’d100000000 : En=1; //state s1 will last 100… clock cycles 32’d500000000 : En=1; //state s2 will last 400… clock cycles 32’d600000000 : En=1; //state s3 will last 100… clock cycles default : En=0;
endcaseend
always @(*) begin //output logiccase(S)2’b00 : begin R=0; O=0; G=1; W=0; end 2’b01 : begin R=0; O=1; G=0; W=0; end
2’b11 : begin R=1; O=0; G=0; W=1; end 2’b10 : begin R=1; O=0; G=0; W=0; end default: begin R=1; O=0; G=0; W=0; end
endcaseH=~W;endendmodule
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Example 3: A vending machine
• Problem Statement
– Design a state machine controller for a vending
machine to satisfy the following:
• Sell one item worth 75c
• Return change and deliver the item when the coins inserted
into the machine exceed the sum of 75c
• Return all coins upon request without releasing the item
• Input variables : – COIN indicating if a coin is deposited,
– RETURN if the return change button is pushed
– SUM which is the output of the coin tallying device internal to
the vending machine. SUM consists of three inputs indicating
whether the current coin entry is <,=,> the price of the product.
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Example 3: A vending machine (2)
• Inputs/Outputs
input abbreviation output abbreviation
coin
return
sum<75
sum=75
sum>75
change-available
CN
RTN
SM0
SM1
SM2
CA
release-candy
return-change
return-all-coins
RC
RCH
RAC
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Example 3: A vending machine (3)
• State transition table
Present
state
Description Next state Release
candy
Return
all coins
Return
change
s0idle s0 if CN=0, RTN=0
s1 if CN=1, RTN=0
s5 if CN=0, RTN=1
0 0 0
s1 coin in, check total s0 if SM0=1
s2 if SM1=1
s3 if SM2=1
0 0 0
s2 release candy s0 1 0 0
s3 check for change s5 if CA=0
s4 if CA=1
0 0 0
s4 return change s2 0 0 1
s5 return all coins s0 0 1 0ENGN3213/6213 - Week 5 24
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Example 3: A vending machine (3)
• State codes
– For this example we use a one-hot coding for the states
– Only one flip-flop is storing a ‘1’ at any one time.
Presentstate
State code
(ABCDEF)
Description
s0 000001 idle
s1 000010 coin in, check total
s2 000100 release candy
s3 001000 check for change
s4 010000 return change
s5100000 return all coins
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Example 3: A vending machine (4)
State diagram
s0 – idle
000001 (F)
s1 – coin in
000010 (E)
s3 –
check change
001000 (C)
s5 –
return all coins
100000 (A)
s4 –
return change010000 (B)
s2 –
return candy
000100 (D)SM0 CN CA’
CA
CN’∙RTN
CN’∙RTN’
SM1
SM2
Reset
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Example 3: A vending machine (5)• General architecture of the system
Next state
logicOutput
logic
CN
RTN
SM0
SM1
SM2
CA
Reset
D Q
CK
D Q
CK
D Q
CK
D Q
CK
D Q
CK
D Q
CK
clk
6
RC
RCH
RAC
D A
DB
DC
DD
DE
DF
Q A
QB
QC
QD
QE
QF
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Example 3: A vending machine (6)
• The Reset signal is wired so as to force the state s0=000001
• The one-hot coding approach uses more flip flops than standard binary or
Gray coding (6 FF, 3 would be more than enough to map 3 states) but makes
next-state logic very simple (almost immediate from the state diagram)
• Next-state logic:
DA = (QF ∙ CN’ ∙ RTN) + (QC ∙ CA’)
(the next state will be A (s5) if the current state is C (s3) and CA=0 or if the current state
is F(s0) and RTN=1 with CN=0)
DB = QC ∙ CA
DC = QE ∙ SM2
DD = QE ∙ SM1 + QB
DE = QF ∙ CN
DF = (QF ∙ CN’ ∙ RTN’) + (QE ∙ SM0) + QD + QA
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Example 3: A vending machine (7)
• The output logic is also very simple thanks to one-hot
coding:
RC = QD
RCH = QB
RAC = QA
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Summing up
• 3 examples of state machine design
– The main state machine design workflow ideas:
• Identify inputs and outputs
• Assign states (a variety of state encoding options available)• Determine transitions (with tables / diagrams) without ambiguity
• Is the output a function of the state alone or of both state and input?
– Moore / Mealy Machine?
• Determine next-state and output logic
• Assemble in circuit schematic / Verilog – Keep next-state logic, state memory and output logic separate
– Keep next-state logic and output logic combinational
– Keep state memory sequential
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