Chapter #8: Finite State Machine Design
description
Transcript of Chapter #8: Finite State Machine Design
No. 8-1
Chapter #8: Finite State Machine Design
No. 8-2
Motivation
Counters: Sequential Circuits where State = Output
Generalizes to Finite State Machines: Outputs are Function of State (and Inputs) Next States are Functions of State and Inputs Used to implement circuits that control other circuits "Decision Making" logic
Application of Sequential Logic Design Techniques Word Problems Mapping into formal representations of FSM behavior Case Studies
No. 8-3
Chapter Overview
Concept of the State Machine
Partitioning into Datapath and Control
When Inputs are Sampled and Outputs Asserted
Basic Design Approach
Six Step Design Process
Alternative State Machine Representations
State Diagram, ASM Notation, VHDL, ABEL Description Language
Moore and Mealy Machines
Definitions, Implementation Examples
Word Problems
Case Studies
No. 8-5
Concept of the State MachineExample: Odd Parity Checker
Even [0]
Odd [1]
Reset
0
0
1 1
Assert output whenever input bit stream has odd # of 1's
StateDiagram
Present State Even Even Odd Odd
Input 0 1 0 1
Next State Even Odd Odd Even
Output 0 0 1 1
Symbolic State Transition Table
Output 0 0 1 1
Next State 0 1 1 0
Input 0 1 0 1
Present State 0 0 1 1
Encoded State Transition Table
No. 8-6
Concept of the State MachineExample: Odd Parity Checker
Next State/Output Functions
NS = PS xor PI; OUT = PS
D
R
Q
Q
Input
CLK PS/Output
\Reset
NS
D FF Implementation
T
R
Q
Q
Input
CLK
Output
\Reset
T FF Implementation
Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
Clk
Output
Input 1 0 0 1 1 0 1 0 1 1 1 0
1 1 0 1 0 0 1 1 0 1 1 1
No. 8-7
Concept of State Machine
Timing: When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events
Clocking event causes state/outputs to transition, based on inputs
For set-up/hold time considerations:
Inputs should be stable before clocking event
After propagation delay, Next State entered, Outputs are stable
NOTE: Asynchronous signals take effect immediately Synchronous signals take effect at the next clocking event
E.g., tri-state enable: effective immediately sync. counter clear: effective at next clock event
No. 8-8
Concept of State Machine
Example: Positive Edge Triggered Synchronous System
On rising edge, inputs sampled outputs, next state computed
After propagation delay, outputs and next state become stable
Immediate Outputs: affect datapath immediately could cause inputs from datapath to change
Delayed Outputs: take effect on next clock edge propagation delays must exceed hold timesOutputs
State T ime
Clock
Inputs
No. 8-9
Concept of the State MachineCommunicating State Machines
Fragment state diagramsInitial inputs/outputs: X = 0, Y = 0
One machine's output is another machine's input
CLK
FSM 1 X FSM 2
Y
A A B
C D D
FSM 1 FSM 2
X
Y
A [1]
B [0]
Y=0
Y=1
Y=0,1
Y=0
C [0]
D [1]
X=0
X=1
X=0
X=0
X=1
No. 8-10
Basic Design Approach
Six Step Process
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state minimization
4. Perform state assignment (or encoding)
5. Choose FF types to implement FSM state register
6. Implement the FSM
1, 2 covered now; 3~6 covered later (Chap. 9);5 and 6 generalized from the counter design procedure
No. 8-11
Basic Design Approach
Example: Vending Machine FSM
General Machine Concept:deliver package of gum after 15 cents deposited
single coin slot for dimes (10 cents), nickels (5 cents)
no change
Block Diagram
Step 1. Understand the problem:
Vending Machine
FSM
N
D
Reset
Clk
OpenCoin
SensorGum
Release Mechanism
Draw a picture!
No. 8-12
Vending Machine Example
Tabulate typical input sequences:three nickelsnickel, dimedime, nickeltwo dimestwo nickels, dime
Draw state diagram:
Inputs: N, D, reset
Output: open
Step 2. Map into more suitable abstract representation
Reset
N
N
N
D
D
N D
[open]
[open] [open] [open]
S0
S1 S2
S3 S4 S5 S6
S8
[open]
S7
D
No. 8-13
Vending Machine Example
Step 3: State Minimization
Reset
N
N
N, D
[open]
15¢
0¢
5¢
10¢
D
D
reuse stateswheneverpossible
Symbolic State Table
Present State
0¢
5¢
10¢
15¢
D
0 0 1 1 0 0 1 1 0 0 1 1 X
N
0 1 0 1 0 1 0 1 0 1 0 1 X
Inputs Next State
0¢ 5¢ 10¢ X 5¢ 10¢ 15¢ X
10¢ 15¢ 15¢ X
15¢
Output Open
0 0 0 X 0 0 0 X 0 0 0 X 1
No. 8-14
Vending Machine Example
Step 4: State Encoding
Next State D 1 D 0
0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X
Present State Q 1 Q 0
0 0
0 1
1 0
1 1
D
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
N
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Inputs Output Open
0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X
No. 8-15
Parity Checker Example
Step 5. Choose FFs for implementation
D FF easiest to use
D1 D0 Open
D1 = Q1 + D + Q0 N
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
8 Gates
CLK
OPEN
CLK
Q 0
D
R
Q
Q
D
R
Q
Q
\ Q 1
\reset
\reset
\ Q 0
\ Q 0
Q 0
Q 0
Q 1
Q 1
Q 1
Q 1
D
D
N
N
N
\ N
D 1
D 0
No. 8-16
Parity Checker Example
Step 5. Choosing FF for Implementation
J-K FF
Remapped encoded state transition table
Next State D 1 D 0
0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X
Present State Q 1 Q 0
0 0
0 1
1 0
1 1
D
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
N
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Inputs K 1
X X X X X X X X 0 0 0 X 0 0 0 X
K 0
X X X X 0 1 0 X X X X X 0 0 0 X
J 1
0 0 1 X 0 1 1 X X X X X X X X X
J 0
0 1 0 X X X X X 0 1 1 X X X X X
No. 8-17
Vending Machine Example
Implementation:
J1 = D + Q0 N
K1 = 0
J0 = Q0 N + Q1 D
K0 = Q1 N
7 Gates
OPEN Q 1
\ Q 0
N
Q 0 J
K R
Q
Q
J
K R
Q
Q
Q 0
\ Q 1
\ Q 1
\ Q 0
Q 1
\reset
D
D
N
N
CLK
CLK
No. 8-18
Alternative State Machine Representations
Why State Diagrams Are Not Enough
Not flexible enough for describing very complex finite state machines
Not suitable for gradual refinement of finite state machine
Do not obviously describe an algorithm: that is, well specified sequence of actions based on input data
algorithm = sequencing + data manipulation separation of control and data
Gradual shift towards program-like representations:
Algorithmic State Machine (ASM) Notation
Hardware Description Languages (e.g., VHDL)
No. 8-19
Alternative State Machine Representations
Algorithmic State Machine (ASM) Notation
Three Primitive Elements:
State Box
Decision Box
Output Box
State Machine in one state block per state time
Single Entry Point
Unambiguous Exit Path for each combination of inputs
Outputs asserted high (.H) or low (.L); Immediate (I) or delayed til next clock
State Entry Path
State Name
State Code
State Box
ASM Block
State Output List
Condition Box
Conditional Output List
Output Box
Exits to other ASM Blocks
Condition
* ***
T F
No. 8-20
Alternative State Machine Representations
ASM Notation
Condition Boxes:Ordering has no effect on final outcome
Equivalent ASM charts: A exits to B on (I0 & I1 = 1) else exit to C
A 010
I0
I1
T
T
F
F
B C
A 010
I0
T
T
F
F
B C
I1
No. 8-21
Alternative State Machine Representations
Example: Parity Checker
Nothing in output list implies Z not asserted
Z asserted in State Odd
Input X, Output Z
InputFTFT
PresentStateEvenEvenOddOdd
NextStateEvenOddOddEven
Output
AA
Symbolic State Table:
Input0101
PresentState
0011
NextState
0110
Output0011
Encoded State Table:
Trace paths to derivestate transition tables
Trace paths to derivestate transition tables
Even
Odd
H. Z
X
X
0
1
F
T
T F
No. 8-22
Alternative State Machine Representations
ASM Chart for Vending Machine
0¢
15¢
H.Open
D
Reset
00
1 1
T
T
F
N F
T
F
10¢
D
10
T
N F
T
F
5¢
D
01
T N
F T
F
0¢
No. 8-23
Moore and Mealy Machine Design ProcedureDefinitions
Moore Machine
Outputs are functionsolely of the current
state
Outputs change synchronously with
state changes
Mealy Machine
Outputs depend onstate AND inputs
Input change causesan immediate output
change
Asynchronous outputs
State Register Clock
State Feedback
Combinational Logic for
Outputs and Next State
X Inputs
i Z Outputs
k
Clock
state feedback
Combinational Logic for
Next State (Flip-flop Inputs)
State Register
Comb. Logic for Outputs
Z Outputs
k
X Inputs
i
No. 8-24
Moore and Mealy MachinesState Diagram Equivalents
Outputs are associated with State
Outputs are associated with Transitions
Reset/0
N/0
N/0
N+D/1
15¢
0¢
5¢
10¢
D/0
D/1
(N D + Reset)/0
Reset/0
Reset/1
N D/0
N D/0
MooreMachine Reset
N
N
N+D
[1]
15¢
0¢
5¢
10¢
D
[0]
[0]
[0]
D
N D + Reset
Reset
Reset
N D
N D
MealyMachine
No. 8-25
Moore and Mealy MachinesStates vs. Transitions
Mealy Machine typically has fewer states than Moore Machine for same output sequence
EquivalentASM Charts
Asserts its output whenever at least two 1’s in sequence
Same I/O behavior
Different # of states
1
1
0
1
2
0
0
[0]
[0]
[1]
1/0
0
1
0/0
0/0
1/1
1
0
S0
S1
IN
IN
S2
IN
10
01
00
H.OUT
S0
S1
IN
IN
1
0
H.OUT
F F
F F
T
T
T
T
T
F
No. 8-26
Moore and Mealy MachinesTiming Behavior of Moore Machines
Reverse engineer the following: why Moore ???
Input XOutput ZState A, B (= Z)
Two Techniques for Reverse Engineering:
Ad Hoc: Try input combinations to derive transition table
Formal: Derive next state/output functions by analyzing the circuit
JCK R
Q
Q
FFa
JCK R
Q
Q
FFb
X
X
X
X
\Reset
\Reset
A
Z
\A
\A\B
\B
Clk
No. 8-27
Moore and Mealy Machines
Ad Hoc Reverse Engineering
Behavior in response to input sequence 1 0 1 0 1 0:
Partially DerivedState Transition
Table
A 0
0
1
1
B 0 1 0 1
X 0 1 0 1 01 0 1
A+ ? 1 0 ? 1 0 1 1
B+ ? 1 0 ? 0 1 1 0
Z 0 0 1 1 0 0 1 1
X = 1 AB = 00
X = 0 AB = 1 1
X = 1 AB = 1 1
X = 0 AB = 10
X = 1 AB = 10
X = 0 AB = 01
X = 0 AB = 00
Reset AB = 00
100
X
Clk
A
Z
\Reset
No. 8-28
Moore and Mealy MachinesFormal Reverse Engineering
Derive transition table from next state and output combinational functions presented to the flipflops!
Ja = XJb = X
Ka = X BKb = X xor A
Z = B
FF excitation equations for J-K flipflop: Q+ = J \Q +\K Q
A+ = Ja A + Ka A = X A + (X + B) AB+ = Jb B + Kb B = X B + (X A + X A) B
Next State K-Maps:
State 00, Input 0 State 00State 01, Input 1 State 11
No. 8-29
Moore and Mealy MachinesComplete ASM Chart for the Mystery Moore Machine
Note: All Outputs Associated With State BoxesNo Separate Output Boxes, Intrinsic in Moore Machines
S 0 00
X
H. Z
S 1 01
X
S 3 1 1
S 2 10
H. Z
X
X
0 1
1 0
0
1
0 1
No. 8-30
Moore and Mealy MachinesReverse Engineering a Mealy Machine
Input X, Output Z, State A, B
State register consists of D FF and J-K FF
D
C R
Q
Q
J C K R
Q
Q
X
X
X
Clk
A
A
A
B
B
B
Z
\Reset \Reset
\ A
\ A
\ X
\ X
\ X \ B
DA
DA
No. 8-31
Moore and Mealy MachineAd Hoc Method
Signal Trace of Input Sequence 101011:
Note glitchesin Z!
Outputs valid atfollowing falling
clock edge
Partially completedstate transition tablebased on the signal
trace
A 0
0
1
1
B 0 1 0 1
X 0 1 0 1 0 1 0 1
A+ 0 0 ? 1 ? 0 1 ?
B+ 1 0 ? 1 ? 1 0 ?
Z 0 0 ? 0 ? 1 1 ?
Reset AB =00
Z =0
X =1 AB =00
Z =0
X =0 AB =00
Z =0
X =1 AB =01
Z =0
X =1 AB =10
Z =1
X =0 AB =1 1
Z =1
X =1 AB =01
Z =0
X
Clk
A
B
Z
\Reset
100
No. 8-32
Moore and Mealy MachinesFormal Method
A+ = B (A + X) = A B + B X
B+ = Jb B + Kb B = (A xor X) B + X B
= A B X + A B X + B X
Z = A X + B XMissing Transitions and Outputs:
State 01, Input 0 -> State 00, Output 1State 10, Input 0 -> State 00, Output 0State 11, Input 1 -> State 11, Output 1A+
B+
Z
No. 8-33
Moore and Mealy MachinesASM Chart for Mystery Mealy Machine
S0 = 00, S1 = 01, S2 = 10, S3 = 11
NOTE: Some Outputs in Output Boxes as well as State BoxesThis is intrinsic in Mealy Machine implementation
S 0 00
X
H. Z S 1 01
S 2 10
X
H. Z
H. Z
S 3 1 1
X X
0
1
0
0 1
1
0 1
No. 8-34
Moore and Mealy MachinesSynchronous Mealy Machine
latched state AND outputs
avoids glitchy outputs!
State Register Clock
Clock
Combinational Logic for
Outputs and Next State
state feedback
X Inputs
i Z Outputs
k
No. 8-35
Finite State Machine Word ProblemsMapping English Language Description to Formal Specifications
Four Case Studies:
Finite String Pattern Recognizer
Complex Counter with Decision Making
Traffic Light Controller
Digital Combination Lock
We will use state diagrams and ASM Charts
No. 8-36
Finite State Machine Word ProblemsFinite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).The output is asserted whenever the input sequence …010…has been observed, as long as the sequence 100 has never beenseen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010Z: 00010101000
X: 11011010010Z: 00000001000
No. 8-37
Finite State Machine Word Problems
Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the strings that must be recognized. I.e., 010 and 100.
Moore State DiagramReset signal places FSM in S0
Outputs 1 Loops in State
No. 8-38
Finite State Machine Word ProblemsFinite String Recognizer
Exit conditions from state S3: if next input is 0 then have …0100 (state S6) if next input is 1 then have …0101 (state S2)
No. 8-39
Finite State Machine Word ProblemsFinite String Recognizer
Exit conditions from S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1
No. 8-40
Finite State Machine Word ProblemsFinite String Recognizer
S2, S5 with incomplete transitions
S2 = …01; If next input is 1, then string could be prefix of (01)1(00) S4 handles just this case!
S5 = …10; If next input is 1, then string could be prefix of (10)1(0) S2 handles just this case!
Final State Diagram
No. 8-41
Finite State Machine Word ProblemsFinite String Recognizer
Review of Process:
Write down sample inputs and outputs to understand specification
Write down sequences of states and transitions for the sequences to be recognized
Add missing transitions; reuse states as much as possible
Verify I/O behavior of your state diagram to insure it functions like the specification
No. 8-42
Finite State Machine Word ProblemsComplex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the countercounts up in the binary sequence. When M = 1, the counter advancesthrough the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111Gray: 000, 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:
Mode Input M0011100
Current State000001010110111101110
Next State (Z2 Z1 Z0)001010110111101110111
No. 8-43
Finite State Machine Word ProblemsComplex Counter
One state for each output combinationAdd appropriate arcs for the mode control
S 0 000
S 1 001 H. Z 0
M
S 3 01 1 H. Z 1 H. Z 0
H. Z 1
S 2 010
M M
S 6 1 10 H. Z 2 H. Z 1
H. Z 2 H. Z 1 H. Z 0
S 4 100
M
H. Z 2
H. Z 2 H. Z 0
M
S 5 101
M
S 7 1 1 1
0 1
0 1
0
1
0
1 0
1
0 1
No. 8-44
Finite State Machine Word ProblemsTraffic Light Controller
A busy highway is intersected by a little used farmroad. DetectorsC sense the presence of cars waiting on the farmroad. With no caron farmroad, light remain green in highway direction. If vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green. These stay green only as long as a farmroad car is detected but never longer than a set interval. When these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green. Even if farmroad vehicles are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse(TS) and a long time pulse (TL) in response to a set (ST) signal. TSis to be used for timing yellow lights and TL for green lights.
No. 8-45
Finite State Machine Word ProblemsTraffic Light Controller
Picture of Highway/Farmroad Intersection:
Highway
Highway
Farmroad
Farmroad
HL
HL
FL
FL
C
C
No. 8-46
Finite State Machine Word ProblemsTraffic Light Controller
Tabulation of Inputs and Outputs:
Input SignalresetCTSTL
Output SignalHG, HY, HRFG, FY, FRST
Descriptionplace FSM in initial statedetect vehicle on farmroadshort time interval expiredlong time interval expired
Descriptionassert green/yellow/red highway lightsassert green/yellow/red farmroad lightsstart timing a short or long interval
Tabulation of Unique States: Some light configuration imply others
StateS0S1S2S3
DescriptionHighway green (farmroad red)Highway yellow (farmroad red)Farmroad green (highway red)Farmroad yellow (highway red)
No. 8-47
Finite State Machine Word ProblemsTraffic Light Controller
Refinement of ASM Chart:
Start with basic sequencing and outputs:
S 0 S 3
S 1 S 2
H.HG H.FR
H.HR H.FY
H.HR H.FG
H.HY H.FR
No. 8-48
Finite State Machine Word ProblemsTraffic Light Controller
Determine Exit Conditions for S0: Car waiting and Long Time Interval Expired- C · TL
Equivalent ASM Chart Fragments
S 0 S 0
H.HG H.FR
H.HG H.FR
TL TL • C
H.ST C
H.ST S 1
H.HY H.FR
S 1
H.HY H.FR
0
0
1
1
0
1
C · TL
No. 8-49
Finite State Machine Word ProblemsTraffic Light Controller
S1 to S2 Transition: Set ST on exit from S0 Stay in S1 until TS asserted Similar situation for S3 to S4 transition
S 1
H.HY H.FR
TS
H.ST
S 2
H.HR H.FG
0 1
No. 8-50
Finite State Machine Word ProblemsTraffic Light Controller
S2 Exit Condition: no car waiting OR long time interval expired
Complete ASM Chart for Traffic Light Controller
S 0 S 3
H.HG H.FR H.ST
H.HR H.FY
TS TL • C
H.ST H.ST
S 1 S 2
H.HY H.FR
H.ST H.HR H.FG
TS TL + C
0 0 1
1
1 0
1
0
No. 8-51
Finite State Machine Word ProblemsTraffic Light Controller
Compare with state diagram:
Advantages of ASM Charts:
Concentrates on paths and conditions for exiting a state
Exit conditions built up incrementally, later combined into single Boolean condition for exit
Easier to understand the design as an algorithm
S0: HG
S1: HY
S2: FG
S3: FY
Reset
TL + C
S0TL•C/ST
TS
S1 S3
S2
TS/ST
TS/ST
TL + C/ST
TS
TL • C
No. 8-52
Finite State Machine Word ProblemsDigital Combination Lock
"3 bit serial lock controls entry to locked room. Inputs are RESET,ENTER, 2 position switch for bit of key data. Locks generates anUNLOCK signal when key matches internal combination. ERRORlight illuminated if key does not match combination. Sequence is:(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &(3) two more times."
Problem specification is incomplete:
how do you set the internal combination?
exactly when is the ERROR light asserted?
Make reasonable assumptions:
hardwired into next state logic vs. stored in internal register
assert as soon as error is detected vs. wait until full combination has been entered
Our design: registered combination plus error after full combination
No. 8-53
Finite State Machine Word ProblemsDigital Combination Lock
Understanding the problem: draw a block diagram
InternalCombination
Operator Data
Inputs:ResetEnterKey-InL0, L1, L2
Outputs:UnlockError
UNLOCK
ERROR
RESET
ENTER
KEY -IN
L 0
L 1
L 2
Combination Lock FSM
No. 8-54
Finite State Machine Word ProblemsDigital Combination Lock
Enumeration of states:
what sequences lead to opening the door? error conditions on a second pass
START state plus three key COMParison states
START entered on RESET
Exit START when ENTER is pressed
Continue on if Key-In matches L0
ST ART
Reset
Enter
COMP0
KI = L 0
N
Y
1
0
0
1
No. 8-55
Finite State Machine Word ProblemsDigital Combination Lock
Path to unlock:
Wait for Enter Key press
Compare Key-IN
COMP0
N KI = L 0
Y IDLE0
Enter
COMP1
N
Y
KI = L 1
IDLE1
COMP2
Enter
N KI = L 2
Y DONE
H.Unlock
Reset
ST ART
1
0
0
1
0
1
No. 8-56
Finite State Machine Word ProblemsDigital Combination Lock
Now consider error paths
Should follow a similar sequence as UNLOCK path, except asserting ERROR at the end:
COMP0 error exits to IDLE0'
COMP1 error exits to IDLE1'
COMP2 error exits to ERROR3
IDLE0'
Enter
ERROR1
IDLE1'
Enter
ERROR2
ERROR3
H.Error
Reset
ST ART
0 0 0
1 1 1
No. 8-57
Finite State Machine Word ProblemsDigital Combination Lock
Equivalent State Diagram
Reset
Reset + Enter
Reset • Enter
Start
Comp0
KI = L0 KI ° L0
Enter
Enter
Enter
Enter
Idle0 Idle0'
Comp1 Error1
KI ° L1KI = L1Enter
Enter
EnterEnter
Idle1 Idle1'
Comp2 Error2
KI ° L2KI = L2
Done [Unlock]
Error3 [Error]
Reset
Reset Reset
Reset
StartStart
No. 8-58
Chapter Review
Basic Timing Behavior an FSM
when are inputs sampled, next state/outputs transition and stabilize
Moore and Mealy (Async and Sync) machine organizations outputs = F(state) vs. outputs = F(state, inputs)
First Two Steps of the Six Step Procedure for FSM Design
understanding the problem
abstract representation of the FSM
Abstract Representations of an FSM
ASM Charts
Word Problems
understand I/O behavior; draw diagrams
enumerate states for the "goal"; expand with error conditions
reuse states whenever possible