ECE 545 – Introduction to VHDL George Mason University
Data types Timing in VHDL
ECE 545Lecture 13
ECE 545 – Introduction to VHDL 2
Sources & Required Reading
• Peter Ashenden, The Designer’s Guide to VHDL,
Chapter 2
Scalar Data Types and OperationsChapter 4
Composite Data Types and Operations
ECE 545 – Introduction to VHDL 3
VHDL as a Strongly Typed Language
ECE 545 – Introduction to VHDL 4
Notion of type
• Type defines a set of values and a set of applicable operations
• Declaration of a type determines which values can be stored in an object (signal, variable, constant) of a given type
• Every object can only assume values of its nominated type
• Each operation (e.g., and, +, *) includes the types of values to which the operation may be applied, and the type of the result
• The goal of strong typing is a detection of errors at an early stage of the design process
ECE 545 – Introduction to VHDL 5
Example of strong typing
architecture incorrect of example1 is
type apples is range 0 to 100;type oranges is range 0 to 100;
signal apple1: apples;signal orange1: oranges;
begin apple1 <= orange1;end incorrect;
ECE 545 – Introduction to VHDL 6
Type Classification
ECE 545 – Introduction to VHDL 7
Classification of data types
ECE 545 – Introduction to VHDL 8
Integer Types
ECE 545 – Introduction to VHDL 9
Integer type
Name: integer
Status: predefined
Contents: all integer numbers representable on a particular host computer, but at least numbers in the range
–(231-1) .. 231-1
ECE 545 – Introduction to VHDL 10
User defined integer types - Examples
type day_of_month is range 0 to 31;
type year is range 0 to 2100;
type set_index_range is range 999 downto 100;
constant number_of_bits: integer :=32;
type bit_index is range 0 to number_of_bits-1;
Values of bounds can be expressions, but
need to be known when the model is analyzed.
ECE 545 – Introduction to VHDL 11
Enumeration Types
ECE 545 – Introduction to VHDL 12
Predefined enumeration types (1)
boolean (true, false)
bit (‘0’, ‘1’)
character VHDL-87:128 7-bit ASCII characters
VHDL-93:256 ISO 8859 Latin-1 8-bit characters
ECE 545 – Introduction to VHDL 13
Predefined enumeration types (2)
severity_level (note, warning, error, failure)
Predefined in VHDL-93 only:
file_open_kind(read_mode, write_mode, append_mode)
file_open_status (open_ok, status_error, name_error, mode_error)
ECE 545 – Introduction to VHDL 14
User-defined enumeration types - Examples
type state is (S0, S1);
type alu_function is (disable, pass, add, subtract,
multiply, divide);
type octal_digit is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’);
type mixed is (lf, cr, ht, ‘-’, ‘/‘, ‘\’);
Each value in an enumeration type must be either
an identifier or a character literal
ECE 545 – Introduction to VHDL 15
Floating-Point Types
ECE 545 – Introduction to VHDL 16
Floating point types
• Used to represent real numbers• Numbers are represented using a significand
(mantissa) part and an exponent part• Conform to the IEEE standard 754 or 854
Minimum size of representation that must besupported by the implementation of the VHDLstandard:
VHDL-2001: 64-bit representationVHDL-87, VHDL-93: 32-bit representation
ECE 545 – Introduction to VHDL 17
Real literals - examples
23.1 23.1
46E5 46 105
1E+12 1 1012
1.234E09 1.234 109
34.0e-08 34.0 10-8
2#0.101#E5 0.1012 25 =(2-1+2-3) 25
8#0.4#E-6 0.48 8-6 = (4 8-1) 8-6
16#0.a5#E-8 0.a516 16-8 =(1016-1+516-2) 16-8
ECE 545 – Introduction to VHDL 18
The ANSI/IEEE standard floating-point number representation formats
ECE 545 – Introduction to VHDL 19
User-defined floating-point types - Examples
type input_level is range -10.0 to +10.0
type probability is range 0.0 to 1.0;
constant max_output: real := 1.0E6;constant min_output: real := 1.0E-6;type output_range is max_output downto min_output;
ECE 545 – Introduction to VHDL 20
Attributes of Scalar Types
ECE 545 – Introduction to VHDL 21
Attributes of all scalar types
T’left first (leftmost) value in TT’right last (rightmost) value in TT’low least value in TT’high greatest value in T
Not available in VHDL-87:T’ascending
true if T is an ascending range, false otherwise
T’image(x) a string representing the value of xT’value(s) the value in T that is represented by s
ECE 545 – Introduction to VHDL 22
type index_range is range 21 downto 11;
index_range’left = 21index_range’right = 11index_range’low = 11index_range’high = 21index_range’ascending = falseindex_range’image(14) = “14”index_range’value(“20”) = 20
Attributes of all scalar types - examples
ECE 545 – Introduction to VHDL 23
Attributes of discrete types
T’pos(x) position number of x in T
T’val(n) value in T at position n
T’succ(x) value in T at position one greater than position of x
T’pred(x) value in T at position one less than position of x
T’leftof(x) value in T at position one to the left of x
T’rightof(x) value in T at position one to the right of x
ECE 545 – Introduction to VHDL 24
type logic_level is (unknown, low, undriven, high);
logic_level’pos(unknown)= 0logic_level’val(3) = highlogic_level’succ(unknown) = lowlogic_level’pred(undriven) = lowlogic_level’leftof(unknown) errorlogic_level’rightof(undriven) = high
Attributes of discrete types - examples
ECE 545 – Introduction to VHDL 25
Subtypes
ECE 545 – Introduction to VHDL 26
Subtype
• Defines a subset of a base type values• A condition that is used to determine which
values are included in the subtype is called a constraint
• All operations that are applicable to the base type also apply to any of its subtypes
• Base type and subtype can be mixed in the operations, but the result must belong to the subtype, otherwise an error is generated.
ECE 545 – Introduction to VHDL 27
Predefined subtypes
natural integers 0
positive integers > 0
Not predefined in VHDL-87:
delay_lengthtime 0
ECE 545 – Introduction to VHDL 28
User-defined subtypes - Examples
subtype bit_index is integer range 31 downto 0;
subtype input_range is real range 1.0E-9 to 1.0E+12;
ECE 545 – Introduction to VHDL 29
Operators
ECE 545 – Introduction to VHDL 30
Operators (1)
ECE 545 – Introduction to VHDL 31
Operators (2)
ECE 545 – Introduction to VHDL 32
Operators (3)
ECE 545 – Introduction to VHDL 33
Operator Overloading
ECE 545 – Introduction to VHDL 34
Operator overloading
• Operator overloading allows different argument types for a given operation (function)
• The VHDL tools resolve which of these function to select based on the types of the inputs
• This selection is transparent to the user as long as the function has been defined for the given argument types.
ECE 545 – Introduction to VHDL 35
Different declarations for the same operator - Example
Declarations in the package ieee.std_logic_unsigned:
function “+” ( L: std_logic_vector; R:std_logic_vector)
return std_logic_vector;
function “+” ( L: std_logic_vector; R: integer)
return std_logic_vector;
function “+” ( L: std_logic_vector; R:std_logic)
return std_logic_vector;
ECE 545 – Introduction to VHDL 36
Different declarations for the same operator - Example
signal count: std_logic_vector(7 downto 0);
You can use:
count <= count + “0000_0001”;
or
count <= count + 1;
or
count <= count + ‘1’;
ECE 545 – Introduction to VHDL 37
Specifying time in VHDL
ECE 545 – Introduction to VHDL 38
Physical data types
Types representing physical quantities, such as time, voltage, capacitance, etc. are referred in VHDL as physical data types.
TIME is the only predefined physical data type.
Value of the physical data type is called a physical literal.
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Time values (physical literals) - Examples
7 ns
1 min
min
10.65 us
10.65 fs
Unit of time
(dimension)
SpaceNumeric value
ECE 545 – Introduction to VHDL 40
TIME values
Numeric value can be an integer or
a floating point number.
Numeric value is optional. If not given, 1 is
implied.
Numeric value and dimension MUST be
separated by a space.
ECE 545 – Introduction to VHDL 41
Units of time
Unit Definition
Base Unit
fs femtoseconds (10-15 seconds)
Derived Units
ps picoseconds (10-12 seconds)
ns nanoseconds (10-9 seconds)
us microseconds (10-6 seconds)
ms miliseconds (10-3 seconds)
sec seconds
min minutes (60 seconds)
hr hours (3600 seconds)
ECE 545 – Introduction to VHDL 42
Values of the type TIME
Value of a physical literal is defined in terms
of integral multiples of the base unit, e.g.
10.65 us = 10,650,000,000 fs
10.65 fs = 10 fs
Smallest available resolution in VHDL is 1 fs.
Smallest available resolution in simulation can be
set using a simulator command or parameter.
ECE 545 – Introduction to VHDL 43
Arithmetic operations on values of the type TIME
Examples:
7 ns + 10 ns = 17 ns
1.2 ns – 12.6 ps = 1187400 fs
5 ns * 4.3 = 21.5 ns
20 ns / 5ns = 4
ECE 545 – Introduction to VHDL 44
Propagation delay in VHDL
ECE 545 – Introduction to VHDL 45
Propagation delay in VHDL - Example
entity MAJORITY isport (A_IN, B_IN, C_IN : in STD_LOGIC; Z_OUT : out STD_LOGIC);end MAJORITY;
architecture DATA_FLOW of MAJORITY isbeginZ_OUT <= (not A_IN and B_IN and C_IN) or
(A_IN and not B_IN and C_IN) or(A_IN and B_IN and not C_IN) or(A_IN and B_IN and C_IN) after 20 ns;
end DATA_FLOW;
ECE 545 – Introduction to VHDL 46
Propagation delay - Example
ECE 545 – Introduction to VHDL 47
MLU: Block Diagram
B
A
NEG_A
NEG_B
IN0
IN1
IN2
IN3 OUTPUT
SEL1
SEL0
MUX_4_1
L0L1
NEG_Y
Y
Y1
A1
B1
MUX_0
MUX_1
MUX_2
MUX_3
ECE 545 – Introduction to VHDL 48
MLU - Architecture Body – Example 1begin
A1<= not A after 6 ns when (NEG_A='1') elseA after 5 ns;
B1<= not B after 6 ns when (NEG_B='1') else B after 5 ns;
Y <= not Y1 after 6 ns when (NEG_Y='1') elseY1 after 5 ns;
MUX_0 <= A1 and B1 after 3 ns;MUX_1 <= A1 or B1 after 3 ns;MUX_2 <= A1 xor B1 after 4 ns;MUX_3 <= A1 xnor B1 after 5 ns;
L<=L1 & L0;
with (L) select Y1 <= MUX_0 after 7 ns when "00",
MUX_1 after 6 ns when "01", MUX_2 after 8 ns when "10",
MUX_3 after 7 ns when others;
end MLU_DATAFLOW;
ECE 545 – Introduction to VHDL 49
MLU - Architecture Body – Example 2begin
A1<= not A after MUX2_delay when (NEG_A='1') elseA after MUX_2_delay;
B1<= not B after MUX2_delay when (NEG_B='1') else B after MUX2_delay;
Y <= not Y1 after MUX2_delay when (NEG_Y='1') elseY1 after MUX2_delay;
MUX_0 <= A1 and B1 after GATE_delay;MUX_1 <= A1 or B1 after GATE_delay;MUX_2 <= A1 xor B1 after XOR_delay;MUX_3 <= A1 xnor B1 after XOR_delay;
L<=L1 & L0;
with (L) select Y1 <= MUX_0 after MUX4_delay when "00",
MUX_1 after MUX4_delay when "01", MUX_2 after MUX4_delay when "10",
MUX_3 after MUX4_delay when others;
end MLU_DATAFLOW;
ECE 545 – Introduction to VHDL 50
Delay constants
constant MUX2_delay: time := 5 ns;
constant GATE_delay : time := 3 ns;
constant XOR_delay : time := 4 ns;
constant MUX4_delay: time := 7 ns;
Can be defined in the declarative portion
of the architecture or in the package
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Inertial delay model
ECE 545 – Introduction to VHDL 52
Inertial delay model
Short pulses (spikes) are not passed to the
outputs of logic gates due to the inertia of
physical systems.
Logic gates behave like low pass filters and
effectively filter out high frequency input
changes as if they never occurred.
ECE 545 – Introduction to VHDL 53
Inertial delay model - Example
SIG_OUT <= not SIG_IN after 7 ns
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VHDL-87 Inertial delay model
Any input signal change that does not persist
for at least a propagation delay of the device
is not reflected at the output.
inertial delay (pulse rejection limit) = propagation delay
ECE 545 – Introduction to VHDL 55
VHDL-93 Enhanced inertial delay model
VHDL-93 allows the inertial delay model to be declaredexplicitly as well as implicitly.
Explicitly:Z_OUT <= inertial (not A_IN and B_IN and C_IN) or
(A_IN and not B_IN and C_IN) or(A_IN and B_IN and not C_IN) or(A_IN and B_IN and C_IN) after 20 ns;
Implicitly:Z_OUT <= (not A_IN and B_IN and C_IN) or
(A_IN and not B_IN and C_IN) or(A_IN and B_IN and not C_IN) or(A_IN and B_IN and C_IN) after 20 ns;
ECE 545 – Introduction to VHDL 56
VHDL-93 Enhanced inertial delay model
VHDL-93 allows inertial delay, also called
a pulse rejection limit, to be different from the
propagation delay.
SIG_OUT <= reject 5 ns inertial not SIG_IN after 7 ns;
ECE 545 – Introduction to VHDL 57
Transport delay model
With a transport delay model, all input signal
changes are reflected at the output, regardless of
how long the signal changes persist.
Transport delay model must be declared explicitly using the
keyword transport.
Inertial delay model is a default delay model because it
reflects better the actual behavior of logic components.
Transport delay model is used for high-level modeling.
ECE 545 – Introduction to VHDL 58
Transport delay model - Example
SIG_OUT <= transport not SIG_IN after 7 ns
ECE 545 – Introduction to VHDL 59
Other delay models
Rise and Fall delays
- a different delay for a transition 0→1
and a transition 1→0
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Event-driven simulation
ECE 545 – Introduction to VHDL 61
Event list as a linked list structure
time
signalnew value
List of events scheduled
to occur at time tq
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Event list as an array – Timing wheel
time
signalnew value
List of events scheduled
to occur at time tc
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Notation
(i, vi’) – an entry of the event list associated with the time t indicating that at the time t the value of signal i is scheduled to be set to vi’
v(i) – current value at the output of gate i
d(i) – nominal delay of gate i
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Top-level algorithm
while (event list not empty)
begin
t = next time in list
process entries for time t
end
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Process entries for time t - Basic version
Activated = Ø /* set of activated gates = empty set */
For every entry (i, vi’) pending at the current time t if vi’ ≠ v(i) then
begin /* it is indeed an event */v(i) = vi’ /* update value of signal i */for every j on the fanout list of i
beginupdate input values of jadd j to Activated
endend
For every j Activatedbegin
vj’ = evaluate(j)schedule (j, vj’) for time t+d(j)
end
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Event-driven simulation - example
(z, 1)
8 10 12
(z, 0) (z, 0)
time
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Notation
lsv(j) – last scheduled value of j
lst(j) – last scheduled time of j = time of the last event scheduled for signal j
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Delta delay
ECE 545 – Introduction to VHDL 69
Delta delay
A propagation delay of 0 time units is
equivalent to omitting the after clause and is
called a delta delay.
Used for functional simulation.
ECE 545 – Introduction to VHDL 70
Two-dimensional aspect of time
ECE 545 – Introduction to VHDL 71
Top-level algorithm
while (event list not empty)
begin
t = next time in list
process entries for time t
end
If next time in list
= previous time
then the previous
iteration of the
loop has advanced
time by one
delta delay
ECE 545 – Introduction to VHDL 72
Transactions vs. Events
ECE 545 – Introduction to VHDL 73
Transaction vs. Event
T5 = T1+20 ns
Z_OUT transactions
Z_OUT events
(‘0’, T1 + 20 ns) (‘1’, T2 + 20 ns) (‘0’, T3 + 20 ns)
(‘1’, T2 + 20 ns) (‘0’, T3 + 20 ns)
ECE 545 – Introduction to VHDL 74
Properties of signals
Signals represent a time-ordered list of valuesdenoting past, present and future values.
This time history of a signal is called a waveform.
A value/time pair (v, t) is called a transaction.
If a transaction changes value of a signal, it iscalled an event.
ECE 545 – Introduction to VHDL 75
Signal Attributes
ECE 545 – Introduction to VHDL 76
Signal attributes (1)
S’transaction - a signal of type bit that changes value from ‘0’ to ‘1’ or vice versa each time there is a transaction on S.
S’event - True if there is an event on S in the current simulation cycle, false otherwise.
S’active – True if there is a transaction on S in a given simulation cycle, false otherwise.
ECE 545 – Introduction to VHDL 77
Signal attributes (2)
S’last_event - The time interval since the last event on S.
S’last_active - The time interval since the last transaction on S.
S’last_value – The value of S just before the last event on S.
ECE 545 – Introduction to VHDL 78
Signal attributes (3)
S’delayed(T) - A signal that takes on the same value as S, but is delayed by time T.
S’stable(T) - A Boolean signal that is true if there has been no event on S in the time interval T up to the current time, otherwise false.
S’quiet(T) – A Boolean signal that is true if there has been no transaction on S in the time interval T up to the current time, otherwise false.
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Detecting setup time violation
if clk’event and clk=‘1’ then
assert d’last_event >= setup_time
report “Setup time violation”
ECE 545 – Introduction to VHDL 80
algorithmic
Design level
register-transfer
gate
transistor
layout
devices
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