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EE141EE141--Fall 2004Fall 2004Digital Integrated Digital Integrated CircuitsCircuits
TuThTuTh 9:309:30--1111521 Cory521 Cory
Instructor: Borivoje Nikolić
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What is this class all about?What is this class all about?Introduction to digital integrated circuits.
CMOS devices and manufacturing technology. CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Combinational and sequential circuits. Timing and clocking. Arithmetic, interconnect, and memories. Design methodologies.
What will you learn?Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability
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ImpressionsImpressionsGood:
“I learned a lot and the professor was really good”“I am now (designing a microprocessor) at Intel and things here are exactly like you said in the lecture”“The most exciting class I ever had.”
Bad:“The project was too hard/time consuming.”“Need more guidance in the project.”“Lectures hard to follow.”
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Practical InformationPractical InformationInstructor
Prof. Borivoje Nikolic570 Cory Hall, 643-9297, bora@eecsOffice hours: Mo 10:30am-12pm, Th 11:00am-12:00pm
TAs:Stanley Wang, sbtwang@eecs
Office hours: Th 2:30-3:30pm, 353 CoryHenry Jen, henryjen@eecs
Office hours: W 12-1pm, 353 Cory
Web page: http://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141_f04/
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Discussions and LabsDiscussions and LabsDiscussion sessions
M 1-2pm, Henry Jen, 285 Cory M 5-6pm, Stanley Wang, 293 CorySame material in both sessions!
Labs (353 Cory)Tu 3:30-6:30pmW 9am-12pmTh 3:30-6:30pm
Please choose one lab session and stick with it!
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TAmtng
M
T
W
R
F
8 9 10 11 12 1 2 3 4 5 6
Lab(Stanley)
353 Cory
Lab(Henry/Stanley)
353 Cory
Lab(Henry)353 Cory
OH(Bora)570 Cory
DISC*(Henry)
285 Cory
DISC*(Stanley)
293 Cory
Lec(Bora)521 Cory
ProblemSets Due
Lec(Bora)521 Cory
* Discussion sections will cover identical material
OH(Bora)570 Cory
OH(Henry)353 Cory
OH(Stanley)
353 Cory
Your EECS141 WeekYour EECS141 Week
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Class OrganizationClass Organization
10 AssignmentsOne design project with three phasesLabs: 6 software, 1 hardware2 midterms, 1 final
Midterm 1: Tuesday, October 19, evening Midterm 2: Tuesday, November 16, eveningFinal: Thursday, December 16, 8-11am
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Some Important AnnouncementsSome Important Announcements
Please don’t bring food/drinks to 353 CoryPlease use the newsgroup for asking questions (ucb.class.ee141)Project is done in pairsHomework is done individuallyDon’t even think about cheating!
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Grading PolicyGrading Policy
Homeworks: 10%Labs: 10%Projects: 20%Midterms: 30%Final: 30%
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Class MaterialClass MaterialTextbook: “Digital Integrated Circuits – A Design Perspective”, 2nd ed, by J. Rabaey, A. Chandrakasan, B. NikolicClass notes: Web pageLab Reader:Available on the web page!Selected material will be made available from Copy
CentralCheck web page for the availability of tools
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The Web SiteThe Web SiteClass and lecture notesAssignments and solutionsLab and project informationExamsMany other goodies …
The sole source of informationhttp://www-inst.eecs.berkeley.edu/~ee141
Print only what you need: Save a tree!
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SoftwareSoftware
CadenceIndustry standardOnline tutorialsWe discontinued the use of MicroMagic in this class
HSPICE and IRSIM for simulation
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Getting StartedGetting Started
Assignment 1: Getting SPICE to work –see web-pageDue next Thursday, September 9, 5pmNO discussion sessions or labs this week.First discussion sessions in Week 2First Software Lab in Week 3
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Digital Integrated CircuitsDigital Integrated CircuitsIntroduction: Issues in digital designThe CMOS inverterCombinational logic structuresSequential logic gatesDesign methodologiesInterconnect: R, L and CTimingArithmetic building blocksMemories and array structures
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IntroductionIntroduction
Why is designing digital ICs different today than it was before?Will it change in future?
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The First ComputerThe First Computer
The BabbageDifference Engine(1832)25,000 partscost: £17,470
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ENIAC ENIAC -- The First Electronic Computer (1946)The First Electronic Computer (1946)
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The Transistor RevolutionThe Transistor Revolution
First transistorBell Labs, 1948
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The First Integrated Circuits The First Integrated Circuits
Bipolar logic1960’s
ECL 3-input GateMotorola 1966
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Intel 4004 MicroprocessorIntel 4004 Microprocessor
19711000 transistors1 MHz operation
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Intel Pentium 4 MicroprocessorIntel Pentium 4 Microprocessor
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MooreMoore’’s Laws Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months
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MooreMoore’’s Laws Law16151413121110
9876543210
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG
2 OF
THE
NU
MB
ER O
FC
OM
PON
ENTS
PER
INTE
GR
ATE
D F
UN
CTI
ON
Electronics, April 19, 1965.
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Evolution in ComplexityEvolution in Complexity
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Transistor CountsTransistor Counts
1,000,000
100,000
10,000
1,000
10
100
11975 1980 1985 1990 1995 2000 2005 2010
808680286
i386i486
Pentium®Pentium® Pro
K 1 Billion 1 Billion TransistorsTransistors
Source: IntelSource: Intel
ProjectedProjected
Pentium® IIPentium® III
Courtesy, Intel
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MooreMoore’’s Law in Microprocessorss Law in Microprocessors
400480088080
8085 8086286
386486 Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010Year
Tran
sist
ors
(MT)
2X growth in 1.96 years!
Transistors on lead microprocessors double every 2 years
Courtesy, Intel
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FrequencyFrequency
P6Pentium ® proc
48638628680868085
8080800840040.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Freq
uenc
y (M
hz)
Lead microprocessors frequency doubles every 2 years
Doubles every2 years
Courtesy, Intel
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Power DissipationPower DissipationP6
Pentium ® proc
486386
2868086
808580808008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Pow
er (W
atts
)
Lead microprocessor power continues to increase
Courtesy, Intel
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Power Will Be a Major ProblemPower Will Be a Major Problem5KW
18KW
1.5KW 500W
400480088080
80858086
286386
486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Pow
er (W
atts
)
Power delivery and dissipation will be prohibitive
Courtesy, Intel
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Power DensityPower Density
400480088080
8085
8086
286 386486
Pentium® procP6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Pow
er D
ensi
ty (W
/cm
2)
Hot Plate
Nuclear Reactor
Rocket Nozzle
S. Borkar
Sun’s Surface
Power density too high to keep junctions at low temp
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Not Only MicroprocessorsNot Only Microprocessors
Digital Cellular Market(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog Baseband
Digital Baseband(DSP + MCU)
PowerManagement
Small Signal RF
PowerRF
(data from Texas Instruments)(data from Texas Instruments)
CellPhone
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Productivity TrendsProductivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000Logic Tr./ChipTr./Staff Month.
xxxx
xx
x21%/Yr. compound
Productivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Logi
c Tr
ansi
stor
per
Chi
p(M
)
0.01
0.1
1
10
100
1,000
10,000
100,000
Prod
uctiv
ity(K
) Tra
ns./S
taff
-Mo.
Source: Sematech
Complexity outpaces design productivity
Com
plex
ity
Courtesy, ITRS Roadmap
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Why Scaling?Why Scaling?Technology shrinks by 0.7/generationWith every generation can integrate 2x more functions per chip; chip cost does not increase significantlyCost of a function decreases by 2xBut …
How to design chips with more and more functions?Design engineering population does not double every two years…
Hence, a need for more efficient design methodsExploit different levels of abstraction
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Challenges in Digital DesignChallenges in Digital Design
“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.
…and There’s a Lot of Them!
∝ DSM ∝ 1/DSM
?
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Design Abstraction LevelsDesign Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
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This ClassThis ClassIntroduces basic metrics for design of integrated circuits – how to measure delay, power, etc.Groups layout rectangles into transistors and wires
Transistors and wires into gatesGates into functions(Functional blocks into systems) – e.g. EECS150
Need to verify that the assumptions are valid
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Next LectureNext Lecture
Introduces basic metrics for design of integrated circuits – how to measure delay, power, cost, etc.Brief intro to IC manufacturing and design
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