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FET BiasingFixed Biased Configuration
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Group Members
Hafiz Aamir Hafeez BCE-FA10-010
Yasir Jameel BCE-FA10-051
Farooq Hassan BCE-FA10-045
M.Awais Sattar BCE-FA10-031
Muazzam Ali BCE-FA10-025
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Introduction
For the JFET, the relationship between input andoutput quantities is nonlinear due to the squaredterm in Shockleys equation.
Nonlinear functions results in curves as obtained
for transfer characteristic of a JFET. Graphical approach will be used to examine the dc
analysis for FET because it is most popularly usedrather than mathematical approach
The input of BJT and FET controlling variables arethe current and the voltage levels respectively
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JFETs differ from BJTs:
Nonlinear relationship between input (VGS) and
output (ID) JFETs are voltage controlled devices, whereas
BJTs are current controlled
Introduction
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Common FET Biasing Circuits
JFET
Fixed Bias
Self Bias
Voltage Divider Bias
Depletion-Type MOSFET
Self Bias
Voltage Divider Bias
Enhancement-Type MOSFET
Feedback Configuration
Voltage Divider Bias
Introduction
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General Relationships
For all FETs:
For JFETs and Depletion-Type MOSFETs:
For Enhancement-Type MOSFETs:
AIG
0
SDII
2
P
GS
DSSD )V
V(1II
2)(
TGSDVVkI
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Fixed-Bias Configuration
The configuration includes the ac levels Vi and Voand the coupling capacitors.
The resistor is present to ensure that Vi appearsat the input to the FET amplifier for the ACanalysis.
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Fixed-Bias Configuration For the DC analysis,
Capacitors are open circuits
and
The zero-volt drop across RG permits replacing RG by a short-circuit
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AIG
0 VRARIVGGGRG
0)0(
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Fixed-Bias Configuration
Investigating the input loop IG=0A, therefore
VRG=IGRG=0V
Applying KVL for the input loop,
-VGG-VGS=0
VGG= -VGS
It is called fixed-bias configurationdue to VGG is a
fixed power supply so VGS is fixed
The resulting current,
10
2)1(P
GS
DSSDV
VII
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Investigating the graphical approach. Using below tables, we
can draw the graph
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VGS
ID
0 IDSS
0.3VP IDSS/2
0.5VP IDSS/4
VP 0mA
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In graph the fixed level of VGShas been superimposed as avertical line atVGS=-VGG. At any point on the
vertical line, the level of VGSis-VGGthe levelof IDmust simply bedetermined on this verticalline. The point where the two
curves intersect is thecommon solution to theconfiguration commonlyreferred to as thequiescentor operating point.The subscript Qwill be appliedto drain current andgate-to-source voltage toidentify their levels at the Q-
point.
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Output loop
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DDDDDSRIVV
VVS
0
SDDS VVV
SDSDVVV 0
SV
DSDVV
SGGSVVV
SGSGVVV 0
SV
GSGVV
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EXAMPLE
Determine the following for the network of FIG(a) VGSQ(b) IDQ(c) VDS(d) VD(e) VG(f) VS
Solution :(a) VGSQ= -VGG= - 2 V(b) IDQ=IDSS(1-VGS/vP)
2= 10 mA(1 - 0.25)2 = 10mA(0.75)2 =10 mA(0.5625)= 5.625 mA(c) VDS=VDD- IDRD
= 16 V - (5.625mA)(2k)=16 V - 11.25 V = 4.75 V(d) VD= VDS=4.75 V(e) VG= VGS=2 V
(f) VS= 0 V
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Graphical Approach
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Ad t f FET
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Advantages of FET
The main advantage of the FET is its high inputresistance, on the order of 100M ohms or more.Thus, it is a voltage-controlled device, andshows a high degree of isolation between inputand output. It is a unipolar device, dependingonly upon majority current flow. It is less noisyand is thus found in FM tuners for quiet
reception. It is relatively immune to radiation. Itexhibits no offset voltage at zero drain currentand hence makes an excellent signal chopper. Ittypically has better thermal stability than a BJT.
Disadvantages of FET It has relatively low gain-bandwidth product
compared to a BJT. The MOSFET has adrawback of being very susceptible to overload
voltages, thus requiring special handling during
U
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UsesIGBTs see application in switching internal combustion engine ignitioncoils, where fast switching and voltage blocking capabilities areimportant.The most commonly used FET is the MOSFET. The CMOS
(complementary metal oxide semiconductor) process technology isthe basis for modern digital integrated circuits. This processtechnology uses an arrangement where the (usually "enhancement-mode") p-channel MOSFET and n-channel MOSFET are connected inseries such that when one is on, the other is off.
The fragile insulating layer of the MOSFET between the gate andchannel makes it vulnerable to electrostatic damage during handling.This is not usually a problem after the device has been installed in aproperly designed circuit.In FETs electrons can flow in either direction through the channel
when operated in the linear mode, and the naming convention of drainterminal and source terminal is somewhat arbitrary, as the devices aretypically (but not always) built symmetrically from source to drain. Thismakes FETs suitable for switching analog signals between paths(multiplexing). With this concept, one can construct a solid-statemixing board, for example.A common use of the FET is as an amplifier. For example, due to its
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