7-1Logic System Design I
Combinatorial Logic Design Practices
ECGR2181
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Logic System Design I 7-2
Documentation Standards
Block diagrams– first step in hierarchical design
Schematic diagramsHDL programs (ABEL, Verilog, VHDL)Timing diagramsCircuit descriptions
Logic System Design I 7-3
Block Diagram
Logic System Design I 7-4
Flat schematic structure
Logic System Design I 7-5
Hierarchichalschematic structure
Logic System Design I 7-6
Other Documentation
Timing diagrams– Output from simulator– Specialized timing-diagram drawing tools
Circuit descriptions– Text (word processing)– Can be as big as a book– Typically incorporate other elements (block diagrams, timing
diagrams, etc.)
Logic System Design I 7-7
Signal names and active levels
Signal names are chosen to be descriptive.Active levels -- HIGH or LOW
– named condition or action occurs in either the HIGH or the LOW state, according to the active-level designation in the name.
Logic System Design I 7-8
Example
LogicCircuit
HIGH when error occurs
ERROROK_L
LogicCircuit
LOW when error occurs
ERROR_L ERROR
ERROR1_L
Logic System Design I 7-9
Microprocessor
A15A14A13A12A11A10
A9A8A7A6A5A4A3A2A1A0
ALE
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ALE
ALE
ADDR15 LA15
LA14
LA13
LA12
LA11
LA10
LA7
LA8
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
D7DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
D6D5D4D3D2D1D0
MIORDYMEMIO
RD_LREAD
WR_L
RD_L
WR_LWRITE
CONTROL
DATA[7:0]
ADDR[15:0]
LA[15:0]
DB[7:0]
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
READY
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
2,3
2
2
Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e
Logic System Design I 7-10
GO
READY
DAT
(b)
GO
READY
DAT
(c)(a)
t
GO
ENB
READY
DAT
DAT
RDY
RDYmin
DATmax
DATmin
RDYmax
DAT
RDY
t
t
t
t
t t
t
Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e
Logic System Design I 7-11
tOUTmax
WRITE_L
DATAIN
DATAOUT
(a)
STEP[7:0]
(b)
tOUTmin
must be stable
tsetup thold
new dataold
00FF 01 02 03
COUNT
CLEAR
Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e
Logic System Design I 7-12
Example – Timing Diagram
Logic System Design I 7-13
Programmable Logic Arrays (PLAs)
Any combinational logic function can be realized as a sum of products.
Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections.– n inputs
• AND gates have 2n inputs -- true and complement of each variable.
– m outputs, driven by large OR gates• Each AND gate is programmably connected to each output’s
OR gate.– p AND gates (p<<2n)
Logic System Design I 7-14
Example: 4x3 PLA, 6 product terms
Logic System Design I 7-15
Programmable Array Logic (PALs)
How beneficial is product sharing?– Not enough to justify the extra AND array
PALs ==> fixed OR array– Each AND gate is permanently connected to a certain OR gate.
Example: PAL16L8
Logic System Design I 7-16
10 primary inputs8 outputs, with 7 ANDs per
output1 AND for 3-state enable6 outputs available as inputs
– more inputs, at expense of outputs
– two-pass logic, helper terms
Note inversion on outputs– output is complement of sum-of-
products– newer PALs have selectable
inversion
Logic System Design I 7-17
Designing with PALs
Compare number of inputs and outputs of the problem with available resources in the PAL.
Write equations for each output using HDL.Compile the HDL program, determine whether minimized
equations fit in the available AND terms.If no fit, try modifying equations.
Logic System Design I 7-18
Decoders
General decoder structure
Typically n inputs, 2n outputs– 2-to-4, 3-to-8, 4-to-16, etc.
Logic System Design I 7-19
Binary 2-to-4 decoder
Note “x” (don’t care) notation.
Logic System Design I 7-20
2-to-4-decoder logic diagram
Logic System Design I 7-21
Architecture
built-in librarycomponents
positionalcorrespondencewith entity definition
Example: 2-to-4 decoder
Logic System Design I 7-22
Decoder Symbol
Logic System Design I 7-23
MSI 2-to-4 decoder
Input buffering (less load)NAND gates (faster)
Logic System Design I 7-24
Complete 74x139 Decoder
Logic System Design I 7-25
3-to-8 decoder
Logic System Design I 7-26
74x138 3-to-8-decoder symbol
Logic System Design I 7-27
Dataflow-style program for 3-to-8 decoder
Logic System Design I 7-28
Dataflow-style program for 3-to-8 decoder
Logic System Design I 7-29
Decoder cascading
4-to-16 decoder
Logic System Design I 7-30
More cascading
5-to-32 decoder
Logic System Design I 7-31
Decoder applications
Microprocessor memory systems– selecting different banks of memory
Microprocessor input/output systems– selecting different devices
Microprocessor instruction decoding– enabling different functional units
Memory chips– enabling different rows of memory depending on address
Logic System Design I 7-32
Example – Microprocessor ApplicationMicroprocessor
A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0
ALE
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ALE
ALE
ADDR15 LA15
LA14
LA13
LA12
LA11
LA10
LA7
LA8
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
D7DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
D6D5D4D3D2D1D0
MIORDYMEMIO
RD_LREAD
WR_L
RD_L
WR_LWRITE
CONTROL
DATA[7:0]
ADDR[15:0]
LA[15:0]
DB[7:0]
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
READY
LA7
LA6
LA5
LA4
LA3
LA2
LA1
LA0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
2,3
2
2
Copyright © 2000 by Prentice Hall, Inc. Digital Design Principles and Practices, 3/e
Logic System Design I 7-33
Encoders vs. Decoders
Decoder Encoder
Logic System Design I 7-34
Binary encoders
Logic System Design I 7-35
Need priority in most applications
Logic System Design I 7-36
8-input priority encoder
Logic System Design I 7-37
Priority-encoder logic equations
Logic System Design I 7-38
74x148 8-input priority encoder
– Active-low I/O– Enable Input– “Got Something”– Enable Output
Logic System Design I 7-39
74x148 circuit
Logic System Design I 7-40
74x148 Truth Table
Logic System Design I 7-41
Cascading priority encoders
32-inputpriority encoder
Logic System Design I 7-42
Multiplexers
Logic System Design I 7-43
Multiplexer - Gate-Level Modeling - Verilog
2-to-1 Multiplexer
// 2-to-1 Multiplexer modulemodule mux_2 (out, i0, i1, sel); // headerinput i0, i1, sel; // input & output portsoutput out;wire x1, x2, x3; // internal netsor (out, x2, x3); // form outputand (x2, i0, x1); // i0 • sel’and (x3, i1, sel); // i1 • selnot (x1, sel); // invert selendmodule
Logic System Design I 7-44
Multiplexer - Dataflow Modeling - Verilog
4-bit Multiplexer
// Four-bit 2-to-1 multiplexermodule mux_4bit (Out, A, B, sel);input [3:0] A, B;input sel;output [3:0] Out;assign Out = sel ? B, A;endmodule
Logic System Design I 7-45
Multiplexer - Behavioral Modeling - Verilog
Conditional Statementsmodule mux4_to_1 (A, B, C, D, OUT, select);input [7:0] A, B, C, D;input [1:0] select;output [7:0] OUT;reg [7:0] OUT;always @ (A or B or C or D or select)case (select)
2’d0: OUT = A;2’d1: OUT = B;2’d2: OUT = C;2’d3: OUT = D;
endcaseend
Logic System Design I 7-46
74x1518-input multiplexer
Logic System Design I 7-47
74x151 truth table
Logic System Design I 7-48
CMOS transmission gates
2-input multiplexer
Logic System Design I 7-49
Other multiplexer varieties
2-input, 4-bit-wide– 74x157
4-input, 2-bit-wide– 74x153
Logic System Design I 7-50
Barrel shifter design example
n data inputs, n data outputsControl inputs specify number of positions to rotate or shift
data inputsExample: n = 16
– DIN[15:0], DOUT[15:0], S[3:0] (shift amount)
Many possible solutions, all based on multiplexers
Logic System Design I 7-51
16 16-to-1 muxes
16-to-1 mux = 2 x 74x151 8-to-1 mux+ NAND gate
Logic System Design I 7-52
4 16-bit 2-to-1 muxes
16-bit 2-to-1 mux = 4 x 74x157 4-bit 2-to-1 mux
Logic System Design I 7-53
Properties of different approaches
Logic System Design I 7-54
2-input XOR gates
Like an OR gate, but excludes the case where both inputs are 1.
XNOR: complement of XOR
Logic System Design I 7-55
XOR and XNOR symbols
Logic System Design I 7-56
Gate-level XOR circuits
No direct realization with just a few transistors.
Logic System Design I 7-57
Equality Comparators1-bit comparator
4-bit comparator
EQ_L
Logic System Design I 7-58
8-bit Magnitude Comparator
Logic System Design I 7-59
Other conditions
Logic System Design I 7-60
Adders
Basic building block is “full adder”– 1-bit-wide adder, produces sum and carry outputs
Truth table:
X Y Cin S Cout
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
Logic System Design I 7-61
Full-adder circuit
Logic System Design I 7-62
Ripple adder
Speed limited by carry chainFaster adders eliminate or limit carry chain
– 2-level AND-OR logic ==> 2n product terms– 3 or 4 levels of logic, carry lookahead
Logic System Design I 7-63
74x2834-bit adder
Uses carry lookaheadinternally
Logic System Design I 7-64
“generate”
“propagate”
“half sum”
carry-in from previous stage
Logic System Design I 7-65
Ripple carry between groups
Logic System Design I 7-66
Lookahead carry between groups
Logic System Design I 7-67
Subtraction
Subtraction is the same as addition of the two’s complement.The two’s complement is the bit-by-bit complement plus 1.Therefore, X – Y = X + Y + 1 .
– Complement Y inputs to adder, set Cin to 1.– For a borrow, set Cin to 0.
Logic System Design I 7-68
Full subtractor = full adder, almost
Logic System Design I 7-69
Multipliers
8x8 multiplier
Logic System Design I 7-70
Full-adder array
Logic System Design I 7-71
Faster carry chain
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