VHDL Design Principles - Personal Web Pagesjmconrad/ECGR2181-2005-01/...Logic System Design I 6-1...
Transcript of VHDL Design Principles - Personal Web Pagesjmconrad/ECGR2181-2005-01/...Logic System Design I 6-1...
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6-1Logic System Design I
VHDL DesignPrinciples
ECGR2181Extra Notes
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port (I: in STD_LOGIC_VECTOR (1 to 9);EVEN, ODD: out STD_LOGIC
);
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Logic System Design I 6-2
HDL-based design flow
– For ASICs, verification and fitting phases are usually much longer (as a fraction of overall project time) than what you’ve experienced in class.
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Logic System Design I 6-3
VHDL
Developed in the mid-1980s under DoD sponsorship– Mandated for federally-sponsored VLSI designs
Used for design description, simulation, and synthesis– Synthesis became practical in the early 90s and use of VHDL (and
Verilog) has taken off since then
Only a subset of the language can be synthesized
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Logic System Design I 6-4
VHDL entity and architecture concept
System is a collection of modules.Architecture: detailed description of the internal structure
or behavior of a module.Entity: a “wrapper” for the architecture that exposes only
its external interfaces, hiding the internal details.
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Logic System Design I 6-5
VHDL Hierarchy
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Logic System Design I 6-6
VHDL program file structure
Entity and architecture definitions for different modules can be in different files.– Compiler maintains “work” library and keeps track of
definitions using entity and architecture names.
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Logic System Design I 6-7
VHDL -- designed by committee
Tries to be all things to all people.– Result -- very general, but also very complex.
Standard logic values and elements are not built-in.
Standard logic defined by a “package”, IEEE 1164 STD_LOGIC.– Must be explicitly “used” by program.
library name package name
Use all definitions in package
Compiler knows where to find this (system-dependent)
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Logic System Design I 6-8
Standard logic values -- not just 0,1
Need additional values for simulation, three-state logic, pull-ups, etc.– Defined in IEEE 1164 STD_LOGIC package.
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Logic System Design I 6-9
Logic functions defined by table lookup
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Logic System Design I 6-10
VHDL strong typing
Every signal, variable, function parameter, and function result has a “type”.– A few built-in types, plus user defined types.
In assignment statements, comparisons, and function calls, types must match.
Commonly used IEEE-1164 types:– STD_LOGIC (one bit)
– STD_LOGIC_VECTOR(range) (multibit vector)– INTEGER (built-in integer type)
Pain in the neck: Must explicitly convert between INTEGERand STD_LOGIC_VECTOR.
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Logic System Design I 6-11
library IEEE;use IEEE.std_logic_1164.all;
entity parity9 isport (
I: in STD_LOGIC_VECTOR (1 to 9);
EVEN, ODD: out STD_LOGIC);
end parity9;
architecture parity9p of parity9 isbeginprocess (I)variable p : STD_LOGIC;variable j : INTEGER;beginp := I(1);for j in 2 to 9 loopif I(j) = '1' then p := not p; end if;
end loop;ODD <= p;EVEN <= not p;
end process;end parity9p;
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Logic System Design I 6-12
VHDL programming styles
Structural– Define explicit components and the connections
between them.– Textual equivalent of drawing a schematic
Dataflow– Assign expressions to signals– Includes “when” and “select” (case) statements
Behavioral– Write an algorithm that describes the circuit’s output– May not be synthesizable or may lead to a very large
circuit– Primarily used for simulation
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Logic System Design I 6-13
Example: 2-to-4 decoder
Entity
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Logic System Design I 6-14
Architecture
built-in librarycomponents
positionalcorrespondencewith entity definition
Example: 2-to-4 decoder
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Logic System Design I 6-15
Dataflow-style program for 3-to-8 decoder
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Logic System Design I 6-16
Dataflow-style program for 3-to-8 decoder
Note: All assignment statements operate concurrently (combinational circuit ).
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Logic System Design I 6-17
Behavioral program style
Normally uses VHDL “processes”Each VHDL process executes in parallel with other VHDL
processes and concurrent statements“Concurrent” statements include assignment and select
statements in dataflow-style programsConcurrency is needed to model the behavior of parallel,
interconnected hardware elementsBut “sequential” statements can be used within a process
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Logic System Design I 6-18
VHDL process
A sequence of “sequential statements”.
Activated when any signal in the “sensitivity list” changes.
Primarily a simulation concept, but can be synthesized
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Logic System Design I 6-19
Behavioral version of 74x138
Except for different syntax, approach is not all that different from the dataflow version
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Logic System Design I 6-20
Truly behavioral version
May not be synthesizable, or may have a slow or inefficient realization. But just fine for simulation and verification.
type conversion
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Logic System Design I 6-21
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
--Declaration of the module's inputs and outputsentity fewgates is port (
A: in std_logic;B: in std_logic;C: in std_logic;Y: out std_logic );
end fewgates;
--Defining the modules behaviorArchitecture behavioral of fewgates is beginprocess (A, B, C) begin
Y <= C OR ((NOT A) AND (NOT B));end process;end behavioral;
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Logic System Design I 6-22
More VHDL
Powerful facilities for generating iterative circuit descriptions (e.g., multiplier array)
Facilities for modeling timing behavior of known componentsProgram I/O facilities for use in simulationDesign-management facilities for selecting alternative
components and architecturesAnd more...