Chapter 7
Digital Arithmetic and Arithmetic Circuits
2
Signed/Unsigned Binary Numbers
• Signed Binary Number:– A binary number of fixed length whose sign (+/–)
is represented by one bit (usually MSB) and its magnitude by the remaining bits.
• Unsigned Binary Number:– A binary number of fixed length whose sign is not
specified by a bit. All bits are magnitude and the sign is assumed +.
3
Unsigned Binary Arithmetic
• Sum:– Result of an Addition Operation of two (or more)
binary numbers (operands).
• Carry:– A digit (or bit) that is carried over to the next most
significant bit during an n-Bit addition operation.
• The carry bit is a 1 if the result was too large to be expressed in n bits.
4
Basic Rules (Unsigned)
One-Bit Unsigned Addition
1 1 1 1 1
0 1 1 1 0
1 0 0 1 0
0 0 0 0 0
C B A C outin
5
Binary Addition Examples
bit outCarry
101000001 11100
00100111 1010
10101110 10010
1111 next tocarry 1
bit outCarry
101000001 11100
00100111 1010
10101110 10010
1111 next tocarry 1
6
Basic Subtraction
• Basic Subtraction of x = a – b, with a = minuend, b = subtrahend, and x = difference or result.
• Requires a Borrow Bit if a < b.• There are other forms of subtraction such
as 2’s Complement Addition used by microprocessors (such as in a PC).
7
Basic Subtraction Rules
1 1 1 - 1 1
0 0 1 - 1 0
1 0 0 - 1 0
0 0 0 - 0 0
DiffBorrow in
BAB
8
Binary Subtraction with Borrow Examples
1 0101
1 10 101 -
LSB to ripplesBorrow 0111(10) 10000
1 010
1 100 1001 -
StageBorrow 110(10) 1110
9
Signed Binary Numbers – 1
• Sign Bit:– A bit (usually the MSB) that indicates
whether a number is positive (= 0) or negative (= 1).
• Magnitude Bits:– The bits of a signed binary number that tell
how large it is in value.
10
Signed Binary Numbers – 2
• True-Magnitude Form:– A form of signed binary whose magnitude
bits are the TRUE binary form (not complements).
11
Signed Binary Numbers – 3
• 1’s Complement:– A form of signed binary in which negative numbers
are created by complementing all bits.
• 2’s Complement:– A form of signed binary in which the negative
numbers are created by complementing all the bits and adding a 1 (1’s Complement + 1).
12
True-Magnitude Form
• 5-Bit Numbers Negative Sign (S = 1)• +25 = 011001 (Note sign bit (MSB) Sign = 0)• –25 = 111001 (Same as +25 with sign = 1)• +12 = 001100• –12 = 101100
13
1’s Complement Form
• 8-Bit 1’s Complement Negative (S = 1)
• +57 = 00111001
• –57 = 11000110 (All Bits Inverted)
• +72 = 01001000
• –72 = 10110111
14
2’s Complement Form• Used in MPU (PC) Arithmetic
1000 1011
1
0111 1011 72-
0111 1011
1
0110 1100 57-
1001 0011 57
15
Signed Binary Addition (8-Bit)
• Signed Addition Positive (S = 0)
• Similar to binary addition with a sign bit.
1001 0101
1011 0100 75
1100 0001 30
16
Subtraction with 1’s Complement• Add the 1’s Complement and then Carry.
• Uses an End around carry addition method.
1111 0000
1
1110 0000 1
65) Comp s(1' 1110 1011 65)( 0001 0100 65 -
0000 0101 80)( 0000 0101 80
17
2’s Complement Subtraction
• Add 2’s Complement to Minuend.
ResultfromBitCarryDiscard
11110000111110101165
111110110001010065
000001010000010180
18
Negative Results
• If the True-Magnitude Form is used for subtraction, the results are incorrect.
• If the result is from 1’s or 2’s Complement and the result is negative (S = 1), the magnitude is found by taking the complement of the result.
19
Negative Result Example• 2’s Complement Negative Result
(65 – 80)
)(-159 1111 0000 )15( Result Final
1 1 d Ad
1110 0000 Invert
0001 1111
0000 011 1 C.) s(2' 0000 1011 80-
0001 0100 0001 0100 65
1010
20
Range of Signed Numbers
• Range of Positive Numbers is 0 to 2n – 1 for a number with n magnitude bits.
• Range of Negative Numbers is –1 to –2n for a number with n magnitude bits.
• 8-Bit Example:8-Bit Number Range is –2n x +2n – 1
or –128 to +127
21
Sign Bit Overflow• Overflow:
– An erroneous carry into the sign bit of a signed binary number
– Results from a sum or difference that is larger than can be represented by the magnitude bits.
• Results in a False Positive or False Negative Number.
22
False Negative Overflow
• Addition of two 8-Bit Positive Numbers:
• Two positive numbers added with a result greater than the range of +127 for 8-bit numbers causes an overflow.
(False) Negative is Result 1011 1010
0000 0110 96
1011 0100 75
23
False Positive Overflow• Addition of two 8-Bit Negative Numbers:
• Two Negative numbers were added to produce a False Positive Result due to overflowing the negative range of 8-bit numbers (0 to –127).
(False) Positive is Result 1111 0110
1111 1011 65
0000 1011 80
24
Hexadecimal Addition
• Similar to decimal addition with a range of digits of 0 to 9 and A to F.
• Examples:
F + 1 = 10
F + F = 1E
F + F + 1 = 1F
25 414FH Hex
4)(15) ( 1) 4)( (
9)(12) 1)(10)( (
(11)(3) 6) 2)( (
1 1 Carry
5)(16)(20)(1 (3)
9)(12) 1)(10)( ( 1A9CH
3) (11)( 6) 2)( ( 26B3H
Equivalent Decimal Hex
Hexadecimal Addition
• For sums greater than 15, subtract 16 and carry 1 to the next position.
26
Hexadecimal Subtraction
C17H Hex
7) ( (1) 0)(12)(
(12) (9) (10) (1) -
3) (10)(16 6) (1)(16
1 1 Borrow
position. previous the from
)(16 10Hborrow digit, tsignifican least the subtract To
(12)(1)(10)(9) 1A9CH
(3)(2)(6)(11) 26B3H
Equivalent Decimal Hex
10
27
BCD Codes
• BCD Code (Binary-Coded Decimal): A code used to represent each decimal digit of a number by a 4-Bit Binary Value.
• Valid Digits for 0 to 9 are 0000 to 1001.– The binary codes 1010 to 1111 are invalid
• Called an 8421 Code due to the decimal weight of each bit position.
28
BCD Examples
• Each digit is a 4-Bit Binary group:
(84)10 = 1000 0100
(4987)10 = 0100 1001 1000 0111BCD
29
Excess-3 Code
• A BCD Code formed by adding 3 (0011) to its true 4-bit binary value.
• Excess-3 is a self-complementing code:– A negative code equivalent can be found by
inverting the binary bits of the positive code
• Inverting the bits of the Excess-3 digit yields 9’s Complement of the decimal equivalent.
30
Excess-3 Examples
• 3 = 0011 + 0011 = 0110 = 6 in E3.
• 1 = 0001 + 0011 = 0100 = 4 in E3.
• If we complement 1 = 1011 in E3, this is the code for an 8.– 9’s Complement of 1 = (9 – 1) = 8 (Self-
Complement)
31
Gray Code
• A binary code that progresses so that only one bit changes between two successive codes.
32
Gray Code and Binary
• Binary: b3b2b1b0
• Gray: g3g2g1g0
• Gray code bits can be defined as follows:
g3 = b3
g2 = b3 b2
g1 = b2 b1
g0 = b1 b0
33
ASCII Code
• American Standard Code for Information Interchange.
• A seven-bit alphanumeric code used to represent text letters, numerals, punctuation, and special controls.
• An expanded 8-bit form is becoming more widespread.
34
Binary Adders
• Half Adder (HA): A circuit that will add two bits and produce a sum bit and a carry bit.
• Full Adder (FA): A circuit that will add a carry bit from another HA or FA and two operand bits to produce a sum bit and a carry bit.
35
Basic HA Addition
• Binary Two-Bit Addition Rules:
0 + 0 = 00
0 + 1 = 01
1 + 1 = 10
36
HA Circuit• Basic Equations: S = A XOR B, C = A and B
where S = Sum and C = Carry.• Truth Table for HA Block:
1 1 1 1
0 1 0 1
0 1 1 0
0 0 0 0
OUTCBA Σ
OUT ABC
BABABA
37
HA Circuit
38
Full Adder Basics
• Adds a CIN input to the HA block.
• Equations are modified as follows:
• A FA can be made from two HA blocks and an OR Gate.
IN
INOUT
) (
) (
CBA
A BCBAC
39
Full Adder Basics
40
Full Adder Basics
41
Full Adder Basics
42
Parallel Adders
• A circuit, consisting of n full adders, that will add n-bit binary numbers.
• The output consists of n sum bits and a carry bit.
• COUT of one full adder is connected to CIN of the next full adder.
43
Parallel Adders
44
Ripple Carry – 1
• In the n-Bit Parallel Adder (FA Stages) the Carryout is generated by the last stage (FAN).
• This is called a Ripple Carry Adder because the final carryout (Last Stage) is based on a ripple through each stage by CIN at the LSB Stage.
45
Ripple Carry – 2
• Each Stage will have a propagation delay on the CIN to COUT of one AND Gate and one OR Gate.
• A 4-Bit Ripple Carry Adder will then have a propagation delay on the final COUT of 4 2 = 8 Gates.
• A 32-Bit adder such as in an MPU in a PC could have a delay of 64 Gates.
46
Ripple Carry - 3
47
Look-Ahead Carry – 1
• Fast Carry or Look-Ahead Carry:– A combinational network that generates
the final COUT directly from the operand bits (A1 to An, B1 to Bn).
– It is independent of the operations of each FA Stage (as the ripple carry is).
48
Look Ahead Carry – 2
• Fast Carry has a small propagation delay compared to the ripple carry.
• The fast carry delay is 3 Gates for a 4-Bit Adder compared to 8 for the Ripple Carry.
49
Parallel Adder
• Created in VHDL by using multiple instances of a full adder component in the top-level file of a VHDL design hierarchy.
50
Parallel Adder
51
VHDL Full AdderENTITY full_add IS PORT( a, b, c_in : IN STD_LOGIC; c_out, sum : OUT STD_LOGIC; END full_add;
ARCHITECTURE adder OF full_add ISBEGIN c_out <= ((a xor b) and c_in) or (a and b); sum <= (a xor b) xor c_ini;END adder;
52
Parallel Adder VHDL
• Requires a separate component file for a full adder, saved in a folder where the compiler can find it.
• A component declaration statement in the top-level file of the design hierarchy.
• A component instantiation statement for each instance of the full adder component.
53
Parallel Adder VHDL Code – 1ENTITY add4par IS PORT( c0 : IN STD_LOGIC; a,b : IN STD_LOGIC_VECTOR (4
downto 1); c4 : OUT STD_LOGIC; sum : OUT STD_LOGIC_VECTOR (4
downto 1);END add4par;
54
Parallel Adder VHDL Code – 2ARCHITECTURE adder OF add4par IS -- Component declaration. COMPONENT full_add PORT( a, b, c_in : IN STD_LOGIC; c_out, sum : OUT STD_LOGIC; END COMPONENT; -- Define a signal for the internal carry bits SIGNAL c : STD_LOGIC_VECTOR (3 downto 1);
55
Parallel Adder VHDL Code – 3BEGIN-- four component instantiation statements. adder1 : full_add PORT MAP (a => a(1), b => b(1),
c_in => c0, c_out => c(1) -- connects to c_in of adder 2. sum => sum(1)); • • • • • •END adder;
56
VHDL Generate Statement – 1ENTITY add4gen IS PORT( c0 : IN STD_LOGIC; a,b : IN STD_LOGIC_VECTOR (4
downto 1); c4 : OUT STD_LOGIC; sum : OUT STD_LOGIC_VECTOR
(4 downto 1));END add4gen;
57
VHDL Generate Statement – 2
ARCHITECTURE adder OF add4gen IS -- Component declaration COMPONENT full_add PORT( a, b, c_in :IN STD_LOGIC; c_out, sum : OUT STD_LOGIC; END COMPONENT; - - Defining a signal for internal carry bits. SIGNAL c : STD_LOGIC_VECTOR (4 downto 0);
58
VHDL Generate Statement – 3BEGIN c(0) <= c0; -- Input port c0 mapped to internal signal (c0)
adders: FOR i IN 1 to 4 GENERATE -- Implicit port mapping. adder : full_add PORT MAP (a(i), b(i), c(i-1), c(i), sum (i)); END GENERATE; c4 <= c(4); -- Output port c4 mapped to internal signal c(4)END adder;
59
Subtractor (2’s Complement) – 1
• The concept of Subtraction using 2’s Complement addition allows a Parallel FA to be used.
• This could be used in a MPU ALU (Arithmetic Logic Unit) for Subtraction.
• The subtract operation involves adding the inverse of the subtrahend to the minuend and then adding a 1.
60
Subtractor (2’s Complement) – 2
• • This operation can be done in a parallel n-Bit
FA by inverting (B1 to Bn) and connecting CIN at the LSB Stage to +5 V.
• The circuit can be modified to allow either the ADD or SUBTRACT operation to be performed.
1Difference BABA
61
Subtractor (2’s Complement) 2
62
Parallel Binary Adder/Subtractor
• XOR gates are used as programmable inverters to pass binary numbers (e.g., B1B2B3B4) to the parallel adder in true or complemented form.
•
• form. true its in is 0, /SUBADD When
ed.complement is 1,/SUBADD When
B
B
63
Parallel Binary Adder/Subtractor
64
Parallel Binary Adder/Subtractor
65
VHDL Parallel Binary Adder/Subtractor – 1
ENTITY addsub4g IS
PORT(
sub : IN BIT;
a,b : IN BIT_VECTOR (4 downto 1);
c4 : OUT BIT;
sum : OUT BIT_VECTOR (4 downto 1));
END addsub4g;
66
VHDL Parallel Binary Adder/Subtractor – 2
ARCHITECTURE adder OF addsub4g IS COMPONENT full_add PORT( a, b, c_in : IN BIT; c_out : OUT BIT); END COMPONENT; - - Define a signal for internal carry bits SIGNAL c : BIT_VECTOR (4 downto 0); SIGNAL b_comp : BIT_VECTOR (4 downto 1);BEGIN
67
VHDL Parallel Binary Adder/Subtractor – 3
- - add/subtract select to carry input (sub = 1 for subtract)
c(0) <= sub;
adders:
FOR i IN 1 to 4 GENERATE
--invert b for subtract function (b(i) xor 1,)
--do not invert b for add function (b(i) xor 0)
b_comp(i) <= b(i) xor sub;
adder: full_add PORT MAP (a(i), b_comp(i), c(I -1), c(i), sum (i));
END GENERATE;
C4 <= C(4);
END adder;
68
Overflow
• If the sign bits of both operands are the same and the sign bit of the sum is different from the operand sign bits, an overflow has occurred.
• Overflow is not possible if the sign bits of the operands are different from each other.
69
Overflow Examples• Adding two 8-bit negative numbers:
• Adding two 8-bit positive numbers:
)1overflow;bit(Sign000010000
00001000
H100
H8000001000H80
V
)1overflow;bit(Sign00001000
00010000
H80
H0111110111FH7
V
70
Overflow 8-bit Parallel Adder
sum) of bit Sign ( S SS
) of bit Sign ( B B S
) of bit Sign ( A AS
1234567
B1234567B
A1234567A
S S S S SS
BS B B B BB
AS A AA AA
71
Overflow Detector Truth TableSA SB S V
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
SSSSSSV BABA
72
Overflow Detector Truth Table
73
BCD Adder
• A Parallel Adder whose output sum is in groups of 4 bits, each representing a BCD (8421) Digit.
• Basic design is a 4-Bit Binary Parallel Adder to generate a 4-Bit Sum of A + B.
• Sum is input to the four-bit input of a Binary-to-BCD Code Converter.
74
BCD Adder
Top Related