April 2011
AMS 2010.2Product update
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Eldo Premier
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Eldo Premier
Dramatically accelerate transistor-level SPICE-accurate simulation of large circuits
Released with AMS 2010.2 (Feb 2011), can be used in Cadence environment in 2010.2a (April 2011)
SPEED : 2.5x on average, up to 20x
ACCURACY : same as Eldo
CAPACITY : ~10M devices, i.e. ~10x Eldo ADMS Premier will be released in 2010.2b, June 2011
3
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Eldo Premier : Technology and use model
Eldo
Brand new matrix solver and algebra, fully hierarchical
Hierarchy extraction for optimized partitioning
Native multi-threading
LTE timestep control
Same netlist, device models
and outputs as Eldo
Learning curve : 30 sec
Use .option premier or
eldo –premier switch
4
KernelHierarchical
Kernel
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Positioning - Classic/Premier/ADiT
SPICE
Cell Char.―Small‖ IP
―Large‖ IPFull-chip
Eldo ClassicSign-off accuracy
Up to ~1M devices
Eldo PremierSign-off accuracy
Higher performanceUp to ~10M devices
ADiTRelaxed functional accuracy
Highest performanceUp to ~50M devices
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Target & Value
Target
Verify L.A.R.G.E. Analog & Mixed-Signal IP's— PLLs and DLLs, transceivers,
ADC, DAC, DC-DC converters,power management, automotive,memory/TFT critical path…
Value
Increased Productivity and Yield— Run nominal simulation much faster— Run PVT corners to reduce risks of silicon re-spins— Improve manufacturing yield
6 AMS 2010.2 Updates, Feb 2011
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Usage: Multi-threading
Must be explicitly requested using Eldo MT option — -use_proc
MT efficiency depends on:— Hardware: Computer architecture, cache sizes and memory
bandwidth— Circuit hierarchy
Verilog-A instances and controlled sources are multi-threaded as well
AMS 2010.2 Updates, Feb 2011
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Eldo 2010.2
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Eldo 2010.2 at a glance
Performance— New algorithms for Digital Cell Characterization : 2x speedup— Dynamic Multi-threading : performance++ on LSF/Grid— New Monte Carlo plans : speedup through LHS and QMC
Functionality and Usability— New Eldo Control Language : build complex simulations plans— Differential Loop Stability : analyze stability issues easily— Graphical plot of SOA violations : debug design more easily
Quality— ~230 defects fixed
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Max relative (%) error vs CPU time
0,00%
1,00%
2,00%
3,00%
4,00%
5,00%
6,00%
7,00%
0s 2s 4s 6s 8s 10s 12s 14s 16s 18s 20s
New Current
Speed improvements for Digital Cell Char.
New algorithms for Digital Cell Characterization— Accelerate high–accuracy cell characterization by ~2x or more— Same trend observed with UMC 65nm, TSMC 40nm and TSMC 28nm
Brute force MC1000 runs
Protocol measures max. relative and absolute deviations from ‗golden results‘, over 250+ measurements on a TSCM 40nm D flip-flop
This chart shows how the max. relative error (vertical) relates to the CPU time (horizontal)
The ‗Current ‘ settings (in red) vary EPS (1e-7, 5e-8, 2e-8, 1e-8, 5e-9)
The ‗New‘ settings (in green) vary the new option DCC_TUNING (fast, standard, accurate, vhigh)
The ‗new‘ settings allow reaching less than 1% max. error in 2x less CPU time
Note : for most CC customers,1% error is considered as unacceptable
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Speed improvements for Digital Cell Char.
New simple macro-options trigger the new algorithms :.option dcc_tuning=fast.option dcc_tuning=standard.option dcc_tuning=accurate.option dcc_tuning=vhigh
Other ‗regular‘ options (tuning, eps, reltol, absol/vntol) must be disabled for better performance
Accuracy mappings (indicative) :dcc_tuning=standard provides accuracy ‗comparable‘ to eps=1e-7dcc_tuning=accurate provides accuracy ‗comparable‘ to eps=1e-8dcc_tuning=vhigh provides accuracy ‗comparable‘ to eps=1e-9
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Eldo’s Monte-Carlo Autostop will Eliminate the Uncertainties & Improve Productivity
+/- 1m
Standard deviation varies around 0.04 dB
Criteria is not met
Add more samples (continue MC)+/- 1m
After 150 samples, not there yet …After 200 samples,
still not there yet
+/- 1m+/- 1m
Converged!
Eldo
Statistical Models(process, parameter mismatches…etc.)
Accuracy Constraint:Standard deviation of overshoot to vary less
than 0.001dB (1mV) for 100 samples
Exact amount of
CPU used to reach
the Accuracy!
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Smart Monte Carlo – continued…
New Monte Carlo sampling plans : LHS and QMC— Accelerate statistical analysis : obtain accurate sigma estimation
in less runs compared to brute force Monte Carlo
* LHS =Latin Hypercube Sampling. QMC = Quasi Monte Carlo
Brute force Monte Carlo,1000 runs
New LHS,1000 runs
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Dynamic multi-threading
Eldo now dynamically and continuously analyzes the optimal number of cores to use, during the simulation— May decide to use less cores than requested, if it‘s more effective— Allows optimal performance even on loaded machines— Critically important in LSF/Grid environments
Eldo now multi-threads the AC solution as well— Only of interest for huge networks, possibly power grid analysis
or similar not-so-frequent AC setup— Optimal number of cores dynamically adjusted
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Aging sensitivity
New analysis provides insights about which aging devices have the most impact on the outputs— Some devices may suffer from aging, but their degradation has
no or little impact upon the performance of the circuit— Some devices may exhibit seemingly minor aging degradation,
but this has a dramatic impact upon the outputs— .age analysis does not say anything about this question…— .age_sensitivity now tells the user what is important, and what is
less important— It is a complex, but flexible command :
supports absolute/normalized stress modes, device coupling, output specifications, sorting, etc.
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Eldo Control Language - ECL
New set of commands to allow implementing complex simulation sequences— Bypass the hard-coded logic of Eldo— Allow decisions, flow control (if/then/else), loops, file I/O…
With Eldo Control Language
Allows custom control of simulation sequence, custom logic and full control of output formatting
ResultResultsYour logic
.STEP
.DATA
.EXTRACT
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Eldo Control Language
Redefine your own commands and use them as usual :
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Differential Loop Stability analysis
.LSTB command used to support only single-ended configurations
Now extended to differential inputs and outputs
The legacy Eldo macro-models now support the regular Y syntax for instantiation (just like VerilogA models)
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Plotting SOA violations
New commands allow plotting SOA violations – analysis, instance, device, specific SOA :
.plot tran SOA
.plot SOA(X1.XBGP)
.plot SOA(X1.nch_mac.main)
.plot SOA(X1.3.M47#ciruit.cir#236)
Graphical outputsin EZwave :
New SOA browser in
Artist link
danger
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New system information section
Eldo now prints system information— machine, OS, number of cores, etc.
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Local subcircuit tolerances
The .localtol command has been extended to support many more accuracy/tuning parameters
It is now possible to assign local tolerances to groups of instances or groups of subcircuits, including wildcards
.localtol inst=(X1.*, X2.X3) subckt=(DFF, LATCH)
+ reltol=1e-3 reltrunc=1e-4
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Hiding auxiliary .extract
In some cases, .extract quantity is only an intermediate calculation, and needs to be filtered out from the outputs
New ‗visible‘ allows making .extract visible/invisible :
.extract tran label=tmp_r xup(v(out), 10n, 20n) visible=0
.extract tran label=tmp_f xdn(v(out), 20n, 30n) visible=0
.extract tran label=t_width extract(tmp_f)-extract(tmp_r)
Only useful output (t_width) will be printed to .aex, .chi etc.
Intermediate outputs (tmp_r) and (tmp_f) remain ‗invisible‘
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ADMS 2010.2
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ADMS in 2010.2
Mixed-signal UPF— Power for analog p-g pins, A2D and D2A converters
SystemVerilog ―bind‖ to mixed-signal context— Full power of SV assertion language in mixed-signal— Automatic insertion of A2D and D2A on ports of bound module— Including Spice as target!
Universal Coverage Database (UCDB) AMS integration— VHDL-AMS branch and assertion coverage— Spice SOA assertions
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Performance
The .localtol command controls local accuracy of a given instance— .optwin (control over fixed time windows) already exists
Init_signal_spy commands on mixed-signal nets are preserved across save/restart
No more partitioning!— choose your engine!
– Eldo– ADiT– Eldo Hierarchical
— Substantially improves simulation and elaboration time
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Gui and language enhancements
Contributor window enhancements— Analog (ADiT) and
digital contributions
Questa ―wildcard‖ filter— Effects add wave, add
list, find nets
Verilog-AMS Enhancements— Wreal objects— Verilog-AMS 2.3 support
VHDL-AMS Enhancements— Vector of records between VHDL and Spice— VHDL support for X and Z real values— Breakpoints (BP) and conditional breakpoints (WHEN) in batch
mode
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ADiT 2010.2
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Performance Improvement & Model Support
Multi-Rate for circuits containing multiple natural frequencies
— .OPTION ADIT_MR=0|1 ADIT_MR_DLW=0|1|2 — .OPTION ADIT_LOCAL Hierarchy_name MR=1 DLW=0|1|2
Support VHDL-AMS through ELDO/ADiT interface to solve the partitioning issue of Questa-ADMS-ADiT
Circuit 1 Circuit 2 Circuit 3 Circuit 4 Circuit 5
No MR 160h 16.5h 12h 25h 37h
MR 12h (13x) 4.9h (3x) 9.5h (1.2x) 12.5h (1.5x) 9h (4X)
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Circuit Check and Reliability
Support the most frequently-used ELDO SOA syntax.SETSOA [LABEL="string"] [TRAN] [SOACODE=num]+ D dname [SUBCKT=subckt_list|INST=inst_list] {param=(min,max[,xaxis])}.SETSOA [LABEL="string"] [TRAN] [SOACODE=num]+ M mname [SUBCKT=subckt_list|INST=inst_list] param=(min,max[,xaxis])}.SETSOA [LABEL="string"] [TRAN] [SOACODE=num]+ E {expression=(min,max[,xaxis])}.SETSOA [LABEL="string"] [TRAN] [SOACODE=num]+ E SUBCKT=subckt_list {param=(min,max[,xaxis])}
Support block-wise UDRM .DEFINE_GROUP group_name+ [SUBCKT=subckt_list][INST=inst_list][BLOCK=group_list][option_list].END_GROUP.AGE ... [SCOPE=group_list] ...
Hi-Z check with DC path report.OPTION ADIT_CHECK=”check_flag ... [DCPATH[=0|1|2]]
DCPATH=0 Default. No DC path is reported.DCPATH=1 Enable DC path report. Behavior model, e.g. Verilog-A are not included. DCPATH=2 Enable DC path report. Behavior model, e.g. Verilog-A are included.
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Ease-of-Use
Support .DSPF_INCLUDE DEV=SCH[EMATIC] and .IGNORE_DSPF_ON_NODE for selective back annotation— .IGNORE_DSPF_ON_NODE { node_name}
Statistics report for DSPF/SPEF annotation— .OPTION ADIT_SPF_STAT=2|1|0— 2: Default. Displays detailed annotation statistics. — 1: Displays a simple annotation statistics — 0: Disables the statistics report
Support ADiT output format TB0 in EZwave
Stop simulation at different simulation stage— -elabonly
– Terminates ADiT process immediately after the elaboration is completed— -partonly
– Terminates ADiT process immediately after the circuit partition is completed
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Artist Link 2010.2
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www.mentor.comArtist Link 2010.2 Updates, March 2011
Artist Link 2010.2 Updates
Supported Cadence versions— 5.1.41 USR4 & USR6— 6.1.3 & 6.1.4
Allow netlisting Spectre parameters for analogLib sources and primitives
New AMS Results Browser— Also standalone: $MGC_AMS_HOME/bin/amsrb [options] [file]
Support OCEAN scripting for Measurements and Extracts
Add Eldo extract mode
Allow Eldo localized options with .DEFINE_GROUP
Add netlist syntax and semantic check
Synchronize with Eldo's macro-models syntax
Update Eldo Multi-threading Options
No need of ghost tree to install AL anymore, made simpler by pointing to Cadence tree and setting some environment variables
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www.mentor.comArtist Link 2010.2 Updates, March 2011
Artist Link 2010.2 Updates – Continued
AMS Results Browser – SOA Violations
Cross-HighlightWith VirtuosoSchematics
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www.mentor.comArtist Link 2010.2 Updates, March 2011
Artist Link 2010.2 Updates – Continued
AMS Results Browser – Extracts
ExtractsExpressions
ExtractsValues
Or
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www.mentor.comArtist Link 2010.2 Updates, March 2011
Artist Link 2010.2 Updates – Continued
AMS Results Browser – Output
Content Filtering
Or
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EZwave 2010.2
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New Cursors— Eye Height at X— Eye Width at Y
Signal Integrity Analysis
Mask Testing— Industry-Standard Masks— Custom Masks— Offset/Margin Automatic Fit— Pass/Fail status
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Automatic Reload
Replace mode (default): — Previous loaded data is overwritten— Warning confirmation window is issued when overwriting
Keep mode:— Previous data is moved to <DB>_sim#.wdb — New results can be displayed automatically vs. previous ones
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Direct support for ADiT Outputs— TRAN .TR%, TB%, .SD% — AC .AC%— DC .DC%
New Format Support
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Display of Assertion
Questa-ADMS: VHDL(-AMS) assert
Eldo: Safe Operating Area (SOA)
Assertion State EZwave
INACTIVE
ACTIVE
FAILED SOA only
Assertion Event EZwave
START
PASSED
FAILED
ANTECEDENT
FAILED_UPPER_BOUND SOA only
FAILED_LOWER_BOUND SOA only
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Cursor Value Column
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Post Processing
Fast Fourier Transform— Symmetric (Default)— Periodic (New)
SSTNOISE Jitter— Absolute Jitter— Period Jitter— Long Term Jitter
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