XST User Guide - Boston University Electronics Design...
72
XST User Guide www.xilinx.com 29 1-800-255-7778 R Chapter 2 HDL Coding Techniques This chapter contains the following sections: • “Introduction” • “Signed/Unsigned Support” • “Registers” • “Tristates” • “Counters” • “Accumulators” • “Shift Registers” • “Dynamic Shift Register” • “Multiplexers” • “Decoders” • “Priority Encoders” • “Logical Shifters” • “Arithmetic Operations” • “RAMs/ROMs” • “State Machine” • “Black Box Support” Introduction Designs are usually made up of combinatorial logic and macros (for example, flip-flops, adders, subtractors, counters, FSMs, RAMs). The macros greatly improve performance of the synthesized designs. Therefore, it is important to use some coding techniques to model the macros so that they are optimally processed by XST. During its run, XST first tries to recognize (infer) as many macros as possible. Then all of these macros are passed to the Low Level Optimization step, either preserved as separate blocks or merged with surrounded logic in order to get better optimization results. This filtering depends on the type and size of a macro (for example, by default, 2-to-1 multiplexers are not preserved by the optimization engine). You have full control of the processing of inferred macros through synthesis constraints. Note: Please refer to Chapter 5, “Design Constraints,” for more details on constraints and their utilization. There is detailed information about the macro processing in the XST LOG file. It contains the following: 30 www.xilinx.com XST User Guide 1-800-255-7778 Chapter 2: HDL Coding Techniques R • The set of macros and associated signals, inferred by XST from the VHDL/Verilog source on a block by block basis. • The overall statistics of recognized macros. Note: Some additional macro processing and recognition is done during the Advanced HDL Synthesis step. • The number and type of macros preserved by low level optimization. The following log sample displays the set of recognized macros on a block by block basis. The following log sample displays the additional macro processing done during the Advanced HDL Synthesis step. Synthesizing Unit <timecore>. Related source file is timecore.vhd. Found finite state machine <FSM_0> for signal <state>. ... Found 7-bit subtractor for signal <fsm_sig1>. Found 7-bit subtractor for signal <fsm_sig2>. Found 7-bit register for signal <min>. Found 4-bit register for signal <points_tmp>. ... Summary: inferred 1 Finite State Machine(s). inferred 18 D-type flip-flop(s). inferred 10 Adder/Subtracter(s). Unit <timecore> synthesized. ... Synthesizing Unit <divider>. Related source file is divider.vhd. Found 18-bit up counter for signal <counter>. Found 1 1-bit 2-to-1 multiplexers. Summary: inferred 1 Counter(s). inferred 1 Multiplexer(s). Unit <divider> synthesized. ... =================================================== * Advanced HDL Synthesis * =================================================== Implementing FSM <FSM_0> on signal <current_state> on BRAM. INFO:Xst - Data output of ROM <Mrom_tmp_one_hot> in block <decode> is tied to register <one_hot> in block <decode>. INFO:Xst - The register is removed and the ROM is implemented as read- only block RAM. ...
Transcript of XST User Guide - Boston University Electronics Design...
XS
T U
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R
Cha
pter
2
HD
L C
odin
g Te
chni
ques
Thi
s ch
apte
r co
ntai
ns th
e fo
llow
ing
sect
ions
:
•“I
ntro
duc
tion
”
•“S
igne
d/
Uns
igne
d S
upp
ort”
•“R
egis
ters
”
•“T
rist
ates
”
•“C
ount
ers”
•“A
ccum
ulat
ors”
•“S
hift
Reg
iste
rs”
•“D
ynam
ic S
hift
Reg
iste
r”
•“M
ulti
plex
ers”
•“D
ecod
ers”
•“P
rior
ity
Enc
oder
s”
•“L
ogic
al S
hift
ers”
•“A
rith
met
ic O
pera
tion
s”
•“R
AM
s/R
OM
s”
•“S
tate
Mac
hine
”
•“B
lack
Box
Sup
port
”
Intr
od
uct
ion
Des
igns
are
usu
ally
mad
e up
of c
ombi
nato
rial
logi
c an
d m
acro
s (f
or e
xam
ple,
flip
-flo
ps,
add
ers,
su
btra
ctor
s, c
ount
ers,
FSM
s, R
AM
s). T
he m
acro
s gr
eatl
y im
prov
e pe
rfor
man
ce o
f th
e sy
nthe
size
d d
esig
ns. T
here
fore
, it i
s im
port
ant t
o u
se s
ome
cod
ing
tech
niqu
es to
mod
el
the
mac
ros
so th
at th
ey a
re o
ptim
ally
pro
cess
ed b
y X
ST.
Dur
ing
its
run,
XST
firs
t tri
es to
rec
ogni
ze (i
nfer
) as
man
y m
acro
s as
pos
sibl
e. T
hen
all o
f th
ese
mac
ros
are
pass
ed to
the
Low
Lev
el O
ptim
izat
ion
step
, eit
her
pres
erve
d a
s se
para
te
bloc
ks o
r m
erge
d w
ith
surr
ound
ed lo
gic
in o
rder
to g
et b
ette
r op
tim
izat
ion
resu
lts.
Thi
s fi
lter
ing
dep
end
s on
the
type
and
siz
e of
a m
acro
(for
exa
mpl
e, b
y d
efau
lt,
2-to
-1 m
ulti
plex
ers
are
not p
rese
rved
by
the
opti
miz
atio
n en
gine
). Yo
u ha
ve fu
ll co
ntro
l of
the
proc
essi
ng o
f inf
erre
d m
acro
s th
rou
gh s
ynth
esis
con
stra
ints
.
No
te:
Ple
ase
refe
r to
Cha
pter
5, “
Des
ign
Con
stra
ints
,” fo
r m
ore
deta
ils o
n co
nstr
aint
s an
d th
eir
utili
zatio
n.
The
re is
det
aile
d in
form
atio
n ab
out t
he m
acro
pro
cess
ing
in th
e X
ST L
OG
file
. It c
onta
ins
the
follo
win
g:
30
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pter
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L C
od
ing
Tec
hn
iqu
esR
•T
he s
et o
f mac
ros
and
asso
ciat
ed s
igna
ls, i
nfer
red
by
XST
from
the
VH
DL
/Ver
ilog
sour
ce o
n a
bloc
k by
blo
ck b
asis
.
•T
he o
vera
ll st
atis
tics
of r
ecog
nize
d m
acro
s.
No
te:
Som
e ad
ditio
nal m
acro
pro
cess
ing
and
reco
gniti
on is
don
e du
ring
the
Adv
ance
d H
DL
Syn
thes
is s
tep.
•T
he n
umbe
r an
d ty
pe o
f mac
ros
pres
erve
d b
y lo
w le
vel o
ptim
izat
ion.
The
follo
win
g lo
g sa
mpl
e d
ispl
ays
the
set o
f rec
ogni
zed
mac
ros
on a
blo
ck b
y bl
ock
basi
s.
The
follo
win
g lo
g sa
mpl
e d
ispl
ays
the
add
itio
nal m
acro
pro
cess
ing
don
e du
ring
the
Adv
ance
d H
DL
Syn
thes
is s
tep.
Synthesizing Unit <timecore>.
Related source file is timecore.vhd.
Found finite state machine <FSM_0> for signal <state>.
...
Found 7-bit subtractor for signal <fsm_sig1>.
Found 7-bit subtractor for signal <fsm_sig2>.
Found 7-bit register for signal <min>.
Found 4-bit register for signal <points_tmp>.
...
Summary:
inferred
1 Finite State Machine(s).
inferred
18 D-type flip-flop(s).
inferred
10 Adder/Subtracter(s).
Unit <timecore> synthesized.
...
Synthesizing Unit <divider>.
Related source file is divider.vhd.
Found 18-bit up counter for signal <counter>.
Found 1 1-bit 2-to-1 multiplexers.
Summary:
inferred
1 Counter(s).
inferred
1 Multiplexer(s).
Unit <divider> synthesized....
===================================================
*Advanced HDL Synthesis
*===================================================
Implementing FSM <FSM_0> on signal <current_state> on BRAM.
INFO:Xst - Data output of ROM <Mrom_tmp_one_hot> in block <decode> is
tied to register <one_hot> in block <decode>.
INFO:Xst - The register is removed and the ROM is implemented as read-
only block RAM.
...
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The
follo
win
g lo
g sa
mpl
e d
ispl
ays
the
over
all s
tati
stic
s of
rec
ogni
zed
mac
ros.
The
follo
win
g lo
g sa
mpl
e d
ispl
ays
the
num
ber
and
type
of m
acro
s p
rese
rved
by
low
leve
l op
tim
izat
ion.
...
===============================================
HDL Synthesis Report
Macro Statistics
# FSMs
: 1
# ROMs
: 4
16x7-bit ROM
: 4
# Registers
: 3
7-bit register
: 2
4-bit register
: 1
# Counters
: 1
18-bit up counter
: 1
# Multiplexers
: 1
2-to-1 multiplexer
: 1
# Adders/Subtractors
: 10
7-bit adder
: 4
7-bit subtractor
: 6
===============================================
...
...
===============================================
Final Results
...
Macro Statistics
# FSMs
: 1
# ROMs
: 4
16x7-bit ROM
: 4
# Registers
: 7
7-bit register
: 2
1-bit register
: 4
18-bit register
: 1
# Adders/Subtractors
: 11
7-bit adder
: 4
7-bit subtractor
: 6
18-bit adder
: 1
...
===============================================
...
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Tec
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iqu
esR
Thi
s ch
apte
r d
iscu
sses
the
follo
win
g M
acro
Blo
cks:
•R
egis
ters
•Tr
ista
tes
•C
ount
ers
•A
ccum
ula
tors
•Sh
ift R
egis
ters
•D
ynam
ic S
hift
Reg
iste
rs
•M
ulti
ple
xers
•D
ecod
ers
•P
rior
ity
Enc
oder
s
•L
ogic
al S
hift
ers
•A
rith
met
ic O
per
ator
s (A
dd
ers,
Su
btra
ctor
s, A
dde
rs/S
ubtr
acto
rs, C
ompa
rato
rs,
Mul
tip
liers
, Div
ider
s)
•R
AM
s
•St
ate
Mac
hine
s
•B
lack
Box
es
For
each
mac
ro, b
oth
VH
DL
and
Ver
ilog
exam
ples
are
giv
en. T
here
is a
lso
a lis
t of
cons
trai
nts
you
can
use
to c
ontr
ol th
e m
acro
pro
cess
ing
in X
ST.
No
te:
For
mac
ro im
plem
enta
tion
deta
ils p
leas
e re
fer
to C
hapt
er 3
, “F
PG
A O
ptim
izat
ion”
and
C
hapt
er 4
, “C
PLD
Opt
imiz
atio
n”.
Tabl
e2-
1 pr
ovid
es a
list
of a
ll th
e ex
amp
les
in th
is c
hap
ter,
as w
ell a
s a
list o
f VH
DL
and
V
erilo
g sy
nthe
sis
tem
pla
tes
avai
labl
e fr
om th
e L
angu
age
Tem
pla
tes
in P
roje
ct N
avig
ator
.
To a
cces
s th
e sy
nthe
sis
tem
plat
es fr
om P
roje
ct N
avig
ator
:
1.Se
lect
Ed
it→
Lan
gu
age
Tem
pla
tes.
..
2.C
lick
the
+ si
gn fo
r ei
ther
VH
DL
or
Veri
log.
3.C
lick
the
+ si
gn n
ext t
o Sy
nthe
sis
Tem
plat
es.
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Tabl
e 2-
1:V
HD
L a
nd
Ver
ilog
Exa
mp
les
and
Tem
pla
tes
Mac
ro B
lock
sC
hap
ter
Exa
mp
les
Lan
gu
age
Tem
pla
tes
Reg
iste
rsFl
ip-f
lop
wit
h Po
siti
ve-E
dge
C
lock
Flip
-flo
p w
ith
Neg
ativ
e-E
dge
Clo
ck a
nd
Asy
nchr
onou
s C
lear
Flip
-flo
p w
ith
Posi
tive
-Ed
ge
Clo
ck a
nd S
ynch
rono
us S
et
Flip
-flo
p w
ith
Posi
tive
-Ed
ge
Clo
ck a
nd C
lock
Ena
ble
Latc
h w
ith
Posi
tive
Gat
e
Latc
h w
ith
Posi
tive
Gat
e an
d A
sync
hron
ous
Cle
ar
Latc
h w
ith
Posi
tive
Gat
e an
d A
sync
hron
ous
Cle
ar
4-bi
t Lat
ch w
ith
Inve
rted
G
ate
and
Asy
nchr
onou
s Pr
eset
4-bi
t Reg
iste
r w
ith
Pos
itiv
e-Ed
ge C
lock
, Asy
nchr
onou
s Se
t and
Clo
ck E
nabl
e
D F
lip-F
lop
D F
lip-f
lop
wit
h A
sync
hron
ous
Res
et
D F
lip-F
lop
wit
h Sy
nchr
onou
s R
eset
D F
lip-F
lop
wit
h C
lock
Ena
ble
D L
atch
D L
atch
wit
h R
eset
Tris
tate
sD
escr
ipti
on U
sing
C
ombi
nato
rial
Pro
cess
and
A
lway
s B
lock
Des
crip
tion
Usi
ng
Con
curr
ent A
ssig
nmen
t
Proc
ess
Met
hod
(VH
DL
)A
lway
s M
etho
d (V
erilo
g)St
anda
lone
Met
hod
(VH
DL
and
Ve
rilo
g)
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esR
Cou
nter
s4-
bit U
nsig
ned
Up
Cou
nter
w
ith
Asy
nchr
onou
s C
lear
4-bi
t Uns
igne
d D
own
Cou
nter
wit
h Sy
nchr
onou
s Se
t
4-bi
t Uns
igne
d U
p C
ount
er
wit
h A
sync
hron
ous
Loa
d
from
Pri
mar
y In
put
4-bi
t Uns
igne
d U
p C
ount
er
wit
h Sy
nchr
onou
s L
oad
w
ith
a C
onst
ant
4-bi
t Uns
igne
d U
p C
ount
er
wit
h A
sync
hron
ous
Cle
ar
and
Clo
ck E
nabl
e
4-bi
t Uns
igne
d U
p/
Dow
n co
unte
r w
ith
Asy
nchr
onou
s C
lear
4-bi
t Sig
ned
Up
Cou
nter
w
ith
Asy
nchr
onou
s R
eset
4-bi
t asy
nchr
onou
s cou
nter
wit
h co
unt e
nabl
e, a
sync
hron
ous
rese
t and
syn
chro
nous
load
Acc
umul
ator
s4-
bit U
nsig
ned
Up
Acc
umul
ator
wit
h A
sync
hron
ous
Cle
ar
Non
e
Tabl
e 2-
1:V
HD
L a
nd
Ver
ilog
Exa
mp
les
and
Tem
pla
tes
Mac
ro B
lock
sC
hap
ter
Exa
mp
les
Lan
gu
age
Tem
pla
tes
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iste
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hift
-Lef
t Reg
iste
r wit
h Po
siti
ve-E
dge
Clo
ck, S
eria
l In
, and
Ser
ial O
ut
8-bi
t Shi
ft-L
eft R
egis
ter w
ith
Neg
ativ
e-E
dge
Clo
ck, C
lock
En
able
, Ser
ial I
n, a
nd S
eria
l O
ut
8-bi
t Shi
ft-L
eft R
egis
ter w
ith
Pos
itiv
e-E
dge
Clo
ck,
Asy
nchr
onou
s C
lear
, Ser
ial
In, a
nd S
eria
l Ou
t
8-bi
t Shi
ft-L
eft R
egis
ter w
ith
Pos
itiv
e-E
dge
Clo
ck,
Sync
hron
ous
Set,
Seri
al In
, an
d S
eria
l Ou
t
8-bi
t Shi
ft-L
eft R
egis
ter w
ith
Posi
tive
-Ed
ge C
lock
, Ser
ial
In, a
nd P
aral
lel O
ut
8-bi
t Shi
ft-L
eft R
egis
ter w
ith
Pos
itiv
e-E
dge
Clo
ck,
Asy
nchr
onou
s Pa
ralle
l Lo
ad, S
eria
l In,
and
Ser
ial
Out
8-bi
t Shi
ft-L
eft R
egis
ter w
ith
Pos
itiv
e-E
dge
Clo
ck,
Sync
hron
ous
Para
llel L
oad
, Se
rial
In, a
nd S
eria
l Out
8-bi
t Shi
ft-L
eft/
Shif
t-R
ight
R
egis
ter
wit
h P
osit
ive-
Edg
e C
lock
, Ser
ial I
n, a
nd P
aral
lel
Out
4-bi
t Loa
dab
le S
eria
l In
Seri
al
Out
Shi
ft R
egis
ter
4-bi
t Ser
ial I
n Pa
ralle
l ou
t Shi
ft
Reg
iste
r
4-bi
t Ser
ial I
n Se
rial
Out
Shi
ft
Reg
iste
r
Tabl
e 2-
1:V
HD
L a
nd
Ver
ilog
Exa
mp
les
and
Tem
pla
tes
Mac
ro B
lock
sC
hap
ter
Exa
mp
les
Lan
gu
age
Tem
pla
tes
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Mul
tipl
exer
s4-
to-1
1-b
it M
UX
usi
ng IF
St
atem
ent
4-to
-1 M
UX
Usi
ng C
ASE
St
atem
ent
4-to
-1 M
UX
Usi
ng T
rist
ate
Buff
ers
No
4-to
-1 M
UX
4-to
-1 M
UX
Des
ign
wit
h C
ASE
St
atem
ent
4-to
-1 M
UX
Des
ign
wit
h Tr
ista
te
Con
stru
ct
Dec
oder
sV
HD
L (O
ne-H
ot)
Veri
log
(One
-Hot
)
VH
DL
(One
-Col
d)
Veri
log
(One
-Col
d)
1-of
-8 D
ecod
er, S
ynch
rono
us
wit
h R
eset
Pri
orit
y E
ncod
ers
3-B
it 1
-of-
9 P
rior
ity
Enc
oder
8-to
-3 e
ncod
er, S
ynch
rono
us
wit
h R
eset
Log
ical
Shi
fter
sEx
ampl
e 1
Exam
ple
2
Exam
ple
3
Non
e
Dyn
amic
Shi
fter
s16
-bit
Dyn
amic
Shi
ft
Reg
iste
r w
ith
Pos
itiv
e-E
dge
Clo
ck, S
eria
l In
and
Ser
ial
Out
Non
e
Tabl
e 2-
1:V
HD
L a
nd
Ver
ilog
Exa
mp
les
and
Tem
pla
tes
Mac
ro B
lock
sC
hap
ter
Exa
mp
les
Lan
gu
age
Tem
pla
tes
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m37
1-
800-
255-
7778
Intr
od
uct
ion
R
Ari
thm
etic
Ope
rato
rsU
nsig
ned
8-b
it A
dd
er
Uns
igne
d 8
-bit
Ad
der
wit
h C
arry
In
Uns
igne
d 8
-bit
Ad
der
wit
h C
arry
Out
Uns
igne
d 8
-bit
Ad
der
wit
h C
arry
In a
nd C
arry
Ou
t
Sim
ple
Sign
ed 8
-bit
Ad
der
Uns
igne
d 8
-bit
Sub
trac
tor
Uns
igne
d 8
-bit
A
dd
er/S
ubt
ract
or
Uns
igne
d 8
-bit
Gre
ater
or
Equ
al C
ompa
rato
r
Uns
igne
d 8
x4-b
it M
ulti
plie
r
Div
isio
n B
y C
onst
ant 2
Res
ourc
e Sh
arin
g
N-B
it C
ompa
rato
r, Sy
nchr
onou
s w
ith
Res
et
Tabl
e 2-
1:V
HD
L a
nd
Ver
ilog
Exa
mp
les
and
Tem
pla
tes
Mac
ro B
lock
sC
hap
ter
Exa
mp
les
Lan
gu
age
Tem
pla
tes
38
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w.x
ilin
x.co
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ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Sig
ned
/Un
sig
ned
Su
pp
ort
Whe
n us
ing
Ver
ilog
or V
HD
L in
XST
, som
e m
acro
s, s
uch
as
add
ers
or c
ount
ers,
can
be
impl
emen
ted
for
sign
ed a
nd u
nsig
ned
val
ues.
For
Ver
ilog,
to e
nabl
e su
ppor
t for
sig
ned
and
uns
igne
d v
alue
s, y
ou m
ust e
nabl
e V
erilo
g-20
01. Y
ou c
an e
nabl
e it
by
sele
ctin
g th
e V
erilo
g 20
01 o
ptio
n un
der
the
Synt
hesi
s O
ptio
ns ta
b in
the
Pro
cess
Pro
pert
ies
dia
log
box
in P
roje
ct N
avig
ator
, or
by s
etti
ng th
e –v
erilo
g200
1 co
mm
and
line
opt
ion
to y
es. S
ee th
e “V
ER
ILO
G20
01”
sect
ion
in th
e C
onst
rain
ts G
uide
for
det
ails
.
RA
Ms
Sing
le-P
ort R
AM
wit
h A
sync
hron
ous
Rea
d
Sing
le-P
ort R
AM
wit
h "F
alse
" Sy
nchr
onou
s R
ead
Sing
le-P
ort R
AM
wit
h Sy
nchr
onou
s R
ead
(Rea
d
Thr
ough
)
Dua
l-Po
rt R
AM
wit
h A
sync
hron
ous
Rea
d
Dua
l-Po
rt R
AM
wit
h Fa
lse
Sync
hron
ous
Rea
d
Dua
l-Po
rt R
AM
wit
h Sy
nchr
onou
s R
ead
(Rea
d
Thr
ough
)
Dua
l-Po
rt B
lock
RA
M w
ith
Diff
eren
t Clo
cks
Blo
ck R
AM
wit
h R
eset
Mu
ltip
le-P
ort R
AM
D
escr
ipti
ons
Sing
le-P
ort B
lock
RA
M
Sing
le-P
ort D
istr
ibut
ed R
AM
Dua
l-Po
rt B
lock
RA
M
Dua
l-Po
rt D
istr
ibut
ed R
AM
Stat
e M
achi
nes
FSM
wit
h 1
Pro
cess
FSM
wit
h 2
Proc
esse
s
FSM
wit
h 3
Proc
esse
s
Bina
ry S
tate
Mac
hine
One
-Hot
Sta
te M
achi
ne
Bla
ck B
oxes
VH
DL
Veri
log
Non
e
Tabl
e 2-
1:V
HD
L a
nd
Ver
ilog
Exa
mp
les
and
Tem
pla
tes
Mac
ro B
lock
sC
hap
ter
Exa
mp
les
Lan
gu
age
Tem
pla
tes
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m39
1-
800-
255-
7778
Reg
iste
rsR
For
VH
DL
, dep
end
ing
on th
e op
erat
ion
and
type
of t
he o
pera
nds,
you
mus
t inc
lud
e ad
dit
iona
l pac
kage
s in
you
r co
de.
For
exa
mpl
e, in
ord
er to
cre
ate
an u
nsig
ned
ad
der
, you
ca
n us
e th
e fo
llow
ing
arit
hmet
ic p
acka
ges
and
type
s th
at o
pera
te o
n un
sign
ed v
alue
s:
To c
reat
e a
sign
ed a
dder
you
can
use
ari
thm
etic
pac
kage
s an
d ty
pes
that
ope
rate
on
sign
ed
valu
es.
Ple
ase
refe
r to
the
IEE
E V
HD
L M
anu
al fo
r d
etai
ls o
n av
aila
ble
type
s.
Reg
iste
rsX
ST r
ecog
nize
s fl
ip-f
lops
wit
h th
e fo
llow
ing
cont
rol s
igna
ls:
•A
sync
hron
ous
Set/
Cle
ar
•Sy
nchr
onou
s Se
t/C
lear
•C
lock
Ena
ble
Log
File
The
XST
log
file
rep
orts
the
type
and
siz
e of
rec
ogni
zed
flip
-flo
ps d
urin
g th
e M
acro
R
ecog
niti
on s
tep.
PA
CK
AG
ET
YP
E
num
eric
_std
unsi
gned
std
_log
ic_a
rith
unsi
gned
std
_log
ic_u
nsig
ned
std
_log
ic_v
ecto
r
PA
CK
AG
ET
YP
E
num
eric
_std
sign
ed
std
_log
ic_a
rith
sign
ed
std
_log
ic_s
igne
dst
d_l
ogic
_vec
tor
...
Synthesizing Unit <flop>.
Related source file is ff_1.vhd.
Found 1-bit register for signal <q>.
Summary:
inferred
1 D-type flip-flop(s).
Unit <flop> synthesized.
...
==============================
HDL Synthesis Report
Macro Statistics
# Registers
:1
1-bit
register
:1
==============================
...
40
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Use
r G
uid
e1-
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255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR Rel
ated
Con
stra
ints
Rel
ated
con
stra
ints
are
IOB
,RE
GIS
TE
R_D
UPL
ICA
TIO
N,
EQ
UIV
AL
EN
T_R
EG
IST
ER
_RE
MO
VA
L, R
EG
IST
ER
_BA
LA
NC
ING
.
Flip
-flo
p w
ith P
ositi
ve-E
dge
Clo
ckT
he fo
llow
ing
figu
re s
how
s a
flip
-flo
p w
ith
posi
tive
-ed
ge c
lock
.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
flip
-flo
p w
ith
posi
tive
ed
ge c
lock
.
VH
DL
Cod
e
Follo
win
g is
the
equi
vale
nt V
HD
L c
ode
sam
ple
for
the
flip
-flo
p w
ith
a po
siti
ve-e
dge
clo
ck.
library ieee;
use ieee.std_logic_1164.all;
entity flop is
port(C, D
: in std_logic;
Q: out std_logic
);
end flop;
architecture archi of flop is
begin
process (C)
begin
if (C’event and C=’1’) then
Q <= D;
end if;
end process;
end archi;
Whe
n us
ing
VH
DL
, for
a p
osit
ive-
edge
clo
ck in
stea
d of
usi
ng
if (C’event and C=’1’) then
you
can
also
use
if (rising_edge(C)) then
IO P
ins
Des
crip
tio
n
DD
ata
Inpu
t
CP
osit
ive
Ed
ge C
lock
QD
ata
Out
put
Q
X371
5
DFD
C
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m41
1-
800-
255-
7778
Reg
iste
rsR
Ver
ilog
Cod
e
Follo
win
g is
the
equi
vale
nt V
erilo
g co
de
sam
ple
for
the
flip
-flo
p w
ith
a p
osit
ive-
edge
cl
ock. module flop (C, D, Q);
input C, D;
output Q;
reg Q;
always @(posedge C)
begin
Q = D;
end
endmodule
Flip
-flo
p w
ith N
egat
ive-
Edg
e C
lock
and
Asy
nchr
onou
s C
lear
The
follo
win
g fi
gure
sho
ws
a fl
ip-f
lop
wit
h ne
gati
ve-e
dge
clo
ck a
nd a
sync
hron
ous
clea
r.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
flip
-flo
p w
ith
nega
tive
-ed
ge c
lock
and
as
ynch
rono
us c
lear
.
IO P
ins
Des
crip
tio
n
DD
ata
Inpu
t
CN
egat
ive-
Edg
e C
lock
CLR
Asy
nchr
onou
s C
lear
(act
ive
Hig
h)
QD
ata
Out
put
Q
X38
47
D CLR
C
FD
C_1
42
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7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
VH
DL
Cod
e
Follo
win
g is
the
equi
vale
nt V
HD
L c
ode
for
a fl
ip-f
lop
wit
h a
nega
tive
-ed
ge c
lock
and
as
ynch
rono
us c
lear
.
library ieee;
use ieee.std_logic_1164.all;
entity flop is
port(C, D, CLR: in std_logic;
Q: out std_logic
);
end flop;
architecture archi of flop is
begin
process (C, CLR)
begin
if (CLR = ’1’)then
Q <= ’0’;
elsif (C’event and C=’0’)then
Q <= D;
end if;
end process;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
equi
vale
nt V
erilo
g co
de
for
a fl
ip-f
lop
wit
h a
nega
tive
-ed
ge c
lock
and
as
ynch
rono
us c
lear
.
module flop (C, D, CLR, Q);
input C, D, CLR;
output Q;
reg Q;
always @(negedge C or posedge CLR)
begin
if (CLR)
Q = 1’b0;
else Q = D;
end
endmodule
Flip
-flo
p w
ith P
ositi
ve-E
dge
Clo
ck a
nd S
ynch
rono
us S
etT
he fo
llow
ing
figu
re s
how
s a
flip
-flo
p w
ith
posi
tive
-ed
ge c
lock
and
syn
chro
nou
s se
t.
Q
X3722
DF
DS
CS
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m43
1-
800-
255-
7778
Reg
iste
rsR
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
flip
-flo
p w
ith
posi
tive
-ed
ge c
lock
and
sy
nchr
onou
s se
t.
VH
DL
Cod
e
Follo
win
g is
the
equi
vale
nt V
HD
L c
ode
for
the
flip
-flo
p w
ith
a po
siti
ve-e
dge
clo
ck a
nd
sync
hron
ous
set.
library ieee;
use ieee.std_logic_1164.all;
entity flop is
port(C, D, S
: in std_logic;
Q: out std_logic);
end flop;
architecture archi of flop is
begin
process (C)
begin
if (C’event and C=’1’) then
if (S=’1’) then
Q <= ’1’;
else
Q <= D;
end if;
end if;
end process;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
equi
vale
nt V
erilo
g co
de
for
the
flip
-flo
p w
ith
a po
siti
ve-e
dge
clo
ck a
nd
sync
hron
ous
set.
module flop (C, D, S, Q);
input C, D, S;
output Q;
reg Q;
always @(posedge C)
begin
if (S)
Q = 1’b1;
else Q = D;
end
endmodule
IO P
ins
Des
crip
tio
n
DD
ata
Inpu
t
CP
osit
ive-
Ed
ge C
lock
SSy
nchr
onou
s Se
t (ac
tive
Hig
h)
QD
ata
Out
put
44
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w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR Flip
-flo
p w
ith P
ositi
ve-E
dge
Clo
ck a
nd C
lock
Ena
ble
The
follo
win
g fi
gure
sho
ws
a fl
ip-f
lop
wit
h po
siti
ve-e
dge
clo
ck a
nd c
lock
ena
ble.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a fl
ip-f
lop
wit
h po
siti
ve-e
dge
clo
ck a
nd c
lock
en
able
.
VH
DL
Cod
e
Follo
win
g is
the
equi
vale
nt V
HD
L c
ode
for
the
flip
-flo
p w
ith
a po
siti
ve-e
dge
clo
ck a
nd
cloc
k en
able
.
library ieee;
use ieee.std_logic_1164.all;
entity flop is
port(C, D, CE
: in std_logic;
Q: out std_logic
);
end flop;
architecture archi of flop is
begin
process (C)
begin
if (C’event and C=’1’) then
if (CE=’1’) then
Q <= D;
end if;
end if;
end process;
end archi;
IO P
ins
Des
crip
tio
n
DD
ata
Inpu
t
CP
osit
ive-
Ed
ge C
lock
CE
Clo
ck E
nabl
e (a
ctiv
e H
igh)
QD
ata
Out
put
Q
C
FDE
X83
61
D CE
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m45
1-
800-
255-
7778
Reg
iste
rsR
Ver
ilog
Cod
e
Follo
win
g is
the
equi
vale
nt V
erilo
g co
de
for
the
flip
-flo
p w
ith
a po
siti
ve-e
dge
clo
ck a
nd
cloc
k en
able
.
module flop (C, D, CE, Q);
input C, D, CE;
output Q;
reg Q;
always @(posedge C)
begin
if (CE)
Q = D;
end
endmodule
4-bi
t Reg
iste
r w
ith P
ositi
ve-E
dge
Clo
ck, A
sync
hron
ous
Set
and
Clo
ck
Ena
ble
The
follo
win
g fi
gure
sho
ws
a 4-
bit r
egis
ter w
ith
posi
tive
-ed
ge c
lock
, asy
nchr
onou
s se
t and
cl
ock
enab
le.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
4-bi
t reg
iste
r w
ith
posi
tive
-ed
ge c
lock
, as
ynch
rono
us s
et a
nd c
lock
ena
ble.
IO P
ins
Des
crip
tio
n
D[3
:0]
Dat
a In
put
CP
osit
ive-
Ed
ge C
lock
PR
EA
sync
hron
ous
Set (
acti
ve H
igh)
CE
Clo
ck E
nabl
e (a
ctiv
e H
igh)
Q[3
:0]
Dat
a O
utpu
t
X3721
FD
PE
CCE
QDP
RE
46
ww
w.x
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x.co
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ST
Use
r G
uid
e1-
800-
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7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
VH
DL
Cod
e
Follo
win
g is
the
equi
vale
nt V
HD
L c
ode
for
a 4-
bit r
egis
ter
wit
h a
posi
tive
-ed
ge c
lock
, as
ynch
rono
us s
et a
nd c
lock
ena
ble.
library ieee;
use ieee.std_logic_1164.all;
entity flop is
port(C, CE, PRE
: in std_logic;
D: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (3 downto 0)
);
end flop;
architecture archi of flop is
begin
process (C, PRE)
begin
if (PRE=’1’) then
Q <= "1111";
elsif (C’event and C=’1’)then
if (CE=’1’) then
Q <= D;
end if;
end if;
end process;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
equi
vale
nt V
erilo
g co
de
for
a 4-
bit r
egis
ter
wit
h a
posi
tive
-ed
ge c
lock
, as
ynch
rono
us s
et a
nd c
lock
ena
ble.
module flop (C, D, CE, PRE, Q);
input C, CE, PRE;
input [3:0] D;
output [3:0] Q;
reg [3:0] Q;
always @(posedge C or posedge PRE)
begin
if (PRE)
Q = 4’b1111;
else if (CE)
Q = D;
end
endmodule
Latc
hes
XST
can
rec
ogni
ze la
tche
s w
ith
the
asyn
chro
nous
set
/cl
ear
cont
rol s
igna
ls.
Lat
ches
can
be
des
crib
ed u
sing
:
•P
roce
ss (V
HD
L) a
nd a
lway
s bl
ock
(Ver
ilog)
.
•C
oncu
rren
t sta
te a
ssig
nmen
t.
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m47
1-
800-
255-
7778
Reg
iste
rsR
Log
File The
XST
log
file
rep
orts
the
type
and
siz
e of
rec
ogni
zed
latc
hes
dur
ing
the
Mac
ro
Rec
ogni
tion
ste
p.
Rel
ated
Con
stra
ints
A r
elat
ed c
onst
rain
t is
IOB
.
Latc
h w
ith P
ositi
ve G
ate
The
follo
win
g fi
gure
sho
ws
a la
tch
wit
h a
posi
tive
gat
e.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
latc
h w
ith
a po
siti
ve g
ate.
...
Synthesizing Unit <latch>.
Related source file is latch_1.vhd.
WARNING:Xst:737 - Found 1-bit latch for signal <q>.
Summary:
inferred
1 Latch(s).
Unit <latch> synthesized.
==============================
HDL Synthesis Report
Macro Statistics
#Latches
: 1
1-bit
latch
: 1
==============================
...
IO P
ins
Des
crip
tio
n
DD
ata
Inpu
t
GP
osit
ive
Gat
e
QD
ata
Out
put
Q
X374
0
DLD
G
48
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
VH
DL
Cod
e
Follo
win
g is
the
equi
vale
nt V
HD
L c
ode
for
a la
tch
wit
h a
posi
tive
gat
e.
library ieee;
use ieee.std_logic_1164.all;
entity latch is
port(G, D
: in std_logic;
Q: out std_logic
);
end latch;
architecture archi of latch is
begin
process (G, D)
begin
if (G=’1’) then
Q <= D;
end if;
end process;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
equi
vale
nt V
erilo
g co
de
for
a la
tch
wit
h a
posi
tive
gat
e.
module latch (G, D, Q);
input G, D;
output Q;
reg Q;
always @(G or D)
begin
if (G)
Q = D;
end
endmodule
Latc
h w
ith P
ositi
ve G
ate
and
Asy
nchr
onou
s C
lear
The
follo
win
g fi
gure
sho
ws
a la
tch
wit
h a
pos
itiv
e ga
te a
nd a
n as
ynch
rono
us
clea
r.
Q
X40
70
DLD
C
G CLR
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m49
1-
800-
255-
7778
Reg
iste
rsR
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
latc
h w
ith
a po
siti
ve g
ate
and
an
asyn
chro
nous
cle
ar.
VH
DL
Cod
e
Follo
win
g is
the
equi
vale
nt V
HD
L c
ode
for
a la
tch
wit
h a
posi
tive
gat
e an
d a
n as
ynch
rono
us c
lear
.
library ieee;
use ieee.std_logic_1164.all;
entity latch is
port(G, D, CLR
: in std_logic;
Q: out std_logic
);
end latch;
architecture archi of latch is
begin
process (CLR, D, G)
begin
if (CLR=’1’) then
Q <= ’0’;
elsif (G=’1’) then
Q <= D;
end if;
end process;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
equi
vale
nt V
erilo
g co
de
for
a la
tch
wit
h a
posi
tive
gat
e an
d a
n as
ynch
rono
us c
lear
.
module latch (G, D, CLR, Q);
input G, D, CLR;
output Q;
reg Q;
always @(G or D or CLR)
begin
if (CLR)
Q = 1’b0;
else if (G)
Q = D;
end
endmodule
IO P
ins
Des
crip
tio
n
DD
ata
Inpu
t
GP
osit
ive
Gat
e
CLR
Asy
nchr
onou
s C
lear
(act
ive
Hig
h)
QD
ata
Out
put
50
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR 4-bi
t Lat
ch w
ith In
vert
ed G
ate
and
Asy
nchr
onou
s P
rese
tT
he fo
llow
ing
figu
re s
how
s a
4-bi
t lat
ch w
ith
an in
vert
ed g
ate
and
an
asyn
chro
nous
pre
set.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
latc
h w
ith
an in
vert
ed g
ate
and
an
asyn
chro
nous
pre
set.
VH
DL
Cod
e
Follo
win
g is
the
equi
vale
nt V
HD
L c
ode
for
a 4-
bit l
atch
wit
h an
inve
rted
gat
e an
d a
n as
ynch
rono
us p
rese
t.
library ieee;
use ieee.std_logic_1164.all;
entity latch is
port(D
: in std_logic_vector(3 downto 0);
G, PRE
: in std_logic;
Q: out std_logic_vector(3 downto 0));
end latch;
architecture archi of latch is
begin
process (PRE, G)
begin
if (PRE=’1’) then
Q <= "1111";
elsif (G=’0’) then
Q <= D;
end if;
end process;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
equi
vale
nt V
erilo
g co
de
for
a 4-
bit l
atch
wit
h an
inve
rted
gat
e an
d a
n as
ynch
rono
us p
rese
t.
IO P
ins
Des
crip
tio
n
D[3
:0]
Dat
a In
put
GIn
vert
ed G
ate
PR
EA
sync
hron
ous
Pres
et (a
ctiv
e H
igh)
Q[3
:0]
Dat
a O
utpu
t
Q
G
LD
P_1
PR
E
X8376
D
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m51
1-
800-
255-
7778
Tris
tate
sR
module latch (G, D, PRE, Q);
input G, PRE;
input [3:0] D;
output [3:0] Q;
reg [3:0] Q;
always @(G or D or PRE)
begin
if (PRE)
Q = 4’b1111;
else if (~G)
Q = D;
end
endmodule
Tris
tate
sTr
ista
te e
lem
ents
can
be
des
crib
ed u
sing
the
follo
win
g:
•C
ombi
nato
rial
pro
cess
(VH
DL
) and
alw
ays
bloc
k (V
erilo
g).
•C
oncu
rren
t ass
ignm
ent.
Log
File
The
XST
log
repo
rts
the
type
and
siz
e of
reco
gniz
ed tr
ista
tes
dur
ing
the
Mac
ro R
ecog
niti
on
step
.
Rel
ated
Con
stra
ints
The
re a
re n
o re
late
d c
onst
rain
ts a
vaila
ble.
...
Synthesizing Unit <three_st>.
Related source file is tristates_1.vhd.
Found 1-bit tristate buffer for signal <o>.
Summary:inferred
1 Tristate(s).
Unit <three_st> synthesized.
=============================
HDL Synthesis Report
Macro Statistics
# Tristates
:1
1-bit
tristate
buffer
:1
=============================
...
52
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w.x
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x.co
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ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR Des
crip
tion
Usi
ng C
ombi
nato
rial P
roce
ss a
nd A
lway
s B
lock
The
follo
win
g fi
gure
sho
ws
a tr
ista
te e
lem
ent u
sing
a c
ombi
nato
rial
pro
cess
and
alw
ays
bloc
k.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
tris
tate
ele
men
t usi
ng a
com
bina
tori
al
proc
ess
and
alw
ays
bloc
k.
VH
DL
Cod
e
Follo
win
g is
VH
DL
cod
e fo
r a
tris
tate
ele
men
t usi
ng a
com
bina
tori
al p
roce
ss a
nd a
lway
s bl
ock. library ieee;
use ieee.std_logic_1164.all;
entity three_st is
port(T
: in std_logic;
I: in std_logic;
O: out std_logic
);
end three_st;
architecture archi of three_st is
begin
process (I, T)
begin
if (T=’0’) then
O <= I;
else O <= ’Z’;
end if;
end process;
end archi;
IO P
ins
Des
crip
tio
n
ID
ata
Inpu
t
TO
utpu
t Ena
ble
(act
ive
Low
)
OD
ata
Out
put
X954
3
T IO
BUFT
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m53
1-
800-
255-
7778
Tris
tate
sR
Ver
ilog
Cod
e
Follo
win
g is
Ver
ilog
cod
e fo
r a
tris
tate
ele
men
t usi
ng a
com
bina
tori
al p
roce
ss a
nd a
lway
s bl
ock. module three_st (T, I, O);
input T, I;
output O;
reg O;
always @(T or I)
begin
if (~T)
O = I;
else O = 1’bZ;
end
endmodule
Des
crip
tion
Usi
ng C
oncu
rren
t Ass
ignm
ent
In th
e fo
llow
ing
two
exam
ples
, not
e th
at c
ompa
ring
to 0
inst
ead
of 1
infe
rs a
BU
FT
prim
itiv
e in
stea
d o
f a B
UFE
mac
ro. (
The
BU
FE m
acro
has
an
inve
rter
on
the
E pi
n.)
VH
DL
Cod
e
Follo
win
g is
VH
DL
cod
e fo
r a
tris
tate
ele
men
t usi
ng a
con
curr
ent a
ssig
nmen
t.
library ieee;
use ieee.std_logic_1164.all;
entity three_st is
port(T
: in std_logic;
I: in std_logic;
O: out std_logic
);
end three_st;
architecture archi of three_st is
begin
O <= I when (T=’0’) else ’Z’;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r a
tris
tate
ele
men
t usi
ng a
con
curr
ent a
ssig
nmen
t.
module three_st (T, I, O);
input T, I;
output O;
assign O = (~T)
? I: 1’bZ;
endmodule
54
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w.x
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r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Co
un
ters
XST
is a
ble
to r
ecog
nize
cou
nter
s w
ith
the
follo
win
g co
ntro
l sig
nals
.
•A
sync
hron
ous
Set/
Cle
ar
•Sy
nchr
onou
s Se
t/C
lear
•A
sync
hron
ous/
Sync
hron
ous
Loa
d (s
igna
l and
/or
cons
tant
)
•C
lock
Ena
ble
•M
odes
(Up,
Dow
n, U
p/D
own)
•M
ixtu
re o
f all
of th
e ab
ove
HD
L co
din
g st
yles
for
the
follo
win
g co
ntro
l sig
nals
are
equ
ival
ent t
o th
e on
es d
escr
ibed
in
“Reg
iste
rs”
in th
is c
hapt
er.
•C
lock
•A
sync
hron
ous
Set/
Cle
ar
•Sy
nchr
onou
s Se
t/C
lear
•C
lock
Ena
ble
Mor
eove
r, X
ST s
uppo
rts
both
uns
igne
d an
d s
igne
d c
ount
ers.
Log
File
The
XST
log
file
rep
orts
the
type
and
siz
e of
rec
ogni
zed
cou
nter
s d
urin
g th
e M
acro
R
ecog
niti
on s
tep.
No
te:
Dur
ing
synt
hesi
s, X
ST
dec
ompo
ses
Cou
nter
s on
Add
ers
and
Reg
iste
rs if
they
do
not c
onta
in
sync
hron
ous
load
sig
nals
. Thi
s is
don
e to
cre
ate
addi
tiona
l opp
ortu
nitie
s fo
r tim
ing
optim
izat
ion.
B
ecau
se o
f thi
s, c
ount
ers
repo
rted
dur
ing
the
Mac
ro R
ecog
nitio
n st
ep a
nd in
the
over
all s
tatis
tics
of
reco
gniz
ed m
acro
s m
ay n
ot a
ppea
r in
the
final
rep
ort.
Add
ers/
regi
ster
s ar
e re
port
ed in
stea
d.
Rel
ated
Con
stra
ints
The
re a
re n
o re
late
d c
onst
rain
ts a
vaila
ble.
...
Synthesizing Unit <counter>.
Related source file is counters_1.vhd.
Found 4-bit up counter for signal <tmp>.
Summary:
inferred
1 Counter(s).
Unit <counter> synthesized.
==============================
HDL Synthesis Report
Macro Statistics
#Counters
:1
4-bit
up
counter
:1
==============================
...
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m55
1-
800-
255-
7778
Co
un
ters
R
4-bi
t Uns
igne
d U
p C
ount
er w
ith A
sync
hron
ous
Cle
arT
he fo
llow
ing
tabl
e sh
ows
pin
def
init
ions
for
a 4-
bit u
nsig
ned
up
coun
ter
wit
h an
as
ynch
rono
us c
lear
.
VH
DL
Cod
e
Follo
win
g is
VH
DL
cod
e fo
r a
4-bi
t uns
igne
d u
p co
unte
r w
ith
an a
sync
hron
ous
clea
r.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR
: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin process (C, CLR)
begin
if (CLR=’1’) then
tmp <= "0000";
elsif (C’event and C=’1’) then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r a
4-bi
t uns
igne
d u
p co
unte
r w
ith
asyn
chro
nou
s cl
ear.
module counter (C, CLR, Q);
input C, CLR;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 4’b0000;
else tmp = tmp + 1’b1;
end
assign Q = tmp;
endmodule
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
CLR
Asy
nchr
onou
s C
lear
(act
ive
Hig
h)
Q[3
:0]
Dat
a O
utpu
t
56
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR 4-bi
t Uns
igne
d D
own
Cou
nter
with
Syn
chro
nous
Set
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
4-bi
t uns
igne
d d
own
coun
ter
wit
h a
sync
hron
ous
set.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-bi
t uns
igne
d d
own
coun
ter
wit
h a
sync
hron
ous
set.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, S
: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C)
begin
if (C’event and C=’1’) then
if (S=’1’) then
tmp <= "1111";
else tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
SSy
nchr
onou
s Se
t (ac
tive
Hig
h)
Q[3
:0]
Dat
a O
utpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m57
1-
800-
255-
7778
Co
un
ters
R
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r a
4-bi
t uns
igne
d d
own
coun
ter
wit
h sy
nchr
onou
s se
t.
module counter (C, S, Q);
input C, S;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C)
begin
if (S)
tmp = 4’b1111;
else
tmp = tmp - 1’b1;
end
assign Q = tmp;
endmodule
4-bi
t Uns
igne
d U
p C
ount
er w
ith A
sync
hron
ous
Load
from
Prim
ary
Inpu
tT
he fo
llow
ing
tabl
e sh
ows
pin
def
init
ions
for
a 4-
bit u
nsig
ned
up
coun
ter
wit
h an
as
ynch
rono
us lo
ad fr
om th
e pr
imar
y in
put.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-bi
t uns
igne
d u
p co
unte
r w
ith
an a
sync
hron
ous
load
fr
om th
e pr
imar
y in
put.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, ALOAD
: in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end counter;
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
AL
OA
DA
sync
hron
ous
Loa
d (a
ctiv
e H
igh)
D[3
:0]
Dat
a In
put
Q[3
:0]
Dat
a O
utpu
t
58
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w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, ALOAD, D)
begin
if (ALOAD=’1’) then
tmp <= D;
elsif (C’event and C=’1’) then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r a
4-bi
t uns
igne
d u
p co
unte
r w
ith
an a
sync
hron
ous
load
fr
om th
e pr
imar
y in
put.
module counter (C, ALOAD, D, Q);
input C, ALOAD;
input [3:0] D;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge ALOAD)
begin
if (ALOAD)
tmp = D;
else tmp = tmp + 1’b1;
end
assign Q = tmp;
endmodule
4-bi
t Uns
igne
d U
p C
ount
er w
ith S
ynch
rono
us L
oad
with
a C
onst
ant
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
4-bi
t uns
igne
d u
p co
unte
r w
ith
a sy
nchr
onou
s lo
ad w
ith
a co
nsta
nt.
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
SLO
AD
Sync
hron
ous
Loa
d (a
ctiv
e H
igh)
Q[3
:0]
Dat
a O
utpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m59
1-
800-
255-
7778
Co
un
ters
R
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-bi
t uns
igne
d u
p c
ount
er w
ith
a sy
nchr
onou
s lo
ad w
ith
a co
nsta
nt.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, SLOAD
: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C)
begin
if (C’event and C=’1’) then
if (SLOAD=’1’) then
tmp <= "1010";
else tmp <= tmp + 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Ver
ilog
cod
e fo
r a 4
-bit
uns
igne
d u
p co
unte
r with
a s
ynch
rono
us lo
ad w
ith
a co
nsta
nt.
module counter (C, SLOAD, Q);
input C, SLOAD;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C)
begin
if (SLOAD)
tmp = 4’b1010;
else tmp = tmp + 1’b1;
end
assign Q = tmp;
endmodule
60
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ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR 4-bi
t Uns
igne
d U
p C
ount
er w
ith A
sync
hron
ous
Cle
ar a
nd C
lock
Ena
ble
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
4-bi
t uns
igne
d u
p co
unte
r w
ith
an
asyn
chro
nous
cle
ar a
nd a
clo
ck e
nabl
e.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-bi
t uns
igne
d u
p co
unte
r w
ith
an a
sync
hron
ous
clea
r an
d a
clo
ck e
nabl
e.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR, CE
: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR=’1’) then
tmp <= "0000";
elsif (C’event and C=’1’) then
if (CE=’1’) then
tmp <= tmp + 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
CLR
Asy
nchr
onou
s C
lear
(act
ive
Hig
h)
CE
Clo
ck E
nabl
e
Q[3
:0]
Dat
a O
utpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m61
1-
800-
255-
7778
Co
un
ters
R
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r a
4-bi
t uns
igne
d u
p co
unte
r w
ith
an a
sync
hron
ous
clea
r an
d a
clo
ck e
nabl
e.
module counter (C, CLR, CE, Q);
input C, CLR, CE;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 4’b0000;
else
if (CE)
tmp = tmp + 1’b1;
end
assign Q = tmp;
endmodule
4-bi
t Uns
igne
d U
p/D
own
coun
ter
with
Asy
nchr
onou
s C
lear
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
4-bi
t uns
igne
d u
p/d
own
coun
ter
wit
h an
as
ynch
rono
us c
lear
.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-bi
t uns
igne
d u
p/d
own
cou
nter
wit
h an
asy
nchr
onou
s cl
ear. library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR, UP_DOWN
: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end counter;
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
CLR
Asy
nchr
onou
s C
lear
(act
ive
Hig
h)
UP
_DO
WN
up/
dow
n co
unt m
ode
sele
ctor
Q[3
:0]
Dat
a O
utpu
t
62
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ST
Use
r G
uid
e1-
800-
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7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR=’1’) then
tmp <= "0000";
elsif (C’event and C=’1’) then
if (UP_DOWN=’1’) then
tmp <= tmp + 1;
else tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Ver
ilog
cod
e fo
r a 4
-bit
uns
igne
d u
p/d
own
coun
ter w
ith
an a
sync
hron
ous
clea
r. module counter (C, CLR, UP_DOWN, Q);
input C, CLR, UP_DOWN;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 4’b0000;
else if (UP_DOWN)
tmp = tmp + 1’b1;
else tmp = tmp - 1’b1;
end
assign Q = tmp;
endmodule
4-bi
t Sig
ned
Up
Cou
nter
with
Asy
nchr
onou
s R
eset
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
4-bi
t sig
ned
up
cou
nter
wit
h an
as
ynch
rono
us r
eset
.
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
CLR
Asy
nchr
onou
s C
lear
(act
ive
Hig
h)
Q[3
:0]
Dat
a O
utpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m63
1-
800-
255-
7778
Co
un
ters
R
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-bi
t sig
ned
up
cou
nter
wit
h an
asy
nchr
onou
s re
set.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity counter is
port(C, CLR
: in std_logic;
Q: out std_logic_vector(3 downto 0)
);
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR = ’1’) then
tmp <= "0000";
elsif (C’event and C=’1’) then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r a
4-bi
t sig
ned
up
coun
ter
wit
h an
asy
nchr
onou
s re
set.
module counter (C, CLR, Q);
input C, CLR;
output signed [3:0] Q;
reg signed [3:0] tmp;
always @ (posedge C or posedge CLR)
begin
if (CLR)
tmp <= "0000";
else tmp <= tmp + 1’b1;
end
assign Q = tmp;
endmodule
64
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w.x
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x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR 4-bi
t Sig
ned
Up
Cou
nter
with
Asy
nchr
onou
s R
eset
and
Mod
ulo
Max
imum
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
4-bi
t sig
ned
up
cou
nter
wit
h an
as
ynch
rono
us r
eset
and
a m
odul
o m
axim
um.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-bi
t sig
ned
up
coun
ter
wit
h an
asy
nchr
onou
s re
set a
nd
a m
axim
um u
sing
the
VH
DL
mod
func
tion
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
generic (MAX
: integer
:= 4);
port(
C, CLR
: in std_logic;
Q: out integer range 0 to MAX-1
);
end counter;
architecture archi of counter is
signal cnt
: integer range 0 to MAX-1;
begin
process (C, CLR)
begin
if (CLR=’1’) then
cnt <= 0;
elsif (rising_edge(C)) then
cnt <= (cnt + 1) mod (MAX * MAX)
;end if;
end process;
Q <= cnt;
end archi;
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
CLR
Asy
nchr
onou
s C
lear
(act
ive
Hig
h)
Q[7
:0]
Dat
a O
utpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m65
1-
800-
255-
7778
Acc
um
ula
tors
R
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r a 4
-bit
sig
ned
up
cou
nter
wit
h an
asy
nchr
onou
s re
set a
nd
a m
odul
o m
axim
um.
module counter (C, CLR, Q);
parameter
MAX_SQRT = 4,
MAX = (MAX_SQRT*MAX_SQRT);
input C, CLR;
output [MAX_SQRT-1:0] Q;
reg [MAX_SQRT-1:0] cnt;
always @ (posedge C or posedge CLR)
begin
if (CLR)
cnt <= 0;
else cnt <= (cnt + 1)
%MAX;
end
assign Q = cnt;
endmodule
Rel
ated
Con
stra
ints
The
re a
re n
o re
late
d c
onst
rain
ts a
vaila
ble.
Acc
um
ula
tors
An
accu
mu
lato
r d
iffe
rs fr
om a
cou
nter
in th
e na
ture
of t
he o
pera
nds
of th
e ad
d a
nd
subt
ract
ope
rati
on:
•In
a c
ount
er, t
he d
esti
nati
on a
nd fi
rst o
pera
nd is
a s
igna
l or
vari
able
and
the
othe
r op
eran
d is
a c
onst
ant e
qual
to 1
: A <
= A
+ 1
.
•In
an
accu
mu
lato
r, th
e d
esti
nati
on a
nd fi
rst o
pera
nd is
a s
igna
l or
vari
able
, and
the
seco
nd o
pera
nd is
eit
her:
♦a
sign
al o
r va
riab
le: A
<=
A +
B.
♦a
cons
tant
not
equ
al to
1: A
<=
A +
Con
stan
t.
An
infe
rred
acc
um
ula
tor
can
be u
p, d
own
or u
pdow
n. F
or a
n u
pdow
n ac
cum
ulat
or, t
he
accu
mul
ated
dat
a m
ay d
iffe
r be
twee
n th
e u
p a
nd d
own
mod
e:
...
if updown = ’1’ then
a <= a + b;
else
a <= a - c;
...
XST
can
infe
r an
acc
umu
lato
r w
ith
the
sam
e se
t of c
ontr
ol s
igna
ls a
vaila
ble
for
coun
ters
. (R
efer
to “
Cou
nter
s” in
this
cha
pter
for
mor
e d
etai
ls.)
66
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Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR Lo
g F
ileT
he X
ST lo
g fi
le r
epor
ts th
e ty
pe a
nd s
ize
of r
ecog
nize
d a
ccum
ulat
ors
duri
ng th
e M
acro
R
ecog
niti
on s
tep.
No
te:
Dur
ing
synt
hesi
s, X
ST
dec
ompo
ses
Acc
umul
ator
s on
Add
ers
and
Reg
iste
rs if
they
do
not
cont
ain
sync
hron
ous
load
sig
nals
. Thi
s is
don
e to
cre
ate
addi
tiona
l opp
ortu
nitie
s fo
r tim
ing
optim
izat
ion.
Bec
ause
of t
his,
Acc
umul
ator
s re
port
ed d
urin
g th
e M
acro
Rec
ogni
tion
step
and
in th
e ov
eral
l sta
tistic
s of
rec
ogni
zed
mac
ros
may
not
app
ear
in th
e fin
al r
epor
t. A
dder
s/re
gist
ers
are
repo
rted
inst
ead.
Rel
ated
Con
stra
ints
The
re a
re n
o re
late
d c
onst
rain
ts a
vaila
ble.
4-bi
t Uns
igne
d U
p A
ccum
ulat
or w
ith A
sync
hron
ous
Cle
arT
he fo
llow
ing
tabl
e sh
ows
pin
def
init
ions
for
a 4-
bit u
nsig
ned
up
accu
mul
ator
wit
h an
as
ynch
rono
us c
lear
.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-bi
t uns
igne
d u
p ac
cum
ula
tor
wit
h an
asy
nchr
onou
s cl
ear. library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
...
Synthesizing Unit <accum>.
Related source file is accumulators_1.vhd.
Found 4-bit up accumulator for signal <tmp>.
Summary:
inferred
1 Accumulator(s).
Unit <accum> synthesized.
==============================
HDL Synthesis Report
Macro Statistics
# Accumulators
:1
4-bit
up
accumulator
:1
==============================
...
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
CLR
Asy
nchr
onou
s C
lear
(act
ive
Hig
h)
D[3
:0]
Dat
a In
put
Q[3
:0]
Dat
a O
utpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m67
1-
800-
255-
7778
Acc
um
ula
tors
R
entity accum is
port(C, CLR
: in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end accum;
architecture archi of accum is
signal tmp
: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR=’1’) then
tmp <= "0000";
elsif (C’event and C=’1’) then
tmp <= tmp + D;
end if;
end process;
Q <= tmp;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r a
4-bi
t uns
igne
d u
p a
ccum
ulat
or w
ith
an a
sync
hron
ous
clea
r. module accum (C, CLR, D, Q);
input C, CLR;
input [3:0] D;
output [3:0] Q;
reg [3:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 4’b0000;
else tmp = tmp + D;
end
assign Q = tmp;
endmodule
Rel
ated
Con
stra
ints
The
re a
re n
o re
late
d c
onst
rain
ts a
vaila
ble.
68
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w.x
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ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Sh
ift
Reg
iste
rsIn
gen
eral
, a s
hift
regi
ster
is c
hara
cter
ized
by
the
follo
win
g co
ntro
l and
dat
a si
gnal
s, w
hich
ar
e fu
lly r
ecog
nize
d b
y X
ST.
•cl
ock
•se
rial
inpu
t
•as
ynch
rono
us s
et/r
eset
•sy
nchr
onou
s se
t/re
set
•sy
nchr
onou
s/as
ynch
rono
us p
aral
lel l
oad
•cl
ock
enab
le
•se
rial
or
para
llel o
utpu
t. T
he s
hift
reg
iste
r ou
tput
mod
e m
ay b
e:
♦se
rial
: onl
y th
e co
nten
ts o
f the
last
flip
-flo
p ar
e ac
cess
ed b
y th
e re
st o
f the
cir
cuit
♦pa
ralle
l: th
e co
nten
ts o
f one
or
seve
ral f
lip-f
lops
, oth
er th
an th
e la
st o
ne, a
re
acce
ssed
•sh
ift m
odes
: lef
t, ri
ght,
etc.
The
re a
re d
iffe
rent
way
s to
des
crib
e sh
ift r
egis
ters
. For
exa
mpl
e, in
VH
DL
you
can
use:
•co
ncat
enat
ion
oper
ator
shreg <= shreg (6 downto 0) & SI;
•"f
or lo
op"
cons
truc
t
for i in 0 to 6 loop
shreg(i+1) <= shreg(i);
end loop;
shreg(0) <= SI;
•pr
edef
ined
shi
ft o
pera
tors
; for
exa
mpl
e, s
ll, s
rl
Con
sult
the
VH
DL
/V
erilo
g la
ngua
ge r
efer
ence
man
uals
for
mor
e in
form
atio
n.
FPG
As:
Bef
ore
wri
ting
shi
ft r
egis
ter
beha
vior
it is
impo
rtan
t to
reca
ll th
at V
irte
x™/
-E/
-II/
-II P
ro/
-II P
ro X
, and
Spa
rtan
™-I
I/-I
IE/
-3 h
ave
spec
ific
har
dw
are
reso
urc
es to
impl
emen
t shi
ft
regi
ster
s: S
RL
16 fo
r V
irte
x™ /
-E/
-II/
-II P
ro/
-II P
ro X
and
Spa
rtan
™-I
I/-I
IE/
-3 a
nd
SRL
C16
for
Vir
tex™
-II/
-II P
ro/-
II P
ro X
and
Spa
rtan
-3™
. Bot
h ar
e av
aila
ble
wit
h or
w
itho
ut a
clo
ck e
nabl
e. T
he fo
llow
ing
figu
re s
how
s th
e pi
n la
yout
of S
RL
16E.
X84
23
SR
L16E
A2
A3
A1
A0
CLKCE
DQ
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m69
1-
800-
255-
7778
Sh
ift
Reg
iste
rsR
The
follo
win
g fi
gure
sho
ws
the
pin
layo
ut o
f SR
LC
16.
No
te:
Syn
chro
nous
and
asy
nchr
onou
s co
ntro
l sig
nals
are
not
ava
ilabl
e in
the
SLR
C16
x pr
imiti
ves.
SRL
16 a
nd S
RL
C16
sup
port
onl
y L
EFT
shi
ft o
pera
tion
for
a lim
ited
nu
mbe
r of
IO s
igna
ls.
•cl
ock
•cl
ock
enab
le
•se
rial
dat
a in
•se
rial
dat
a ou
t
Thi
s m
eans
that
if y
our s
hift
regi
ster
doe
s hav
e, fo
r ins
tanc
e, a
syn
chro
nous
par
alle
l loa
d, n
o SR
L16
is im
plem
ente
d. X
ST u
ses
spec
ific
inte
rnal
pro
cess
ing
whi
ch a
llow
s it
to p
rod
uce
th
e be
st fi
nal r
esul
ts.
The
XST
log
file
rep
orts
rec
ogni
zed
shi
ft r
egis
ters
whe
n it
can
be
impl
emen
ted
usi
ng
SRL
16.
Log
File
The
XST
log
file
rep
orts
the
type
and
siz
e of
rec
ogni
zed
shi
ft r
egis
ters
du
ring
the
Mac
ro
Rec
ogni
tion
ste
p.
X94
97
CLK
Q Q15
D A0
A1
A2
A3
SR
LC16
...
Synthesizing Unit <shift>.
Related source file is shift_registers_1.vhd.
Found 8-bit shift register for signal <tmp<7>>.
Summary:
inferred
1 Shift register(s).
Unit <shift> synthesized.
==============================
HDL Synthesis Report
Macro Statistics
# ShiftRegisters
:1
8-bit
shift
register
:1
==============================
...
70
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pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR Rel
ated
Con
stra
ints
A r
elat
ed c
onst
rain
t is
SHR
EG
_EX
TR
AC
T.
8-bi
t Shi
ft-Le
ft R
egis
ter
with
Pos
itive
-Edg
e C
lock
, Ser
ial I
n, a
nd S
eria
l Out
No
te:
For
this
exa
mpl
e, X
ST
infe
rs a
n S
RL1
6.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-
edge
clo
ck, a
ser
ial i
n, a
nd a
ser
ial o
ut.
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
SISe
rial
In
SOSe
rial
Ou
tpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m71
1-
800-
255-
7778
Sh
ift
Reg
iste
rsR
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck, a
se
rial
in a
nd a
ser
ial o
ut.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI
: in std_logic;
SO
: out std_logic
);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C’event and C=’1’) then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Ver
ilog
cod
e fo
r an
8-bi
t shi
ft-l
eft r
egis
ter w
ith
a po
siti
ve-e
dge
clo
ck, s
eria
l in
, and
ser
ial o
ut.
module shift (C, SI, SO);
input C,SI;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
tmp = tmp << 1;
tmp[0] = SI;
end
assign SO = tmp[7];
endmodule
72
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR 8-bi
t Shi
ft-Le
ft R
egis
ter
with
Neg
ativ
e-E
dge
Clo
ck, C
lock
Ena
ble,
Ser
ial
In, a
nd S
eria
l Out
No
te:
For
this
exa
mpl
e, X
ST
infe
rs a
n S
RL1
6E_1
.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a ne
gati
ve-
edge
clo
ck, a
clo
ck e
nabl
e, a
ser
ial i
n, a
nd a
ser
ial o
ut.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a ne
gati
ve-e
dge
clo
ck, a
cl
ock
enab
le, a
ser
ial i
n, a
nd a
ser
ial o
ut.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI, CE
: in std_logic;
SO
: out std_logic
);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C’event and C=’0’) then
if (CE=’1’) then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end if;
end process;
SO <= tmp(7);
end archi;
IO P
ins
Des
crip
tio
n
CN
egat
ive-
Edg
e C
lock
SISe
rial
In
CE
Clo
ck E
nabl
e (a
ctiv
e H
igh)
SOSe
rial
Ou
tpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m73
1-
800-
255-
7778
Sh
ift
Reg
iste
rsR
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a ne
gati
ve-e
dge
clo
ck, a
cl
ock
enab
le, a
ser
ial i
n, a
nd a
ser
ial o
ut.
module shift (C, CE, SI, SO);
input C, SI, CE;
output SO;
reg [7:0] tmp;
always @(negedge C)
begin
if (CE)
begin
tmp = tmp << 1;
tmp[0] = SI;
end
end
assign SO = tmp[7];
endmodule
8-bi
t Shi
ft-Le
ft R
egis
ter
with
Pos
itive
-Edg
e C
lock
, Asy
nchr
onou
s C
lear
, S
eria
l In,
and
Ser
ial O
utN
ote
:B
ecau
se th
is e
xam
ple
incl
udes
an
asyn
chro
nous
cle
ar, X
ST
doe
s n
ot
infe
r an
SR
L16.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-
edge
clo
ck, a
n as
ynch
rono
us c
lear
, a s
eria
l in,
and
a s
eria
l ou
t.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck, a
n as
ynch
rono
us
clea
r, a
seri
al in
, and
a s
eria
l out
.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI, CLR
: in std_logic;
SO
: out std_logic
);
end shift;
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
SISe
rial
In
CLR
Asy
nchr
onou
s C
lear
(act
ive
Hig
h)
SOSe
rial
Ou
tpu
t
74
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w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C, CLR)
begin
if (CLR=’1’) then
tmp <= (others => ’0’);
elsif (C’event and C=’1’) then
tmp <= tmp(6 downto 0) & SI;
end if;
end process;
SO <= tmp(7);
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck,
asyn
chro
nous
cle
ar, s
eria
l in,
and
ser
ial o
ut.
module shift (C, CLR, SI, SO);
input C, SI, CLR;
output SO;
reg [7:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp = 8’b00000000;
else begin
tmp = {tmp[6:0], SI};
end
end
assign SO = tmp[7];
endmodule
8-bi
t Shi
ft-Le
ft R
egis
ter w
ith P
ositi
ve-E
dge
Clo
ck, S
ynch
rono
us S
et, S
eria
l In
, and
Ser
ial O
utN
ote
:F
or th
is e
xam
ple,
XS
T d
oes
no
t in
fer
an S
RL1
6.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-
edge
clo
ck, a
syn
chro
nous
set
, a s
eria
l in,
and
a s
eria
l out
.
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
SISe
rial
In
SSy
nchr
onou
s Se
t (ac
tive
Hig
h)
SOSe
rial
Ou
tpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m75
1-
800-
255-
7778
Sh
ift
Reg
iste
rsR
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck, a
sy
nchr
onou
s se
t, a
seri
al in
, and
a s
eria
l ou
t.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI, S
: in std_logic;
SO
: out std_logic
);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C, S)
begin
if (C’event and C=’1’) then
if (S=’1’) then
tmp <= (others => ’1’);
else tmp <= tmp(6 downto 0) & SI;
end if;
end if;
end process;
SO <= tmp(7);
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck, a
sy
nchr
onou
s se
t, a
seri
al in
, and
a s
eria
l ou
t.
module shift (C, S, SI, SO);
input C, SI, S;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
if (S)
tmp = 8’b11111111;
else begin
tmp = {tmp[6:0], SI};
end
end
assign SO = tmp[7];
endmodule
76
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mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR 8-bi
t Shi
ft-Le
ft R
egis
ter
with
Pos
itive
-Edg
e C
lock
, Ser
ial I
n, a
nd P
aral
lel
Out
No
te:
For
this
exa
mpl
e, X
ST
doe
s n
ot
infe
r S
RL1
6.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-
edge
clo
ck, a
ser
ial i
n, a
nd a
par
alle
l out
.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck, a
se
rial
in, a
nd a
par
alle
l out
.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI
: in std_logic;
PO
: out std_logic_vector(7 downto 0)
);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C’event and C=’1’) then
tmp <= tmp(6 downto 0)& SI;
end if;
end process;
PO <= tmp;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck, a
se
rial
in, a
nd a
par
alle
l out
.
module shift (C, SI, PO);
input C, SI;
output [7:0] PO;
reg [7:0] tmp;
always @(posedge C)
begin
tmp = {tmp[6:0], SI};
end
assign PO = tmp;
endmodule
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
SISe
rial
In
PO
[7:0
]P
aral
lel O
utpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m77
1-
800-
255-
7778
Sh
ift
Reg
iste
rsR
8-bi
t Shi
ft-Le
ft R
egis
ter
with
Pos
itive
-Edg
e C
lock
, Asy
nchr
onou
s P
aral
lel
Load
, Ser
ial I
n, a
nd S
eria
l Out
No
te:
For
this
exa
mpl
e, X
ST
doe
s n
ot
infe
r S
RL1
6.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-
edge
clo
ck, a
n as
ynch
rono
us p
aral
lel l
oad
, a s
eria
l in,
and
a s
eria
l out
.
VH
DL
Cod
e
Follo
win
g is
VH
DL
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a p
osit
ive-
edge
clo
ck, a
n as
ynch
rono
us p
aral
lel l
oad
, a s
eria
l in,
and
a s
eria
l ou
t.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI, ALOAD
: in std_logic;
D: in std_logic_vector(7 downto 0);
SO
: out std_logic
);
end shift;
architecture archi of shift is
signal tmp
: std_logic_vector(7 downto 0);
begin
process (C, ALOAD, D)
begin
if (ALOAD=’1’) then
tmp <= D;
elsif (C’event and C=’1’) then
tmp <= tmp(6 downto 0) & SI;
end if;
end process;
SO <= tmp(7);
end archi;
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
SISe
rial
In
AL
OA
DA
sync
hron
ous
Para
llel L
oad
(act
ive
Hig
h)
D[7
:0]
Dat
a In
put
SOSe
rial
Ou
tpu
t
78
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck, a
n as
ynch
rono
us p
aral
lel l
oad
, a s
eria
l in,
and
a s
eria
l ou
t.
module shift (C, ALOAD, SI, D, SO);
input C, SI, ALOAD;
input [7:0] D;
output SO;
reg [7:0] tmp;
always @(posedge C or posedge ALOAD)
begin
if (ALOAD)
tmp = D;
else begin
tmp = {tmp[6:0], SI};
end
end
assign SO = tmp[7];
endmodule
8-bi
t Shi
ft-Le
ft R
egis
ter
with
Pos
itive
-Edg
e C
lock
, Syn
chro
nous
Par
alle
l Lo
ad, S
eria
l In,
and
Ser
ial O
utN
ote
:F
or th
is e
xam
ple,
XS
T d
oes
no
t in
fer
SR
L16.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-
edge
clo
ck, a
syn
chro
nous
par
alle
l loa
d, a
ser
ial i
n an
d a
ser
ial o
ut.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck,
sync
hron
ous
para
llel l
oad,
ser
ial i
n, a
nd s
eria
l out
.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(C, SI, SLOAD
: in std_logic;
D: in std_logic_vector(7 downto 0);
SO
: out std_logic
);
end shift;
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
SISe
rial
In
SLO
AD
Sync
hron
ous
Par
alle
l Loa
d (a
ctiv
e H
igh)
D[7
:0]
Dat
a In
put
SOSe
rial
Ou
tpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m79
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Sh
ift
Reg
iste
rsR
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C’event and C=’1’) then
if (SLOAD=’1’) then
tmp <= D;
else tmp <= tmp(6 downto 0) & SI;
end if;
end if;
end process;
SO <= tmp(7);
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r an
8-b
it s
hift
-lef
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck, a
sy
nchr
onou
s pa
ralle
l loa
d, a
ser
ial i
n, a
nd a
ser
ial o
ut.
module shift (C, SLOAD, SI, D, SO);
input C, SI, SLOAD;
input [7:0] D;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
if (SLOAD)
tmp = D;
else begin
tmp = {tmp[6:0], SI};
end
end
assign SO = tmp[7];
endmodule
8-bi
t Shi
ft-Le
ft/S
hift-
Rig
ht R
egis
ter
with
Pos
itive
-Edg
e C
lock
, Ser
ial I
n,
and
Par
alle
l Out
No
te:
For
this
exa
mpl
e, X
ST
doe
s n
ot
infe
r an
SR
L16.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r an
8-b
it s
hift
-lef
t/sh
ift-
righ
t reg
iste
r w
ith
a po
siti
ve-e
dge
clo
ck, a
ser
ial i
n, a
nd a
ser
ial o
ut.
IO P
ins
Des
crip
tio
n
CP
osit
ive-
Ed
ge C
lock
SISe
rial
In
LE
FT_R
IGH
TL
eft/
righ
t shi
ft m
ode
sele
ctor
PO
[7:0
]P
aral
lel O
utpu
t
80
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L C
od
ing
Tec
hn
iqu
esR
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r an
8-b
it s
hift
-lef
t/sh
ift-
righ
t reg
iste
r w
ith
a po
siti
ve-e
dge
cl
ock,
a s
eria
l in,
and
a s
eria
l out
.
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(
C, SI, LEFT_RIGHT
: in std_logic;
PO
: out std_logic_vector(7 downto 0)
);
end shift;
architecture archi of shift is
signal tmp
: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C’event and C=’1’) then
if (LEFT_RIGHT=’0’) then
tmp <= tmp(6 downto 0) & SI;
else tmp <= SI & tmp(7 downto 1);
end if;
end if;
end process;
PO <= tmp;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Ver
ilog
cod
e fo
r an
8-b
it s
hift
-lef
t/sh
ift-
righ
t reg
iste
r w
ith
a po
siti
ve-e
dge
cl
ock,
a s
eria
l in,
and
a s
eria
l out
.
module shift (C, SI, LEFT_RIGHT, PO);
input C, SI, LEFT_RIGHT;
output PO;
reg [7:0] tmp;
always @(posedge C)
begin
if (LEFT_RIGHT == 1’b0)
begin
tmp = {tmp[6:0], SI};
end
else begin
tmp = {SI, tmp[6:0]};
end
end
assign PO = tmp;
endmodule
XS
T U
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ide
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Dyn
amic
Sh
ift
Reg
iste
rR
Dyn
amic
Sh
ift
Reg
iste
rX
ST c
an in
fer D
ynam
ic s
hift
regi
ster
s. O
nce
a d
ynam
ic s
hift
regi
ster
has
bee
n id
enti
fied
, its
ch
arac
teri
stic
s ar
e ha
nded
to th
e X
ST m
acro
gen
erat
or fo
r op
tim
al im
plem
enta
tion
usi
ng
SRL
16x
prim
itiv
es a
vaila
ble
in S
part
an™
-II/
-IIE
/-3
, Vir
tex™
/-II
/-I
I Pro
/-I
I Pro
X o
r SR
LC
16x
in V
irte
x™-I
I/-I
I Pro
/-I
I Pro
X a
nd S
part
an-3
™.
16-b
it D
ynam
ic S
hift
Reg
iste
r w
ith P
ositi
ve-E
dge
Clo
ck, S
eria
l In
and
Ser
ial O
utT
he fo
llow
ing
tabl
e sh
ows
pin
def
init
ions
for
a d
ynam
ic re
gist
er. T
he re
gist
er c
an b
e ei
ther
se
rial
or
para
llel;
be le
ft o
r ri
ght;
have
a s
ynch
rono
us o
r as
ynch
rono
us
clea
r; a
nd h
ave
a d
epth
up
to 1
6 b
its.
LOG
File
The
rec
ogni
tion
of d
ynam
ic s
hift
reg
iste
r ha
ppen
s in
the
Ad
vanc
ed H
DL
Syn
thes
is s
tep.
T
his
is w
hy n
o m
essa
ge a
bou
t a d
ynam
ic s
hift
reg
iste
r is
dis
play
ed d
uri
ng H
DL
syn
thes
is
step
. Ins
tead
an
n-bi
t reg
iste
r an
d a
mu
ltip
lexe
r is
infe
rred
:
IO P
ins
Des
crip
tio
n
Clk
Pos
itiv
e-E
dge
Clo
ck
SISe
rial
In
AC
lrA
sync
hron
ous
Cle
ar (o
ptio
nal)
SClr
Sync
hron
ous
Cle
ar (o
pti
onal
)
SLoa
dSy
nchr
onou
s Pa
ralle
l Loa
d (o
ptio
nal)
Dat
aP
aral
lel D
ata
Inpu
t Por
t (op
tion
al)
Clk
En
Clo
ck E
nabl
e (o
ptio
nal)
Lef
tRig
htD
irec
tion
sel
ecti
on (o
ptio
nal)
Seri
alIn
Rig
htSe
rial
Inpu
t Rig
ht fo
r B
idir
ecti
onal
Shi
ft R
egis
ter
(opt
iona
l)
PSO
[x:0
]Se
rial
or
Para
llel O
utpu
t
...
Synthesizing Unit <dynamic_srl>.
Related source file is dynamic_srl.vhd.
Found 1-bit 16-to-1 multiplexer for signal <Q>.
Found 16-bit register for signal <data>.
Summary:
inferred
16 D-type flip-flop(s).
inferred
1 Multiplexer(s).
Unit <dynamic_srl> synthesized.
...
82
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Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
The
not
ific
atio
n th
at X
ST r
ecog
nize
d a
dyn
amic
shi
ft r
egis
ter
is d
isp
laye
d o
nly
in th
e "M
acro
Sta
tist
ics"
sec
tion
of t
he "
Fina
l Rep
ort"
.
Rel
ated
Con
stra
ints
A r
elat
ed c
onst
rain
t is
SHR
EG
_EX
TR
AC
T.
VH
DL
Cod
eFo
llow
ing
is th
e V
HD
L c
ode
for
a 16
-bit
dyn
amic
shi
ft r
egis
ter.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity shiftregluts is
port(CLK
: in std_logic;
DATA
: in std_logic;
CE
: in std_logic;
A: in std_logic_vector(3 downto 0);
Q: out std_logic
);
end shiftregluts;
architecture rtl of shiftregluts is
constant DEPTH_WIDTH
: integer:= 16;
type SRL_ARRAY is array (0 to DEPTH_WIDTH-1) of std_logic;
-- The type SRL_ARRAY can be array
-- (0 to DEPTH_WIDTH-1) of
-- std_logic_vector(BUS_WIDTH downto 0)
-- or array (DEPTH_WIDTH-1 downto 0) of
-- std_logic_vector(BUS_WIDTH downto 0)
-- (the subtype is forward (see below))
signal SRL_SIG
: SRL_ARRAY;
begin
PROC_SRL16
: process (CLK)
begin
if (CLK’event and CLK = ’1’) then
if (CE = ’1’) then
SRL_SIG <= DATA & SRL_SIG(0 to DEPTH_WIDTH-2);
end if;
end if;
end process;
Q <= SRL_SIG(conv_integer(A));
end rtl;
... Macro Statistics
# Shift Registers
:1
#16-bit dynamic shift register
:1
...
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Mu
ltip
lexe
rsR
Ver
ilog
Cod
eFo
llow
ing
is th
e V
erilo
g co
de
for
a 16
-bit
dyn
amic
shi
ft r
egis
ter.
module dynamic_srl (Q,CE,CLK,D,A);
input CLK, D, CE;
input [3:0] A;
output Q;
reg [15:0] data;
assign Q = data[A];
always @(posedge CLK)
begin
if (CE == 1’b1)
{data[15:0]} <= {data[14:0], D};
end
endmodule
Mu
ltip
lexe
rsX
ST s
upp
orts
dif
fere
nt d
escr
ipti
on s
tyle
s fo
r m
ulti
plex
ers
(MU
Xs)
, suc
h as
If-T
hen-
Else
or
Cas
e. W
hen
wri
ting
MU
Xs,
you
mu
st p
ay p
arti
cula
r at
tent
ion
in o
rder
to a
void
com
mon
tr
aps.
For
exa
mpl
e, if
you
des
crib
e a
MU
X u
sing
a C
ase
stat
emen
t, an
d y
ou d
o no
t spe
cify
al
l val
ues
of th
e se
lect
or, y
ou m
ay g
et la
tche
s in
stea
d o
f a m
ult
iple
xer.
Wri
ting
MU
Xs
you
can
also
use
“d
on't
care
s” to
des
crib
e se
lect
or v
alue
s.
Dur
ing
the
Mac
ro In
fere
nce
step
, XST
mak
es a
dec
isio
n to
infe
r or
not
infe
r th
e M
UX
s. F
or
exam
ple,
if th
e M
UX
has
sev
eral
inpu
ts th
at a
re th
e sa
me,
then
XST
can
dec
ide
not t
o in
fer
it. I
f you
do
wan
t to
infe
r the
MU
X, y
ou c
an fo
rce
XST
by
usi
ng th
e d
esig
n co
nstr
aint
cal
led
M
UX
_EX
TR
AC
T.
If y
ou u
se V
erilo
g, th
en y
ou m
ust b
e aw
are
that
Ver
ilog
Cas
e st
atem
ents
can
be
full
or n
ot
full,
and
they
can
als
o be
par
alle
l or
not p
aral
lel.
A C
ase
stat
emen
t is:
•FU
LL
if a
ll po
ssib
le b
ranc
hes
are
spec
ifie
d.
•PA
RA
LLE
L if
it d
oes
not c
onta
in b
ranc
hes
that
can
be
exec
uted
sim
ulta
neou
sly.
84
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pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
The
follo
win
g ta
bles
giv
es th
ree
exam
ples
of C
ase
stat
emen
ts w
ith
dif
fere
nt c
hara
cter
isti
cs.
Fu
ll an
d P
aral
lel C
ase
module full
(sel, i1, i2, i3, i4, o1);
input [1:0] sel;
input [1:0] i1, i2, i3, i4;
output [1:0] o1;
reg [1:0] o1;
always @(sel or i1 or i2 or i3 or i4)
begin
case (sel)
2’b00:
o1 = i1;
2’b01:
o1 = i2;
2’b10:
o1 = i3;
2’b11:
o1 = i4;
endcase
end
endmodule
No
t F
ull
bu
t P
aral
lel
module notfull
(sel, i1, i2, i3, o1);
input [1:0] sel;
input [1:0] i1, i2, i3;
output [1:0] o1;
reg [1:0] o1;
always @(sel or i1 or i2 or i3)
begin
case (sel)
2’b00:
o1 = i1;
2’b01:
o1 = i2;
2’b10:
o1 = i3;
endcase
end
endmodule
XS
T U
ser
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ide
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Mu
ltip
lexe
rsR
XST
aut
omat
ical
ly d
eter
min
es th
e ch
arac
teri
stic
s of
the
Cas
e st
atem
ents
and
gen
erat
es
logi
c us
ing
mul
tipl
exer
s, p
rior
ity
enco
ders
and
latc
hes
that
bes
t im
plem
ent t
he e
xact
be
havi
or o
f the
Cas
e st
atem
ent.
Thi
s ch
arac
teri
zati
on o
f the
Cas
e st
atem
ents
can
be
guid
ed o
r m
odif
ied
by
usin
g th
e C
ase
Impl
emen
tati
on S
tyle
par
amet
er. P
leas
e re
fer
to th
e C
hap
ter
5, “
Des
ign
Con
stra
ints
” fo
r m
ore
det
ails
. Acc
epte
d v
alu
es fo
r th
is p
aram
eter
are
none
,ful
l,pa
ralle
l and
full-
para
llel.
•If
non
e is
use
d (t
he d
efau
lt),
XST
impl
emen
ts th
e ex
act b
ehav
ior
of th
e C
ase
stat
emen
ts.
•If
full
is u
sed,
XST
con
sid
ers
that
Cas
e st
atem
ents
are
com
plet
e an
d a
void
s la
tch
crea
tion
.
•If
par
alle
l is
use
d, X
ST c
onsi
der
s th
at th
e br
anch
es c
anno
t occ
ur in
par
alle
l and
doe
s no
t use
a p
rior
ity
enco
der
.
•If
full-
para
llel i
s us
ed, X
ST c
onsi
der
s th
at C
ase
stat
emen
ts a
re c
ompl
ete
and
that
the
bran
ches
can
not o
ccur
in p
aral
lel,
ther
efor
e sa
ving
latc
hes
and
prio
rity
enc
oder
s.
The
follo
win
g ta
ble
ind
icat
es th
e re
sour
ces
used
to s
ynth
esiz
e th
e th
ree
exam
ples
abo
ve
usin
g th
e fo
ur C
ase
Impl
emen
tati
on S
tyle
s. T
he te
rm "
reso
urce
s" m
eans
the
func
tion
alit
y.
For
exam
ple,
if y
ou c
ode
the
Cas
e st
atem
ent n
eith
er fu
ll no
r pa
ralle
l wit
h C
ase
Impl
emen
tati
on S
tyle
set
to n
one,
from
the
func
tion
alit
y po
int o
f vie
w, X
ST im
plem
ents
a
prio
rity
enc
oder
+ la
tch.
But
, it d
oes
not i
nevi
tabl
y m
ean
that
XST
infe
rs th
e pr
iori
ty
enco
der
dur
ing
the
Mac
ro R
ecog
niti
on s
tep.
Nei
ther
Fu
ll n
or
Par
alle
l
module notfull_notparallel
(sel1, sel2, i1, i2, o1);
input [1:0] sel1, sel2;
input [1:0] i1, i2;
output [1:0] o1;
reg [1:0] o1;
always @(sel1 or sel2)
begin
case (2’b00)
sel1:
o1 = i1;
sel2:
o1 = i2;
endcase
end
endmodule
Par
amet
er V
alu
eC
ase
Imp
lem
enta
tio
n
Fu
llN
ot
Fu
llN
eith
er F
ull
no
r P
aral
lel
none
MU
XLa
tch
Prio
rity
Enc
oder
+ L
atch
par
alle
lM
UX
Latc
hL
atch
full
MU
XM
UX
Prio
rity
Enc
oder
full-
para
llel
MU
XM
UX
MU
X
86
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pter
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L C
od
ing
Tec
hn
iqu
esR
No
te:
Spe
cify
ing
full,
par
alle
l or
full-
para
llel m
ay r
esul
t in
an im
plem
enta
tion
with
a b
ehav
ior
that
m
ay d
iffer
from
the
beha
vior
of t
he in
itial
mod
el.
Log
File
The
XST
log
file
rep
orts
the
type
and
siz
e of
rec
ogni
zed
MU
Xs
du
ring
the
Mac
ro
Rec
ogni
tion
ste
p.
Rel
ated
Con
stra
ints
Rel
ated
con
stra
ints
are
MU
X_E
XT
RA
CT
and
MU
X_S
TY
LE
.
4-to
-1 1
-bit
MU
X u
sing
IF S
tate
men
tT
he fo
llow
ing
tabl
e sh
ows
pin
def
init
ions
for
a 4-
to-1
1-b
it M
UX
usi
ng a
n If
sta
tem
ent.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-to
-1 1
-bit
MU
X u
sing
an
If s
tate
men
t.
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port ( a, b, c, d
: in std_logic;
s: in std_logic_vector (1 downto 0);
o: out std_logic
);
end mux;
...
Synthesizing Unit <mux>.
Related source file is multiplexers_1.vhd.
Found 1-bit 4-to-1 multiplexer for signal <o>.
Summary:
inferred
1 Multiplexer(s).
Unit <mux> synthesized.
=============================
HDL Synthesis Report
Macro Statistics
# Multiplexers
:1
1-bit 4-to-1 multiplexer
:1
==============================
...
IO P
ins
Des
crip
tio
n
a, b
, c, d
Dat
a In
puts
s[1:
0]M
UX
sel
ecto
r
oD
ata
Out
put
XS
T U
ser
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ide
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7778
Mu
ltip
lexe
rsR
architecture archi of mux is
begin
process (a, b, c, d, s)
begin
if (s = "00") then
o <= a;
elsif (s = "01") then
o <= b;
elsif (s = "10") then
o <= c;
else o <= d;
end if;
end process;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r a
4-to
-1 1
-bit
MU
X u
sing
an
If s
tate
men
t.
module mux (a, b, c, d, s, o);
input a,b,c,d;
input [1:0] s;
output o;
reg o;
always @(a or b or c or d or s)
begin
if (s == 2’b00)
o = a;
else if (s == 2’b01)
o = b;
else if (s == 2’b10)
o = c;
else o = d;
end
endmodule
4-to
-1 M
UX
Usi
ng C
AS
E S
tate
men
tT
he fo
llow
ing
tabl
e sh
ows
pin
def
init
ions
for
a 4-
to-1
1-b
it M
UX
usi
ng a
Cas
e st
atem
ent.
IO P
ins
Des
crip
tio
n
a, b
, c, d
Dat
a In
puts
s[1:
0]M
UX
sel
ecto
r
oD
ata
Out
put
88
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-to
-1 1
-bit
MU
X u
sing
a C
ase
stat
emen
t.
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port ( a, b, c, d
: in std_logic;
s: in std_logic_vector (1 downto 0);
o: out std_logic
);
end mux;
architecture archi of mux is
begin
process (a, b, c, d, s)
begin
case s is
when "00" => o <= a;
when "01" => o <= b;
when "10" => o <= c;
when others => o <= d;
end case;
end process;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
Cod
e fo
r a
4-to
-1 1
-bit
MU
X u
sing
a C
ase
stat
emen
t.
module mux (a, b, c, d, s, o);
input a, b, c, d;
input [1:0] s;
output o;
reg o;
always @(a or b or c or d or s)
begin
case (s)
2’b00
: o = a;
2’b01
: o = b;
2’b10
: o = c;
default
: o = d;
endcase
end
endmodule
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m89
1-
800-
255-
7778
Mu
ltip
lexe
rsR
4-to
-1 M
UX
Usi
ng T
rista
te B
uffe
rsT
he fo
llow
ing
tabl
e sh
ows
pin
def
init
ions
for
a 4-
to-1
1-b
it M
UX
usi
ng tr
ista
te b
uffe
rs.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
4-to
-1 1
-bit
MU
X u
sing
tris
tate
buf
fers
.
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port (a, b, c, d
: in std_logic;
s: in std_logic_vector (3 downto 0);
o: out std_logic
);
end mux;
architecture archi of mux is
begin
o <= a when (s(0)=’0’) else ’Z’;
o <= b when (s(1)=’0’) else ’Z’;
o <= c when (s(2)=’0’) else ’Z’;
o <= d when (s(3)=’0’) else ’Z’;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
Cod
e fo
r a
4-to
-1 1
-bit
MU
X u
sing
tris
tate
bu
ffer
s.
module mux (a, b, c, d, s, o);
input a, b, c, d;
input [3:0] s;
output o;
assign o = s[3]
? a
:1’bz;
assign o = s[2]
? b
:1’bz;
assign o = s[1]
? c
:1’bz;
assign o = s[0]
? d
:1’bz;
endmodule
No
4-to
-1 M
UX
T
he fo
llow
ing
exam
ple
doe
s no
t gen
erat
e a
4-to
-1 1
-bit
MU
X, b
ut a
3-t
o-1
MU
X w
ith
1-bi
t la
tch.
The
rea
son
is th
at n
ot a
ll se
lect
or v
alu
es w
ere
des
crib
ed in
the
If s
tate
men
t. It
is
supp
osed
that
for t
he s
=11
case
, "O
" kee
ps it
s ol
d v
alue
, and
ther
efor
e a
mem
ory
elem
ent i
s ne
eded
.
IO P
ins
Des
crip
tio
n
a, b
, c, d
Dat
a In
puts
s[3:
0]M
UX
Sel
ecto
r
oD
ata
Out
put
90
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
3-to
-1 1
-bit
MU
X w
ith
a 1-
bit l
atch
.
VH
DL
Cod
e
Follo
win
g is
the
VH
DL
cod
e fo
r a
3-to
-1 1
-bit
MU
X w
ith
a 1-
bit l
atch
.
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port ( a, b, c, d
: in std_logic;
s: in std_logic_vector (1 downto 0);
o: out std_logic
);
end mux;
architecture archi of mux is
begin
process (a, b, c, d, s)
begin
if (s = "00") then
o <= a;
elsif (s = "01") then
o <= b;
elsif (s = "10") then
o <= c;
end if;
end process;
end archi;
Ver
ilog
Cod
e
Follo
win
g is
the
Veri
log
cod
e fo
r a
3-to
-1 1
-bit
MU
X w
ith
a 1-
bit l
atch
.
module mux (a, b, c, d, s, o);
input a, b, c, d;
input [1:0] s;
output
o;
reg
o;
always @(a or b or c or d or s)
begin
if
(s == 2’b00)
o = a;
else if
(s == 2’b01)
o = b;
else if
(s == 2’b10)
o = c;
end
endmodule
IO P
ins
Des
crip
tio
n
a, b
, c, d
Dat
a In
puts
s[1:
0]Se
lect
or
oD
ata
Out
put
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m91
1-
800-
255-
7778
Dec
od
ers
R
Dec
od
ers
A d
ecod
er is
a m
ult
iple
xer w
hose
inpu
ts a
re a
ll co
nsta
nt w
ith
dis
tinc
t one
-hot
(or o
ne-c
old
) co
ded
val
ues.
Ple
ase
refe
r to
“M
ult
iple
xers
” in
this
cha
pter
for
mor
e de
tails
. Thi
s se
ctio
n sh
ows
two
exam
ples
of 1
-of-
8 d
ecod
ers
usin
g O
ne-H
ot a
nd O
ne-C
old
cod
ed v
alu
es.
Log
File
The
XST
log
file
rep
orts
the
type
and
siz
e of
rec
ogni
zed
dec
oder
s d
uri
ng th
e M
acro
R
ecog
niti
on s
tep.
The
follo
win
g ta
ble
show
s pi
n d
efin
itio
ns fo
r a
1-of
-8 d
ecod
er.
Rel
ated
Con
stra
ints
A r
elat
ed c
onst
rain
t is
DE
CO
DE
R_E
XT
RA
CT.
VH
DL
(One
-Hot
)Fo
llow
ing
is th
e V
HD
L c
ode
for
a 1-
of-8
dec
oder
.
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port ( sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0)
);
end dec;
Synthesizing Unit <dec>.
Related source file is decoders_1.vhd.
Found 1-of-8 decoder for signal <res>.
Summary:
inferred
1 Decoder(s).
Unit <dec> synthesized.
==============================
HDL Synthesis Report
Macro Statistics
#Decoders
:1
1-of-8 decoder
:1
==============================
...
IO p
ins
Des
crip
tio
n
s[2:
0]Se
lect
or
res
Dat
a O
utpu
t
92
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
architecture archi of dec is
begin
res <= "00000001" when sel = "000" else
"00000010" when sel = "001" else
"00000100" when sel = "010" else
"00001000" when sel = "011" else
"00010000" when sel = "100" else
"00100000" when sel = "101" else
"01000000" when sel = "110" else
"10000000";
end archi;
Ver
ilog
(One
-Hot
)Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a 1-
of-8
dec
oder
.
module mux (sel, res);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res)
begin
case (sel)
3’b000
: res = 8’b00000001;
3’b001
: res = 8’b00000010;
3’b010
: res = 8’b00000100;
3’b011
: res = 8’b00001000;
3’b100
: res = 8’b00010000;
3’b101
: res = 8’b00100000;
3’b110
: res = 8’b01000000;
default
: res = 8’b10000000;
endcase
end
endmodule
VH
DL
(One
-Col
d)Fo
llow
ing
is th
e V
HD
L c
ode
for
a 1-
of-8
dec
oder
.
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port ( sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0)
);
end dec;
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m93
1-
800-
255-
7778
Dec
od
ers
R
architecture archi of dec is
begin
res <= "11111110" when sel = "000" else
"11111101" when sel = "001" else
"11111011" when sel = "010" else
"11110111" when sel = "011" else
"11101111" when sel = "100" else
"11011111" when sel = "101" else
"10111111" when sel = "110" else
"01111111";
end archi;
Ver
ilog
(One
-Col
d)Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a 1-
of-8
dec
oder
.
module mux (sel, res);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel)
begin
case (sel)
3’b000
: res = 8’b11111110;
3’b001
: res = 8’b11111101;
3’b010
: res = 8’b11111011;
3’b011
: res = 8’b11110111;
3’b100
: res = 8’b11101111;
3’b101
: res = 8’b11011111;
3’b110
: res = 8’b10111111;
default
: res = 8’b01111111;
endcase
end
endmodule
Dec
oder
s w
ith U
nsel
ecte
d O
utpu
tsIn
the
curr
ent v
ersi
on, X
ST d
oes
not i
nfer
dec
oder
s if
one
or
seve
ral o
f the
dec
oder
out
puts
ar
e no
t sel
ecte
d, e
xcep
t whe
n th
e un
use
d s
elec
tor
valu
es a
re c
onse
cuti
ve a
nd a
t the
end
of
the
cod
e sp
ace.
Fol
low
ing
is a
n ex
ampl
e:
IO p
ins
Des
crip
tio
n
s[2:
0]Se
lect
or
res
Dat
a O
utpu
t
94
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
VH
DL
(No
Dec
oder
Infe
renc
e)
For
the
follo
win
g V
HD
L c
ode,
XST
doe
s no
t inf
er a
dec
oder
.
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port ( sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0)
);
end dec;
architecture archi of dec is
begin
res <=
"00000001" when sel = "000" else -- unused decoder output
"XXXXXXXX" when sel = "001" else
"00000100" when sel = "010" else
"00001000" when sel = "011" else
"00010000" when sel = "100" else
"00100000" when sel = "101" else
"01000000" when sel = "110" else
"10000000";
end archi;
Ver
ilog
(No
Dec
oder
Infe
renc
e)
For
the
follo
win
g V
erilo
g co
de,
XST
doe
s no
t inf
er a
dec
oder
.
module mux (sel, res);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel)
begin
case (sel)
3’b000
: res = 8’b00000001; // unused decoder output
3’b001
: res = 8’bxxxxxxxx;
3’b010
: res = 8’b00000100;
3’b011
: res = 8’b00001000;
3’b100
: res = 8’b00010000;
3’b101
: res = 8’b00100000;
3’b110
: res = 8’b01000000;
default
: res = 8’b10000000;
endcase
end
endmodule
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m95
1-
800-
255-
7778
Dec
od
ers
R
VH
DL
Cod
e (D
ecod
er In
fere
nce)
The
follo
win
g V
HD
L c
ode
lead
s to
the
infe
renc
e of
a 1
-of-
8 d
ecod
er.
library ieee;
use ieee.std_logic_1164.all;
entity dec is
port ( sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0)
);
end dec;
architecture archi of dec is
begin
res <= "00000001" when sel = "000" else
"00000010" when sel = "001" else
"00000100" when sel = "010" else
"00001000" when sel = "011" else
"00010000" when sel = "100" else
"00100000" when sel = "101" else
-- 110 and 111 selector values are unused
"XXXXXXXX";
end archi;
Ver
ilog
Cod
e (D
ecod
er In
fere
nce)
The
follo
win
g Ve
rilo
g co
de
lead
s to
the
infe
renc
e of
a 1
-of-
8 d
ecod
er.
module mux (sel, res);
input [2:0] sel;
output [7:0] res;
reg [7:0] res;
always @(sel or res)
begin
case (sel)
3’b000
: res = 8’b00000001;
3’b001
: res = 8’b00000010;
3’b010
: res = 8’b00000100;
3’b011
: res = 8’b00001000;
3’b100
: res = 8’b00010000;
3’b101
: res = 8’b00100000;
// 110 and 111 selector values are unused
default
: res = 8’bxxxxxxxx;
endcase
end
endmodule
96
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Pri
ori
ty E
nco
der
sX
ST c
an r
ecog
nize
a p
rior
ity
enco
der
, but
in m
ost c
ases
XST
doe
s no
t inf
er it
. To
forc
e pr
iori
ty e
ncod
er in
fere
nce,
use
the
PR
IOR
ITY
_EX
TR
AC
T c
onst
rain
t wit
h th
e va
lue
forc
e.X
ilinx
® s
tron
gly
sugg
ests
that
you
use
this
con
stra
int o
n a
sign
al-b
y-si
gnal
bas
is;
othe
rwis
e, th
e co
nstr
aint
may
gui
de
you
tow
ard
s su
b-op
tim
al r
esul
ts.
Log
File
The
XST
log
file
repo
rts
the
type
and
siz
e of
reco
gniz
ed p
rior
ity
enco
der
s d
urin
g th
e M
acro
R
ecog
niti
on s
tep.
3-B
it 1-
of-9
Prio
rity
Enc
oder
No
te:
For
this
exa
mpl
e X
ST
may
infe
r a
prio
rity
enco
der.
You
mus
t use
the
PR
IOR
ITY
_EX
TR
AC
T
cons
trai
nt w
ith a
val
ue force
to fo
rce
its in
fere
nce.
Rel
ated
Con
stra
int
A r
elat
ed c
onst
rain
t is
PR
IOR
ITY
_EX
TR
AC
T.
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r a
3-bi
t 1-o
f-9
Prio
rity
Enc
oder
.
library ieee;
use ieee.std_logic_1164.all;
entity priority is
port (sel
: in std_logic_vector (7 downto 0);
code
:out std_logic_vector (2 downto 0)
);
end priority;
...
Synthesizing Unit <priority>.
Related source file is priority_encoders_1.vhd.
Found 3-bit 1-of-9 priority encoder for signal <code>.
Summary:
inferred
3 Priority encoder(s).
Unit <priority> synthesized.
==============================
HDL Synthesis Report
Macro Statistics
# PriorityEncoders
:1
3-bit
1-of-9
priority encoder
:1
==============================
...
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m97
1-
800-
255-
7778
Lo
gic
al S
hif
ters
R
architecture archi of priority is
begin
code <= "000" when sel(0) = ’1’ else
"001" when sel(1) = ’1’ else
"010" when sel(2) = ’1’ else
"011" when sel(3) = ’1’ else
"100" when sel(4) = ’1’ else
"101" when sel(5) = ’1’ else
"110" when sel(6) = ’1’ else
"111" when sel(7) = ’1’ else
"---";
end archi;
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r a
3-bi
t 1-o
f-9
Pri
orit
y E
ncod
er.
module priority (sel, code);
input [7:0] sel;
output [2:0] code;
reg [2:0] code;
always @(sel)
begin
if (sel[0]) code <= 3’b000;
else if (sel[1]) code <= 3’b001;
else if (sel[2]) code <= 3’b010;
else if (sel[3]) code <= 3’b011;
else if (sel[4]) code <= 3’b100;
else if (sel[5]) code <= 3’b101;
else if (sel[6]) code <= 3’b110;
else if (sel[7]) code <= 3’b111;
else
code <= 3’bxxx;
end
endmodule
Lo
gic
al S
hif
ters X
ilinx
® d
efin
es a
logi
cal s
hift
er a
s a
com
bina
tori
al c
ircu
it w
ith
2 in
puts
and
1 o
utpu
t:
•T
he fi
rst i
nput
is a
dat
a in
put t
hat i
s sh
ifte
d.
•T
he s
econ
d in
put i
s a
sele
ctor
who
se b
inar
y va
lue
def
ines
the
shif
t dis
tanc
e.
•T
he o
utpu
t is
the
resu
lt o
f the
shi
ft o
pera
tion
.
No
te:
All
ofth
ese
I/Os
are
man
dato
ry; o
ther
wis
e, X
ST
doe
s no
t inf
er a
logi
cal s
hifte
r.
Mor
eove
r, yo
u m
ust
adh
ere
to th
e fo
llow
ing
cond
itio
ns w
hen
wri
ting
you
r H
DL
cod
e:
•U
se o
nly
logi
cal,
arit
hmet
ic a
nd r
otat
e sh
ift o
pera
tion
s. S
hift
ope
rati
ons
that
fill
vaca
ted
pos
itio
ns w
ith
valu
es fr
om a
noth
er s
igna
l are
not
rec
ogni
zed
.
•Fo
r V
HD
L, y
ou c
an o
nly
use
pred
efin
ed s
hift
(sll,
srl
, rol
, etc
.) or
con
cate
nati
on
oper
atio
ns. P
leas
e re
fer
to th
e IE
EE
VH
DL
lang
uage
ref
eren
ce m
anu
al fo
r m
ore
info
rmat
ion
on p
red
efin
ed s
hift
ope
rati
ons.
•U
se o
nly
one
type
of s
hift
ope
rati
on.
•T
he n
val
ue in
the
shif
t ope
rati
on m
ust
be
incr
emen
ted
or
decr
emen
ted
only
by
1 fo
r ea
ch c
onse
quen
t bin
ary
valu
e of
the
sele
ctor
.
98
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
•T
he n
val
ue c
an b
e on
ly p
osit
ive.
•A
ll va
lues
of t
he s
elec
tor
mus
t be
pres
ente
d.
Log
File
The
XST
log
file
rep
orts
the
type
and
siz
e of
a r
ecog
nize
d lo
gica
l shi
fter
dur
ing
the
Mac
ro
Rec
ogni
tion
ste
p.
Rel
ated
Con
stra
ints
A r
elat
ed c
onst
rain
t is
SHIF
T_E
XT
RA
CT.
Exa
mpl
e 1 T
he fo
llow
ing
tabl
e sh
ows
pin
des
crip
tion
s fo
r a
logi
cal s
hift
er.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a lo
gica
l shi
fter
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
Synthesizing Unit <lshift>.
Related source file is Logical_Shifters_1.vhd.
Found 8-bit shifter logical left for signal <so>.
Summary:
inferred
1 Combinational logic shifter(s).
Unit <lshift> synthesized.
...
==============================
HDL Synthesis Report
Macro Statistics
#Logic shifters
:1
8-bit shifter logical left
:1
==============================
...
IO p
ins
Des
crip
tio
n
D[7
:0]
Dat
a In
put
SEL
Shif
t Dis
tanc
e Se
lect
or
SO[7
:0]
Dat
a O
utpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m99
1-
800-
255-
7778
Lo
gic
al S
hif
ters
R
entity lshift is
port(DI
: in unsigned(7 downto 0);
SEL
: in unsigned(1 downto 0);
SO
: out unsigned(7 downto 0)
);
end lshift;
architecture archi of lshift is
begin
with SEL select
SO <= DI when "00",
DI sll 1 when "01",
DI sll 2 when "10",
DI sll 3 when others;
end archi;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a lo
gica
l shi
fter
.
module lshift (DI, SEL, SO);
input
[7:0] DI;
input
[1:0] SEL;
output
[7:0] SO;
reg
[7:0] SO;
always @(DI or SEL)
begin
case (SEL)
2’b00
: SO <= DI;
2’b01
: SO <= DI << 1;
2’b10
: SO <= DI << 2;
default
: SO <= DI << 3;
endcase
end
endmodule
Exa
mpl
e 2 X
ST d
oes
not i
nfer
a lo
gica
l shi
fter
for
this
exa
mpl
e, a
s no
t all
of th
e se
lect
or v
alue
s ar
e pr
esen
ted
.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
IO p
ins
Des
crip
tio
n
D[7
:0]
Dat
a In
put
SEL
Shif
t Dis
tanc
e Se
lect
or
SO[7
:0]
Dat
a O
utpu
t
100
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
entity lshift is
port(DI
: in unsigned(7 downto 0);
SEL
: in unsigned(1 downto 0);
SO
: out unsigned(7 downto 0)
);
end lshift;
architecture archi of lshift is
begin
with SEL select
SO <= DI when "00",
DI sll 1 when "01",
DI sll 2 when others;
end archi;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de.
module lshift (DI, SEL, SO);
input
[7:0] DI;
input
[1:0] SEL;
output
[7:0] SO;
reg
[7:0] SO;
always @(DI or SEL)
begin
case (SEL)
2’b00
: SO <= DI;
2’b01
: SO <= DI << 1;
default
: SO <= DI << 2;
endcase
end
endmodule
Exa
mpl
e 3 X
ST d
oes
not i
nfer
a lo
gica
l shi
fter
for t
his
exam
ple,
as
the
valu
e is
not
incr
emen
ted
by
1 fo
r ea
ch c
onse
quen
t bin
ary
valu
e of
the
sele
ctor
.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
IO p
ins
Des
crip
tio
n
D[7
:0]
Dat
a In
put
SEL
shif
t dis
tanc
e se
lect
or
SO[7
:0]
Dat
a O
utpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m10
1
1-80
0-25
5-77
78
Ari
thm
etic
Op
erat
ion
sR
entity lshift is
port(DI
: in unsigned(7 downto 0);
SEL
: in unsigned(1 downto 0);
SO
: out unsigned(7 downto 0)
);
end lshift;
architecture archi of lshift is
begin
with SEL select
SO <= DI when "00",
DI sll 1 when "01",
DI sll 3 when "10",
DI sll 2 when others;
end archi;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de.
module lshift (DI, SEL, SO);
input
[7:0] DI;
input
[1:0] SEL;
output
[7:0] SO;
reg
[7:0] SO;
always @(DI or SEL)
begin
case (SEL)
2’b00
: SO <= DI;
2’b01
: SO <= DI << 1;
2’b10
: SO <= DI << 3;
default
: SO <= DI << 2;
endcase
end
endmodule
Ari
thm
etic
Op
erat
ion
sX
ST s
upp
orts
the
follo
win
g ar
ithm
etic
ope
rati
ons:
•A
dde
rs w
ith:
♦C
arry
In
♦C
arry
Out
♦C
arry
In/O
ut
•Su
btra
ctor
s
•A
dde
rs/
Subt
ract
ors
•C
ompa
rato
rs (=
, /=
,<, <
=, >
, >=)
•M
ulti
plie
rs
•D
ivid
ers
Add
ers,
su
btra
ctor
s, c
ompa
rato
rs a
nd m
ulti
plie
rs a
re s
uppo
rted
for
sign
ed a
nd u
nsig
ned
op
erat
ions
.
102
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Ple
ase
refe
r to
“Si
gned
/U
nsig
ned
Sup
port
” in
this
cha
pter
for
mor
e in
form
atio
n on
the
sign
ed/u
nsig
ned
ope
rati
ons
supp
ort i
n V
HD
L.
Mor
eove
r, X
ST p
erfo
rms
reso
urce
sha
ring
for
add
ers,
sub
trac
tors
, ad
ders
/su
btra
ctor
s an
d
mu
ltip
liers
.
Add
ers,
Sub
trac
tors
, Add
ers/
Sub
trac
tors
Thi
s se
ctio
n pr
ovid
es H
DL
exa
mpl
es o
f ad
der
s an
d s
ubtr
acto
rs.
Log
File The
XST
log
file
rep
orts
the
type
and
siz
e of
rec
ogni
zed
ad
der
, su
btra
ctor
, and
ad
der
/su
btra
ctor
dur
ing
the
Mac
ro R
ecog
niti
on s
tep.
Rel
ated
Con
stra
ints
The
re a
re n
o re
late
d c
onst
rain
ts a
vaila
ble.
Uns
igne
d 8-
bit A
dder
Thi
s su
bsec
tion
con
tain
s a
VH
DL
and
Ver
ilog
des
crip
tion
of a
n u
nsig
ned
8-b
it a
dd
er.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
an u
nsig
ned
8-b
it a
dd
er.
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r an
uns
igne
d 8
-bit
ad
der
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
...
Synthesizing Unit <adder>.
Related source file is arithmetic_operations_1.vhd.
Found 8-bit adder for signal <sum>.
Summary:
inferred
1 Adder/Subtracter(s).
Unit <adder> synthesized.
=============================
HDL Synthesis Report
Macro Statistics
#Adders/Subtractors
:1
8-bit
adder
:1
==============================
IO p
ins
Des
crip
tio
n
A[7
:0],
B[7:
0]A
dd
Ope
rand
s
SUM
[7:0
]A
dd
Res
ult
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m10
3
1-80
0-25
5-77
78
Ari
thm
etic
Op
erat
ion
sR
entity adder is
port(A,
B: in std_logic_vector(7 downto 0);
SUM
: out std_logic_vector(7 downto 0)
);
end adder;
architecture archi of adder is
begin
SUM <= A + B;
end archi;
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r an
uns
igne
d 8
-bit
ad
der
.
module adder(A, B, SUM);
input
[7:0] A;
input
[7:0] B;
output
[7:0] SUM;
assign SUM = A + B;
endmodule
Uns
igne
d 8-
bit A
dder
with
Car
ry In
Thi
s se
ctio
n co
ntai
ns V
HD
L a
nd V
erilo
g d
escr
ipti
ons
of a
n un
sign
ed 8
-bit
ad
der
wit
h ca
rry
in.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
an u
nsig
ned
8-b
it a
dd
er w
ith
carr
y in
.
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r an
uns
igne
d 8
-bit
ad
der
wit
h ca
rry
in.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A, B
: in std_logic_vector(7 downto 0);
CI
: in std_logic;
SUM
: out std_logic_vector(7 downto 0));
end adder;
architecture archi of adder is
begin
SUM <= A + B + CI;
end archi;
IO p
ins
Des
crip
tio
n
A[7
:0],
B[7:
0]A
dd
Ope
rand
s
CI
Car
ry In
SUM
[7:0
]A
dd
Res
ult
104
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r an
uns
igne
d 8
-bit
ad
der
wit
h ca
rry
in.
module adder(A, B, CI, SUM);
input
[7:0] A;
input
[7:0] B;
input
CI;
output
[7:0] SUM;
assign SUM = A + B + CI;
endmodule
Uns
igne
d 8-
bit A
dder
with
Car
ry O
ut
Thi
s se
ctio
n co
ntai
ns V
HD
L a
nd V
erilo
g d
escr
ipti
ons
of a
n un
sign
ed 8
-bit
ad
der
wit
h ca
rry
out.
If y
ou u
se V
HD
L, t
hen
befo
re w
riti
ng a
"+
" op
erat
ion
wit
h ca
rry
out,
plea
se e
xam
ine
the
arit
hmet
ic p
acka
ge y
ou a
re g
oing
to u
se. F
or e
xam
ple,
"std
_log
ic_u
nsig
ned
" doe
s no
t allo
w
you
to w
rite
"+
" in
the
follo
win
g fo
rm to
obt
ain
Car
ry O
ut:
Res(9-bit) = A(8-bit) + B(8-bit)
The
rea
son
is th
at th
e si
ze o
f the
res
ult f
or "
+"
in th
is p
acka
ge is
equ
al to
the
size
of t
he
long
est a
rgum
ent,
that
is, 8
bit
s.
•O
ne s
olut
ion,
for
the
exam
ple,
is to
ad
just
the
size
of o
pera
nds
A a
nd B
to 9
-bit
s us
ing
conc
aten
atio
n.
Res <= ("0" & A) + ("0" & B);
In th
is c
ase,
XST
reco
gniz
es th
at th
is 9
-bit
ad
der
can
be
impl
emen
ted
as
an 8
-bit
ad
der
w
ith
carr
y ou
t.
•A
noth
er s
olut
ion
is to
con
vert
A a
nd B
to in
tege
rs a
nd th
en c
onve
rt th
e re
sult
bac
k to
th
e st
d_l
ogic
vec
tor,
spec
ifyi
ng th
e si
ze o
f the
vec
tor
equa
l to
9.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
an u
nsig
ned
8-b
it a
dd
er w
ith
carr
y ou
t.
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r an
uns
igne
d 8
-bit
ad
der
wit
h ca
rry
out.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
IO p
ins
Des
crip
tio
n
A[7
:0],
B[7:
0]A
dd
Ope
rand
s
SUM
[7:0
]A
dd
Res
ult
CO
Car
ry O
ut
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m10
5
1-80
0-25
5-77
78
Ari
thm
etic
Op
erat
ion
sR
entity adder is
port(A, B
: in std_logic_vector(7 downto 0);
SUM
: out std_logic_vector(7 downto 0);
CO
: out std_logic
);
end adder;
architecture archi of adder is
signal tmp: std_logic_vector(8 downto 0);
begin
tmp <= conv_std_logic_vector((conv_integer(A) + conv_integer(B)),9);
SUM <= tmp(7 downto 0);
CO
<= tmp(8);
end archi;
In th
e pr
eced
ing
exam
ple,
two
arit
hmet
ic p
acka
ges
are
use
d:
•st
d_l
ogic
_ari
th. T
his
pack
age
cont
ains
the
inte
ger
to s
td_l
ogic
con
vers
ion
func
tion
, th
at is
, con
v_st
d_l
ogic
_vec
tor.
•st
d_l
ogic
_uns
igne
d. T
his
pack
age
cont
ains
the
unsi
gned
"+
" op
erat
ion.
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r an
uns
igne
d 8
-bit
ad
der
wit
h ca
rry
out.
module adder(A, B, SUM, CO);
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
output CO;
wire [8:0] tmp;
assign tmp = A + B;
assign SUM = tmp [7:0];
assign CO = tmp [8];
endmodule
Uns
igne
d 8-
bit A
dder
with
Car
ry In
and
Car
ry O
ut
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
an u
nsig
ned
8-b
it a
dd
er w
ith
carr
y in
and
ca
rry
out.
IO p
ins
Des
crip
tio
n
A[7
:0],
B[7:
0]A
dd
Ope
rand
s
CI
Car
ry In
SUM
[7:0
]A
dd
Res
ult
CO
Car
ry O
ut
106
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r an
uns
igne
d 8
-bit
ad
der
wit
h ca
rry
in a
nd c
arry
out
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A, B
: in std_logic_vector(7 downto 0);
CI
: in std_logic;
SUM
: out std_logic_vector(7 downto 0);
CO
: out std_logic
);
end adder;
architecture archi of adder is
signal tmp: std_logic_vector(8 downto 0);
begin
tmp <= conv_std_logic_vector((conv_integer(A) + conv_integer(B)
+ conv_integer(CI)),9);
SUM <= tmp(7 downto 0);
CO <= tmp(8);
end archi;
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r an
uns
igne
d 8
-bit
ad
der
wit
h ca
rry
in a
nd c
arry
out
.
module adder(A, B, CI, SUM, CO);
input
CI;
input
[7:0] A;
input
[7:0] B;
output
[7:0] SUM;
output CO;
wire [8:0] tmp;
assign tmp = A + B + CI;
assign SUM = tmp [7:0];
assign CO
= tmp [8];
endmodule
Sim
ple
Sig
ned
8-bi
t Add
er
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a si
mpl
e si
gned
8-b
it a
dd
er.
IO p
ins
Des
crip
tio
n
A[7
:0],
B[7:
0]A
dd
Ope
rand
s
SUM
[7:0
]A
dd
Res
ult
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m10
7
1-80
0-25
5-77
78
Ari
thm
etic
Op
erat
ion
sR
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r a
sim
ple
sign
ed 8
-bit
ad
der
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity adder is
port(A, B
: in std_logic_vector(7 downto 0);
SUM
: out std_logic_vector(7 downto 0));
end adder;
architecture archi of adder is
begin
SUM <= A + B;
end archi;
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r a
sim
ple
sign
ed 8
-bit
ad
der
.
module adder (A,B,SUM)
input signed [7:0] A;
input signed [7:0] B;
output signed [7:0] SUM;
wire signed [7:0] SUM;
assign SUM = A + B;
endmodule
Uns
igne
d 8-
bit S
ubtr
acto
r
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
an u
nsig
ned
8-b
it s
ubtr
acto
r.
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r an
uns
igne
d 8
-bit
sub
trac
tor.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity subtr is
port(A, B
: in std_logic_vector(7 downto 0);
RES
: out std_logic_vector(7 downto 0)
);
end subtr;
architecture archi of subtr is
begin
RES <= A - B;
end archi;
IO p
ins
Des
crip
tio
n
A[7
:0],
B[7:
0]Su
b O
per
and
s
RE
S[7:
0]Su
b R
esul
t
108
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r an
uns
igne
d 8
-bit
sub
trac
tor.
module subtr(A, B, RES);
input
[7:0] A;
input
[7:0] B;
output
[7:0] RES;
assign RES = A - B;
endmodule
Uns
igne
d 8-
bit A
dder
/Sub
trac
tor
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
an u
nsig
ned
8-b
it a
dd
er/s
ubtr
acto
r.
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r an
uns
igne
d 8
-bit
ad
der
/su
btra
ctor
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addsub is
port(A, B
: in std_logic_vector(7 downto 0);
OPER
: in std_logic;
RES
: out std_logic_vector(7 downto 0)
);
end addsub;
architecture archi of addsub is
begin
RES <= A + B when OPER=’0’
else A - B;
end archi;
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r an
uns
igne
d 8
-bit
ad
der
/su
btra
ctor
.
module addsub(A, B, OPER, RES);
input
OPER;
input
[7:0] A;
input
[7:0] B;
output
[7:0] RES;
reg
[7:0] RES;
IO p
ins
Des
crip
tio
n
A[7
:0],
B[7:
0]A
dd
/Su
b O
per
and
s
OPE
RA
dd
/Su
b Se
lect
SUM
[7:0
]A
dd
/Su
b R
esul
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m10
9
1-80
0-25
5-77
78
Ari
thm
etic
Op
erat
ion
sR
always @(A or B or OPER)
begin
if (OPER==1’b0)
RES = A + B;
else
RES = A - B;
end
endmodule
Com
para
tors
(=
, /=
,<, <
=, >
, >=
)T
his
sect
ion
cont
ains
a V
HD
L a
nd V
erilo
g d
escr
ipti
on fo
r an
uns
igne
d 8-
bit g
reat
er o
r eq
ual
com
para
tor.
Log
File The
XST
log
file
rep
orts
the
type
and
siz
e of
rec
ogni
zed
com
para
tors
dur
ing
the
Mac
ro
Rec
ogni
tion
ste
p.
Uns
igne
d 8-
bit G
reat
er o
r E
qual
Com
para
tor
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a co
mpa
rato
r.
...
Synthesizing Unit <compar>.
Related source file is comparators_1.vhd.
Found 8-bit comparator greatequal for signal <$n0000> created at
line 10.
Summary:
inferred
1 Comparator(s).
Unit <compar> synthesized.
=============================
HDL Synthesis Report
Macro Statistics
#Comparators
:1
8-bit
comparator greatequal
:1
==============================
...
IO p
ins
Des
crip
tio
n
A[7
:0],
B[7:
0]C
omp
aris
on O
pera
nds
CM
PC
ompa
riso
n R
esu
lt
110
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r an
uns
igne
d 8
-bit
gre
ater
or
equa
l com
para
tor.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compar is
port(A, B
: in std_logic_vector(7 downto 0);
CMP
: out std_logic
);
end compar;
architecture archi of compar is
begin
CMP <= ’1’ when A >= B else ’0’;
end archi;
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r an
uns
igne
d 8
-bit
gre
ater
or
equ
al c
ompa
rato
r.
module compar(A, B, CMP);
input
[7:0] A;
input
[7:0] B;
output
CMP;
assign CMP = A >= B
? 1’b1
: 1’b0;
endmodule
Mul
tiplie
rsW
hen
impl
emen
ting
a m
ulti
plie
r, th
e si
ze o
f the
res
ulti
ng s
igna
l is
equa
l to
the
sum
of 2
op
eran
d le
ngth
s. If
you
mu
ltip
ly A
(8-b
it s
igna
l) b
y B
(4-b
it s
igna
l), t
hen
the
size
of t
he
resu
lt m
ust
be
dec
lare
d a
s a
12-b
it s
igna
l.
Larg
e M
ultip
liers
Usi
ng B
lock
Mul
tiplie
rs
XST
can
gen
erat
e la
rge
mul
tipl
iers
usi
ng a
n 18
x18
bit b
lock
mu
ltip
lier
avai
labl
e in
V
irte
x™-I
I/-I
I Pro
/-I
I Pro
X. F
or m
ulti
plie
rs la
rger
than
this
, XST
can
gen
erat
e la
rger
m
ult
iplie
rs u
sing
mul
tip
le 1
8x18
bit
blo
ck m
ulti
plie
rs.
Reg
iste
red
Mul
tiplie
r
For
Vir
tex™
-II/
-II P
ro/-
II P
ro X
, in
inst
ance
s w
here
a m
ulti
plie
r w
ould
hav
e a
regi
ster
ed
outp
ut, X
ST in
fers
a u
niqu
e re
gist
ered
mul
tipl
ier.
Thi
s re
gist
ered
mu
ltip
lier
is 1
8x18
bit
s.
Und
er th
e fo
llow
ing
cond
itio
ns, a
reg
iste
red
mul
tipl
ier
is n
ot u
sed
, and
a m
ulti
plie
r +
re
gist
er is
use
d in
stea
d.
•O
utp
ut fr
om th
e m
ulti
plie
r go
es to
any
com
pone
nt o
ther
than
the
regi
ster
.
•T
he M
ULT
_ST
YL
E c
onst
rain
t is
set t
o lu
t.
•T
he m
ulti
plie
r is
asy
nchr
onou
s.
•T
he m
ulti
plie
r ha
s co
ntro
l sig
nals
oth
er th
an s
ynch
rono
us r
eset
or
cloc
k en
able
.
•T
he m
ulti
plie
r d
oes
not f
it in
a s
ingl
e 18
x18
bit b
lock
mu
ltip
lier.
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m11
1
1-80
0-25
5-77
78
Ari
thm
etic
Op
erat
ion
sR
The
follo
win
g pi
ns a
re o
ptio
nal f
or a
reg
iste
red
mul
tipl
ier.
•cl
ock
enab
le p
ort
•sy
nchr
onou
s an
d a
sync
hron
ous
rese
t, an
d lo
ad p
orts
Mul
tiplic
atio
n w
ith C
onst
ant
Whe
n on
e of
the
argu
men
ts is
a c
onst
ant,
XST
can
cre
ate
an e
ffic
ient
ded
icat
ed
impl
emen
tati
on c
alle
d a
mu
ltip
lier
wit
h co
nsta
nt o
r K
CM
. Ple
ase
note
that
in th
e cu
rren
t re
leas
e, X
ST d
oes
not i
nfer
a K
CM
aut
omat
ical
ly fo
r su
ch m
ulti
plie
rs. A
KC
M m
ust b
e im
plem
ente
d v
ia th
e M
ULT
_ST
YL
E c
onst
rain
t.
Lim
itatio
ns:
If th
e ei
ther
of t
he a
rgum
ents
is la
rger
than
29
bits
, XST
doe
s no
t use
KC
M im
plem
enta
tion
, ev
en if
it is
spe
cifi
ed w
ith
the
MU
LT_S
TY
LE
con
stra
int.
Log
File The
XST
log
file
rep
orts
the
type
and
siz
e of
rec
ogni
zed
mul
tipl
iers
dur
ing
the
Mac
ro
Rec
ogni
tion
ste
p.
Rel
ated
Con
stra
ints
A r
elat
ed c
onst
rain
t is
MU
LT_S
TY
LE
.
Uns
igne
d 8x
4-bi
t Mul
tiplie
r
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
an u
nsig
ned
8x4
-bit
mul
tipl
ier.
...
Synthesizing Unit <mult>.
Related source file is multipliers_1.vhd.
Found 8x4-bit multiplier for signal <res>.
Summary:
inferred
1 Multiplier(s).
Unit <mult> synthesized.
==============================
HDL Synthesis Report
Macro Statistics
#Multipliers
:1
8x4-bit
multiplier
:1
==============================
...
IO p
ins
Des
crip
tio
n
A[7
:0],
B[3:
0]M
ULT
Ope
rand
s
RE
S[7:
0]M
ULT
Res
ult
112
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r an
uns
igne
d 8
x4-b
it m
ulti
plie
r.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mult is
port(A
: in std_logic_vector(7 downto 0);
B: in std_logic_vector(3 downto 0);
RES
: out std_logic_vector(11 downto 0)
);
end mult;
architecture archi of mult is
begin
RES <= A * B;
end archi;
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r an
uns
igne
d 8
x4-b
it m
ulti
plie
r.
module compar(A, B, RES);
input
[7:0] A;
input
[3:0] B;
output
[11:0] RES;
assign RES = A * B;
endmodule
Pip
elin
ed M
ultip
liers
To in
crea
se th
e sp
eed
of d
esig
ns w
ith
larg
e m
ulti
plie
rs, X
ST is
cap
able
of i
nfer
ring
pi
pelin
ed m
ulti
plie
rs. B
y in
ters
pers
ing
regi
ster
s be
twee
n th
e st
ages
of l
arge
mul
tipl
iers
, pi
pelin
ing
can
sign
ific
antl
y in
crea
se th
e ov
eral
l fre
quen
cy o
f you
r d
esig
n. T
he e
ffec
t of
pipe
linin
g is
sim
ilar
to fl
ip-f
lop
reti
min
g w
hich
is d
escr
ibed
in “
Flip
-Flo
p R
etim
ing”
in
Cha
pter
3.
To in
sert
pip
elin
e st
ages
, des
crib
e th
e ne
cess
ary
regi
ster
s in
you
r HD
L c
ode
and
pla
ce th
em
afte
r an
y m
ulti
plie
rs, t
hen
set t
he M
ULT
_ST
YL
E co
nstr
aint
to p
ipe_
lut.
Whe
n X
ST d
etec
ts v
alid
reg
iste
rs fo
r pi
pelin
ing
and
MU
LT_S
TY
LE
is s
et to
pip
e_lu
t, X
ST
uses
the
max
imu
m n
umbe
r of
ava
ilabl
e re
gist
ers
to r
each
the
max
imum
mu
ltip
lier
spee
d.
XST
aut
omat
ical
ly c
alcu
late
s th
e m
axim
um n
umbe
r of
reg
iste
rs fo
r ea
ch m
ulti
plie
r to
get
th
e be
st fr
eque
ncy.
If y
ou h
ave
not s
peci
fied
suf
fici
ent r
egis
ter
stag
es, a
nd M
ULT
_ST
YL
E is
cod
ed d
irec
tly
on
a si
gnal
, XST
gui
des
you
via
the
HD
L A
dvi
sor
to s
peci
fy th
e op
tim
um n
umbe
r of
reg
iste
r st
ages
. XST
doe
s th
is d
urin
g th
e A
dva
nced
HD
L S
ynth
esis
ste
p. If
the
num
ber
of re
gist
ers
plac
ed a
fter
the
mu
ltip
lier
exce
eds
the
max
imu
m r
equi
red
, and
shi
ft r
egis
ter
extr
acti
on is
ac
tiva
ted,
then
XST
impl
emen
ts th
e un
use
d s
tage
s as
shi
ft r
egis
ters
.
Lim
itatio
ns:
•X
ST c
anno
t pip
elin
e ha
rdw
are
Mu
ltip
liers
.
•X
ST c
anno
t pip
elin
e m
ult
iplie
rs if
reg
iste
rs c
onta
in a
sync
h/sy
nch
set/
rese
t sig
nals
.
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m11
3
1-80
0-25
5-77
78
Ari
thm
etic
Op
erat
ion
sR
Log
File
. VH
DL
Use
the
follo
win
g te
mpl
ates
to im
plem
ent p
ipel
ined
mul
tipl
iers
in V
HD
L.
The
follo
win
g V
HD
L te
mpl
ate
show
s th
e m
ult
iplic
atio
n op
erat
ion
plac
ed o
utsi
de th
e pr
oces
s bl
ock
and
the
pipe
line
stag
es r
epre
sent
ed a
s si
ngle
reg
iste
rs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult is
generic(
A_port_size
: integer
:= 18;
B_port_size
: integer
:= 18
);
port(clk
: in std_logic;
A: in unsigned (A_port_size-1 downto 0);
B: in unsigned (B_port_size-1 downto 0);
MULT
: out unsigned ((A_port_size+B_port_size-1) downto 0)
);
end mult;
====================================================================
*HDL Synthesis
*====================================================================
Synthesizing Unit <my_mult>.
Related source file is pipe_mult_1.vhd.
Found 36-bit register for signal <MULT>.
Found 18-bit register for signal <a_in>.
Found 18-bit register for signal <b_in>.
Found 18x18-bit multiplier for signal <mult_res>.
Found 36-bit register for signal <pipe_1>.
Summary:
inferred 108 D-type flip-flop(s).
inferred
1 Multiplier(s).
Unit <my_mult> synthesized.
...
====================================================================
*Advanced HDL Synthesis
*====================================================================
Found pipelined multiplier on the signal <mult_res> with 1 pipeline
level(s).
INFO:Xst - HDL ADVISOR - You can improve the performance of this
multiplier by adding 3 register level(s).
114
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
architecture beh of mult is
signal a_in, b_in
: unsigned (A_port_size-1 downto 0);
signal mult_res
: unsigned (
(A_port_size+B_port_size-1) downto 0);
signal pipe_1,
pipe_2,
pipe_3
: unsigned ((A_port_size+B_port_size-1) downto 0);
begin
mult_res <= a_in * b_in;
process (clk)
begin
if (clk’event and clk=’1’) then
a_in <= A; b_in <= B;
pipe_1 <= mult_res;
pipe_2 <= pipe_1;
pipe_3 <= pipe_2;
MULT <= pipe_3;
end if;
end process;
end beh;
The
follo
win
g V
HD
L te
mpl
ate
show
s th
e m
ult
iplic
atio
n op
erat
ion
plac
ed in
sid
e th
e pr
oces
s bl
ock
and
the
pipe
line
stag
es r
epre
sent
ed a
s si
ngle
reg
iste
rs.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult is
generic(
A_port_size: integer
:= 18;
B_port_size: integer
:= 18
);
port(clk
: in std_logic;
A: in unsigned (A_port_size-1 downto 0);
B: in unsigned (B_port_size-1 downto 0);
MULT
: out unsigned ((A_port_size+B_port_size-1) downto 0)
);
end mult;
architecture beh of mult is
signal a_in, b_in
: unsigned (A_port_size-1 downto 0);
signal mult_res
: unsigned ((A_port_size+B_port_size-1) downto 0);
signal pipe_2,
pipe_3
: unsigned ((A_port_size+B_port_size-1) downto 0);
begin
process (clk)
begin if (clk’event and clk=’1’) then
a_in <= A; b_in <= B;
mult_res
<= a_in * b_in;
pipe_2
<= mult_res;
pipe_3
<= pipe_2;
MULT
<= pipe_3;
end if;
end process;
end beh;
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m11
5
1-80
0-25
5-77
78
Ari
thm
etic
Op
erat
ion
sR
The
follo
win
g V
HD
L te
mpl
ate
show
s th
e m
ult
iplic
atio
n op
erat
ion
plac
ed o
utsi
de th
e pr
oces
s bl
ock
and
the
pipe
line
stag
es r
epre
sent
ed a
s sh
ift r
egis
ters
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult is
generic(
A_port_size: integer
:= 18;
B_port_size: integer
:= 18
);
port(
clk
: in std_logic;
A: in unsigned (A_port_size-1 downto 0);
B: in unsigned (B_port_size-1 downto 0);
MULT
: out unsigned ((A_port_size+B_port_size-1) downto 0)
);
end mult;
architecture beh of mult is
signal a_in, b_in
: unsigned (A_port_size-1 downto 0);
signal mult_res
: unsigned ((A_port_size+B_port_size-1) downto 0);
type pipe_reg_type is array (2 downto 0) of unsigned
((A_port_size+B_port_size-1) downto 0);
signal pipe_regs
: pipe_reg_type;
begin
mult_res <= a_in * b_in;
process (clk)
begin
if (clk’event and clk=’1’) then
a_in <= A; b_in <= B;
pipe_regs <= mult_res & pipe_regs(2 downto 1);
MULT <= pipe_regs(0);
end if;
end process;
end beh;
Ver
ilog
Use
the
follo
win
g te
mpl
ates
to im
plem
ent p
ipel
ined
mul
tipl
iers
in V
erilo
g.
The
follo
win
g Ve
rilo
g te
mpl
ate
show
s th
e m
ult
iplic
atio
n op
erat
ion
plac
ed o
utsi
de
the
alw
ays
bloc
k an
d th
e pi
pelin
e st
ages
rep
rese
nted
as
sing
le r
egis
ters
.
module mult(clk, A, B, MULT);
input clk;
input [17:0] A;
input [17:0] B;
output [35:0] MULT;
reg [35:0] MULT;
reg [17:0] a_in, b_in;
wire [35:0] mult_res;
reg [35:0] pipe_1, pipe_2, pipe_3;
assign mult_res = a_in * b_in;
116
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
always @(posedge clk)
begin
a_in <= A; b_in <= B;
pipe_1 <= mult_res;
pipe_2 <= pipe_1;
pipe_3 <= pipe_2;
MULT <= pipe_3;
end
endmodule
The
follo
win
g Ve
rilo
g te
mpl
ate
show
s th
e m
ult
iplic
atio
n op
erat
ion
plac
ed in
side
the
proc
ess
bloc
k an
d th
e pi
pelin
e st
ages
are
rep
rese
nted
as
sing
le r
egis
ters
.
module mult(clk, A, B, MULT);
input clk;
input [17:0] A;
input [17:0] B;
output [35:0] MULT;
reg [35:0] MULT;
reg [17:0] a_in, b_in;
reg [35:0] mult_res;
reg [35:0] pipe_2, pipe_3;
always @(posedge clk)
begin
a_in <= A; b_in <= B;
mult_res <= a_in * b_in;
pipe_2 <= mult_res;
pipe_3 <= pipe_2;
MULT <= pipe_3;
end
endmodule
The
follo
win
g Ve
rilo
g te
mpl
ate
show
s th
e m
ult
iplic
atio
n op
erat
ion
plac
ed o
utsi
de
the
alw
ays
bloc
k an
d th
e pi
pelin
e st
ages
rep
rese
nted
as
shif
t reg
iste
rs.
module mult3(clk, A, B, MULT);
input clk;
input [17:0] A;
input [17:0] B;
output [35:0] MULT;
reg [35:0] MULT;
reg [17:0] a_in, b_in;
wire [35:0] mult_res;
reg [35:0] pipe_regs [3:0];
assign mult_res = a_in * b_in;
always @(posedge clk)
begin
a_in <= A; b_in <= B;
{pipe_regs[3],pipe_regs[2],pipe_regs[1],pipe_regs[0]} <=
{MULT, pipe_regs[3],pipe_regs[2],pipe_regs[1]};
end
end module
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m11
7
1-80
0-25
5-77
78
Ari
thm
etic
Op
erat
ion
sR
Div
ider
sD
ivid
ers
are
only
sup
port
ed w
hen
the
div
isor
is a
con
stan
t and
is a
pow
er o
f 2. I
n th
at c
ase,
th
e op
erat
or is
impl
emen
ted
as
a sh
ifte
r; o
ther
wis
e, X
ST is
sues
an
erro
r m
essa
ge.
Log
File Whe
n yo
u im
plem
ent a
div
ider
wit
h a
cons
tant
wit
h th
e p
ower
of 2
, XST
doe
s no
t iss
ue
any
mes
sage
dur
ing
the
Mac
ro R
ecog
niti
on s
tep.
In c
ase
you
r div
ider
doe
s no
t cor
resp
ond
to
the
case
sup
port
ed b
y X
ST, t
he fo
llow
ing
erro
r m
essa
ge d
isp
lays
:
Rel
ated
Con
stra
ints
The
re a
re n
o re
late
d c
onst
rain
ts a
vaila
ble.
Div
isio
n B
y C
onst
ant 2
Thi
s se
ctio
n co
ntai
ns V
HD
L an
d V
erilo
g d
escr
ipti
ons
of a
Div
isio
n B
y C
onst
ant 2
div
ider
.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a D
ivis
ion
By
Con
stan
t 2 d
ivid
er.
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r a
Div
isio
n B
y C
onst
ant 2
div
ider
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity divider is
port(DI
: in unsigned(7 downto 0);
DO
: out unsigned(7 downto 0)
);
end divider;
architecture archi of divider is
begin
DO <= DI / 2;
end archi;
...
ERROR:Xst:719 - file1.vhd (Line 172).
Operator is not supported yet: ’DIVIDE’
...
IO p
ins
Des
crip
tio
n
DI[
7:0]
Div
isio
n O
pera
nds
DO
[7:0
]D
ivis
ion
Res
ult
118
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r a
Div
isio
n B
y C
onst
ant 2
div
ider
.
module divider(DI, DO);
input [7:0] DI;
output [7:0] DO;
assign DO = DI / 2;
endmodule
Res
ourc
e S
harin
gT
he g
oal o
f res
ourc
e sh
arin
g (a
lso
know
n as
fold
ing)
is to
min
imiz
e th
e nu
mbe
r of
op
erat
ors
and
the
subs
eque
nt lo
gic
in th
e sy
nthe
size
d d
esig
n. T
his
opti
miz
atio
n is
bas
ed
on th
e pr
inci
ple
that
two
sim
ilar
arit
hmet
ic r
esou
rces
may
be
impl
emen
ted
as
one
sing
le
arit
hmet
ic o
pera
tor
if th
ey a
re n
ever
use
d a
t the
sam
e ti
me.
XST
per
form
s bo
th r
esou
rce
shar
ing
and
, if r
equi
red
, red
uce
s th
e nu
mbe
r of m
ulti
plex
ers
that
are
cre
ated
in th
e pr
oces
s.
XST
su
ppor
ts r
esou
rce
shar
ing
for
add
ers,
su
btra
ctor
s, a
dd
ers/
subt
ract
ors
and
m
ult
iplie
rs.
If th
e op
tim
izat
ion
goal
is S
PEE
D, t
hen
the
dis
ablin
g of
reso
urce
sha
ring
may
lead
to b
ette
r re
sult
s. X
ST a
dvi
ses
you
to tr
y to
dea
ctiv
ate
reso
urce
sha
ring
at t
he A
dva
nce
HD
L Sy
nthe
sis
step
in o
rder
to im
prov
e cl
ock
freq
uenc
y.
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m11
9
1-80
0-25
5-77
78
Ari
thm
etic
Op
erat
ion
sR
Log
File The
XST
log
file
repo
rts
the
type
and
siz
e of
reco
gniz
ed a
rith
met
ic b
lock
s an
d m
ult
iple
xers
d
urin
g th
e M
acro
Rec
ogni
tion
ste
p.
Rel
ated
Con
stra
int
The
rel
ated
con
stra
int i
s R
ESO
UR
CE
_SH
AR
ING
.
Exa
mpl
e
For
the
follo
win
g V
HD
L/
Ver
ilog
exam
ple,
XST
giv
es th
e fo
llow
ing
solu
tion
.
...
Synthesizing Unit <addsub>.
Related source file is resource_sharing_1.vhd.
Found 8-bit addsub for signal <res>.
Found 8 1-bit 2-to-1 multiplexers.
Summary:
inferred
1 Adder/Subtracter(s).
inferred
8 Multiplexer(s).
Unit <addsub> synthesized.
==============================
HDL Synthesis Report
Macro Statistics
#Multiplexers
: 1
2-to-1
multiplexer
: 1
#Adders/Subtractors
: 1
8-bit
addsub
: 1
==============================
...
===================================================================
*Advanced HDL Synthesis
*===================================================================
INFO:Xst - HDL ADVISOR - Resource sharing has identified that some
arithmetic operations in this design can share the same physical
resources for reduced device utilization. For improved clock
frequency you may try to disable resource sharing.
...
X89
84
B C
A
+/-
RE
S
OP
ER
OP
ER
120
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
the
exam
ple.
VH
DL
Follo
win
g is
the
VH
DL
exa
mpl
e fo
r re
sou
rce
shar
ing.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addsub is
port(A, B, C: in std_logic_vector(7 downto 0);
OPER
: in std_logic;
RES
: out std_logic_vector(7 downto 0)
);
end addsub;
architecture archi of addsub is
begin
RES <= A + B when OPER=’0’ else A - C;
end archi;
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r re
sou
rce
shar
ing.
module addsub(A, B, C, OPER, RES);
input OPER;
input [7:0] A;
input [7:0] B;
input [7:0] C;
output [7:0] RES;
reg [7:0] RES;
always @(A or B or C or OPER)
begin
if (OPER==1’b0)
RES = A + B;
else RES = A - C;
end
endmodule
IO p
ins
Des
crip
tio
n
A[7
:0],
B[7:
0], C
[7:0
]O
pera
nds
OPE
RO
pera
tion
Sel
ecto
r
RE
S[7:
0]D
ata
Out
put
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m12
1
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
RA
Ms/
RO
Ms
If y
ou d
o no
t wan
t to
inst
anti
ate
RA
M p
rim
itiv
es to
kee
p yo
ur
HD
L c
ode
tech
nolo
gy
inde
pend
ent,
XST
off
ers
an a
utom
atic
RA
M r
ecog
niti
on c
apab
ility
. XST
can
infe
r d
istr
ibut
ed a
s w
ell a
s B
lock
RA
M. I
t cov
ers
the
follo
win
g ch
arac
teri
stic
s, o
ffer
ed b
y th
ese
RA
M ty
pes.
•Sy
nchr
onou
s w
rite
•W
rite
ena
ble
•R
AM
ena
ble
•A
sync
hron
ous
or s
ynch
rono
us r
ead
•R
eset
of t
he d
ata
outp
ut la
tche
s
•D
ata
outp
ut r
eset
•Si
ngle
, dua
l or
mul
tipl
e-po
rt r
ead
•Si
ngle
-por
t wri
te
The
type
of i
nfer
red
RA
M d
epen
ds
on it
s d
escr
ipti
on.
•R
AM
des
crip
tion
s w
ith
an a
sync
hron
ous
read
gen
erat
e a
dis
trib
uted
RA
M m
acro
.
•R
AM
des
crip
tion
s w
ith
a sy
nchr
onou
s re
ad g
ener
ate
a B
lock
RA
M m
acro
. In
som
e ca
ses,
a B
lock
RA
M m
acro
can
act
ual
ly b
e im
ple
men
ted
wit
h D
istr
ibut
ed R
AM
. The
d
ecis
ion
on th
e ac
tual
RA
M im
plem
enta
tion
is d
one
by th
e m
acro
gen
erat
or.
Follo
win
g is
the
list o
f VH
DL
/V
erilo
g te
mpl
ates
that
are
des
crib
ed b
elow
.
•V
irte
x-II
RA
M R
ead
/W
rite
mod
es
♦R
ead
-Fir
st M
ode
♦W
rite
-Fir
st M
ode
♦N
o-C
hang
e M
ode
•Si
ngle
-Por
t RA
M w
ith
Asy
nchr
onou
s R
ead
•Si
ngle
-Por
t RA
M w
ith
"Fal
se"
Sync
hron
ous
Rea
d
•Si
ngle
-Por
t RA
M w
ith
Sync
hron
ous
Rea
d (R
ead
Thr
ough
)
•Si
ngle
-Por
t RA
M w
ith
Ena
ble
•D
ual
-Por
t RA
M w
ith
Asy
nchr
onou
s R
ead
•D
ual
-Por
t RA
M w
ith
Fals
e Sy
nchr
onou
s R
ead
•D
ual
-Por
t RA
M w
ith
Sync
hron
ous
Rea
d (R
ead
Thr
ough
)
•D
ual
-Por
t RA
M w
ith
One
Ena
ble
Con
trol
ling
Bot
h Po
rts
•D
ual
-Por
t RA
M w
ith
Ena
ble
Con
trol
ling
Eac
h Po
rt
•D
ual
-Por
t RA
M w
ith
Dif
fere
nt C
lock
s
•M
ulti
ple
-Por
t RA
M D
escr
ipti
ons
•B
lock
RA
M w
ith
Res
et
•In
itia
lizin
g Bl
ock
RA
M
•R
OM
s U
sing
Blo
ck R
AM
Res
ourc
es
If a
giv
en te
mpl
ate
can
be im
plem
ente
d u
sing
Blo
ck a
nd D
istr
ibut
ed R
AM
, XST
im
plem
ents
BL
OC
K o
nes.
You
can
use
the
RA
M_S
TY
LE c
onst
rain
t to
cont
rol R
AM
im
plem
enta
tion
and
sel
ect a
des
irab
le R
AM
type
. Ple
ase
refe
r to
Cha
pter
5, “
Des
ign
Con
stra
ints
” fo
r m
ore
deta
ils.
122
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Plea
se n
ote
that
the
follo
win
g fe
atur
es s
peci
fica
lly a
vaila
ble
wit
h B
lock
RA
M a
re n
ot y
etsu
ppor
ted
.
•D
ual
wri
te p
ort
•Pa
rity
bit
s
•D
iffe
rent
asp
ect r
atio
s on
eac
h po
rt
Ple
ase
refe
r to
Cha
pter
3, “
FPG
A O
ptim
izat
ion”
for
mor
e d
etai
ls o
n R
AM
impl
emen
tati
on.
No
te:
Not
e th
at X
ST
can
impl
emen
t Sta
te M
achi
nes
(see
“S
tate
Mac
hine
”) a
nd m
ap g
ener
al lo
gic
(see
“M
appi
ng L
ogic
ont
o B
lock
RA
M”
in C
hapt
er 3
) on
Blo
ck R
AM
s.
Log
File
The
XST
log
file
rep
orts
the
type
and
siz
e of
rec
ogni
zed
RA
M a
s w
ell a
s co
mpl
ete
info
rmat
ion
on it
s I/
O p
orts
dur
ing
the
Mac
ro R
ecog
niti
on s
tep.
Rel
ated
Con
stra
ints
Rel
ated
con
stra
ints
are
RA
M_E
XT
RA
CT,
RA
M_S
TY
LE
, RO
M_E
XT
RA
CT
and
R
OM
_ST
YL
E.
...
Synthesizing Unit <raminfr>.
Related source file is rams_1.vhd.
Found 128-bit single-port distributed RAM for signal <ram>.
----------------------------------------------------------
|aspect
ratio
|32-wordx
4-bit
||
|clock
|connected
to
signal
<clk>
|rise
|
|write
enable
|connected
to
signal
<we>
|high
|
|address
|connected
to
signal
<a>
||
|data
in
|connected
to
signal
<di>
||
|data
out
|connected
to
signal
<do>
||
|ram_style
|Auto
||
---------------------------------------------------------
INFO:Xst - For optimized device usage and improved timings, you
may take advantage of available block RAM resources by
registering the read address.
Summary:
inferred
1 RAM(s).
Unit <raminfr> synthesized.
====================================
HDL Synthesis Report
Macro Statistics
#RAMs
:1
128-bit
single-port
distributed RAM
:1
===================================
...
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m12
3
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
Virt
ex-I
I™/S
part
an-3
™ R
AM
Rea
d/W
rite
Mod
esB
lock
RA
M r
esou
rces
ava
ilabl
e in
Vir
tex™
-II/
-II P
ro/-
II P
ro X
and
Spa
rtan
-3™
off
er
diff
eren
t rea
d/
wri
te s
ynch
roni
zati
on m
odes
. Thi
s se
ctio
n pr
ovid
es c
odin
g ex
ampl
es fo
r all
thre
e m
odes
that
are
ava
ilabl
e: w
rite
-fir
st, r
ead
-fir
st, a
nd n
o-ch
ange
.
The
follo
win
g ex
ampl
es d
escr
ibe
a si
mp
le s
ingl
e-po
rt b
lock
RA
M. Y
ou c
an d
educ
e d
escr
ipti
ons
of d
ual
-por
t blo
ck R
AM
s fr
om th
ese
exam
ples
. Dua
l-po
rt b
lock
RA
Ms
can
be
conf
igur
ed w
ith
a d
iffe
rent
rea
d/w
rite
mod
e on
eac
h po
rt. I
nfer
ence
sup
port
s th
is
capa
bilit
y.
The
follo
win
g ta
ble
sum
mar
izes
sup
port
for
read
/w
rite
mod
es a
ccor
ding
to th
e ta
rget
ed
fam
ily a
nd h
ow X
ST h
and
les
it.
Rea
d-F
irst M
ode
The
follo
win
g te
mpl
ates
sho
w a
sin
gle-
por
t RA
M in
rea
d-f
irst
mod
e.
VH
DL
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
en
: in std_logic;
addr
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0)
);
end raminfr;
Fam
ily In
ferr
ed
Mo
des
Beh
avio
r
Spar
tan-
3™V
irte
x-II
™,
Vir
tex-
II P
ro,
Vir
tex-
II P
ro X
wri
te-f
irst
, re
ad-f
irst
, no
-cha
nge
•M
acro
infe
renc
e an
d g
ener
atio
n
•A
ttac
h ad
equ
ate
WR
ITE
_MO
DE
, W
RIT
E_M
OD
E_A
, W
RIT
E_M
OD
E_B
con
stra
ints
to
gene
rate
d b
lock
RA
Ms
in N
CF
Vir
tex™
, V
irte
x-E
, Sp
arta
n-II
Spar
tan-
IIE
wri
te-f
irst
•M
acro
infe
renc
e an
d g
ener
atio
n
•N
o co
nstr
aint
to a
ttac
h on
ge
nera
ted
blo
ck R
AM
s
CPL
Dno
neR
AM
infe
renc
e co
mpl
etel
y d
isab
led
124
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
begin
process (clk)
begin
if clk’event and clk = ’1’ then
if en = ’1’ then
if we = ’1’ then
RAM(conv_integer(addr)) <= di;
end if;
do <= RAM(conv_integer(addr));
end if;
end if;
end process;
end syn;
Ver
ilog
module raminfr (clk, en, we, addr, di, do);
input clk;
input we;
input en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg [3:0] RAM [31:0];
reg [3:0] do;
always @(posedge clk)
begin
if (en)
begin
if (we)
RAM[addr]
<=
di;
do <= RAM[addr];
end
end
endmodule
Writ
e-F
irst M
ode
The
follo
win
g te
mpl
ates
sho
w a
sin
gle-
por
t RA
M in
wri
te-f
irst
mod
e.
VH
DL
The
follo
win
g te
mpl
ate
show
s th
e re
com
men
ded
con
figu
rati
on c
oded
in V
HD
L.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
en
: in std_logic;
addr
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0));
end raminfr;
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m12
5
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
begin
process (clk)
begin
if clk’event and clk = ’1’ then
if en = ’1’ then
if we = ’1’ then
RAM(conv_integer(addr)) <= di;
do <= di;
else do <= RAM(conv_integer(addr));
end if;
end if;
end if;
end process;
end syn;
The
follo
win
g te
mpl
ates
sho
w a
n al
tern
ate
conf
igur
atio
n of
a s
ingl
e-p
ort R
AM
in
wri
te-f
irst
mod
e w
ith
a re
gist
ered
rea
d a
dd
ress
cod
ed in
VH
DL
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
en
: in std_logic;
addr
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
signal read_addr
: std_logic_vector(4 downto 0);
begin
process (clk)
begin if clk’event and clk = ’1’ then
if en = ’1’ then
if we = ’1’ then
mem(conv_integer(addr)) <= di;
end if;
read_addr <= addr;
end if;
end if;
end process;
do <= ram(conv_integer(read_addr));
end syn;
126
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Ver
ilog
The
follo
win
g te
mpl
ate
show
s th
e re
com
men
ded
con
figu
rati
on c
oded
in V
erilo
g.
module raminfr (clk, we, en, addr, di, do);
input clk;
input we;
input en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg [3:0] RAM [31:0];
reg [4:0] read_addr;
always @(posedge clk)
begin
if (en)
begin
if (we)
RAM[addr] <= di;
read_addr <= addr;
end
end
assign do = RAM[read_addr];
endmodule
No-
Cha
nge
Mod
e
The
follo
win
g te
mpl
ates
sho
w a
sin
gle-
por
t RA
M in
no-
chan
ge m
ode.
VH
DL
The
follo
win
g te
mpl
ate
show
s th
e re
com
men
ded
con
figu
rati
on c
oded
in V
HD
L.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
en
: in std_logic;
addr
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0)
);
end raminfr;
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m12
7
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
begin
process (clk)
begin
if clk’event and clk = ’1’ then
if en = ’1’ then
if we = ’1’ then
RAM(conv_integer(addr)) <= di;
else do <= RAM(conv_integer(addr));
end if;
end if;
end if;
end process;
end syn;
The
follo
win
g te
mpl
ates
sho
w a
n al
tern
ate
conf
igur
atio
n of
a s
ingl
e-p
ort R
AM
inno
-cha
nge
mod
e w
ith
a re
gist
ered
rea
d ad
dre
ss c
oded
in V
HD
L.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
en
: in std_logic;
addr
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
signal read_addr
: std_logic_vector(4 downto 0);
begin
process (clk)
begin
if clk’event and clk = ’1’ then
if en = ’1’ then
if we = ’1’ then
RAM(conv_integer(addr)) <= di;
else read_addr <= addr;
end if;
end if;
end if;
end process;
do <= RAM(read_addr);
end syn;
128
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Ver
ilog
The
follo
win
g te
mpl
ate
show
s th
e re
com
men
ded
con
figu
rati
on c
oded
in V
erilo
g.
module raminfr (clk, we, en, addr, di, do);
input clk;
input we;
input en;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg [3:0] RAM [31:0];
reg [3:0] do;
always @(posedge clk)
begin if (en)
begin
if (we)
RAM[addr] <= di;
else do <= RAM[addr];
end
end
endmodule
Sin
gle-
Por
t RA
M w
ith A
sync
hron
ous
Rea
dT
he fo
llow
ing
desc
ript
ions
are
dir
ectl
y m
appa
ble
onto
dis
trib
uted
RA
M o
nly.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for a
sin
gle-
port
RA
M w
ith
asyn
chro
nous
read
.
IO P
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
we
Sync
hron
ous
Wri
te E
nabl
e (A
ctiv
e H
igh)
aR
ead
/Wri
te A
dd
ress
di
Dat
a In
put
do
Dat
a O
utpu
t
X89
76
Dis
trib
uted
RA
MD
O
WE DI A
CLK
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m12
9
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a si
ngle
-por
t RA
M w
ith
asyn
chro
nous
rea
d.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
a: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
RAM(conv_integer(a)) <= di;
end if;
end if;
end process;
do <= RAM(conv_integer(a));
end syn;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a si
ngle
-por
t RA
M w
ith
asyn
chro
nous
rea
d.
module raminfr (clk, we, a, di, do);
input clk;
input we;
input
[4:0] a;
input
[3:0] di;
output
[3:0] do;
reg
[3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign do = ram[a];
endmodule
130
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR Sin
gle-
Por
t RA
M w
ith "
Fal
se"
Syn
chro
nous
Rea
dT
he fo
llow
ing
des
crip
tion
s d
o no
t im
plem
ent t
rue
sync
hron
ous
read
acc
ess
as d
efin
ed b
y th
e V
irte
x™ b
lock
RA
M s
pec
ific
atio
n, w
here
the
read
ad
dre
ss is
reg
iste
red
. The
y ar
e on
ly
map
pabl
e on
to D
istr
ibut
ed R
AM
wit
h an
ad
diti
onal
buf
fer
on th
e d
ata
outp
ut, a
s sh
own
belo
w.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a si
ngle
-por
t RA
M w
ith
“fal
se”
sync
hron
ous
read
.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a si
ngle
-por
t RA
M w
ith
“fal
se”
sync
hron
ous
read
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
a: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0)
);
end raminfr;
IO P
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
we
Sync
hron
ous
Wri
te E
nabl
e (A
ctiv
e H
igh)
aR
ead
/Wri
te A
dd
ress
di
Dat
a In
put
do
Dat
a O
utpu
t
X89
77
Dis
trib
uted
RA
MD
O
WE DI A
CLK
D
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m13
1
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
RAM(conv_integer(a)) <= di;
end if;
do <= RAM(conv_integer(a));
end if;
end process;
end syn;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a si
ngle
-por
t RA
M w
ith
“fal
se”
sync
hron
ous
read
.
module raminfr (clk, we, a, di, do);
input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [3:0] do;
always @(posedge clk) begin
if (we)
ram[a] <= di;
do <= ram[a];
end
endmodule
The
follo
win
g d
escr
ipti
ons,
feat
urin
g an
ad
dit
iona
l res
et o
f the
RA
M o
utp
ut, a
re a
lso
only
m
appa
ble
onto
Dis
trib
uted
RA
M w
ith
an a
ddi
tion
al r
eset
able
buf
fer
on th
e d
ata
outp
ut a
s sh
own
in th
e fo
llow
ing
figu
re:
X89
78
Dis
trib
uted
RA
MD
O
WE DI A
CLK
DRS
T
132
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a si
ngle
-por
t RA
M w
ith
“fal
se”
sync
hron
ous
read
and
res
et o
n th
e ou
tput
.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
rst
: in std_logic;
a: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
RAM(conv_integer(a)) <= di;
end if;
if (rst = ’1’) then
do <= (others => ’0’);
else do <= RAM(conv_integer(a));
end if;
end if;
end process;
end syn;
IO P
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
we
Sync
hron
ous
Wri
te E
nabl
e (a
ctiv
e H
igh)
rst
Sync
hron
ous
Out
put R
eset
(act
ive
Hig
h)
aR
ead
/Wri
te A
dd
ress
di
Dat
a In
put
do
Dat
a O
utpu
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m13
3
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de.
module raminfr (clk, we, rst, a, di, do);
input clk;
input we;
input rst;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [3:0] do;
always @(posedge clk) begin
if (we)
ram[a] <= di;
if (rst)
do <= 4’b0;
else do <= ram[a];
end
endmodule
Sin
gle-
Por
t RA
M w
ith S
ynch
rono
us R
ead
(Rea
d T
hrou
gh)
The
follo
win
g de
scri
ptio
n im
plem
ents
a tr
ue s
ynch
rono
us
read
. A tr
ue s
ynch
rono
us r
ead
is
the
sync
hron
izat
ion
mec
hani
sm a
vaila
ble
in V
irte
x™ b
lock
RA
Ms,
whe
re th
e re
ad
add
ress
is r
egis
tere
d o
n th
e R
AM
clo
ck e
dge
. Su
ch d
escr
ipti
ons
are
dire
ctly
map
pabl
e on
to
Blo
ck R
AM
, as
show
n be
low
. (T
he s
ame
des
crip
tion
s ca
n al
so b
e m
appe
d o
nto
Dis
trib
uted
R
AM
).
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a si
ngle
-por
t RA
M w
ith
sync
hron
ous
read
(r
ead
thro
ugh
).
IO p
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
we
Sync
hron
ous
Wri
te E
nabl
e (A
ctiv
e H
igh)
aR
ead
/Wri
te A
dd
ress
di
Dat
a In
put
do
Dat
a O
utpu
t
X89
79
Blo
ckR
AM
DO
WE DI A
CLK
134
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a si
ngle
-por
t RA
M w
ith
sync
hron
ous
read
(rea
d th
rou
gh).
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
a: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
signal read_a
: std_logic_vector(4 downto 0);
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
RAM(conv_integer(a)) <= di;
end if;
read_a <= a;
end if;
end process;
do <= RAM(conv_integer(read_a));
end syn;
Ver
ilog Fo
llow
ing
is th
e V
erilo
g co
de
for a
sin
gle-
port
RA
M w
ith
sync
hron
ous
read
(rea
d th
rou
gh).
module raminfr (clk, we, a, di, do);
input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [4:0] read_a;
always @(posedge clk) begin
if (we)
ram[a] <= di;
read_a <= a;
end
assign do = ram[read_a];
endmodule
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m13
5
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
Sin
gle-
Por
t RA
M w
ith E
nabl
eT
he fo
llow
ing
desc
ript
ion
impl
emen
ts a
sin
gle-
port
RA
M w
ith
a gl
obal
ena
ble.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a si
ngle
-por
t RA
M w
ith
enab
le.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a si
ngle
-por
t blo
ck R
AM
wit
h en
able
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
en
: in std_logic;
we
: in std_logic;
a: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0)
);
end raminfr;
IO p
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
enG
loba
l Ena
ble
we
Sync
hron
ous
Wri
te E
nabl
e (A
ctiv
e H
igh)
aR
ead
/Wri
te A
dd
ress
di
Dat
a In
put
do
Dat
a O
utpu
t
X94
78
EN
DO
A
WE DI
CLK
Blo
ckR
AM
136
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
signal read_a
: std_logic_vector(4 downto 0);
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (en = ‘1’) then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
read_a <= a;
end if;
end if;
end process;
do <= RAM(conv_integer(read_a));
end syn;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a si
ngle
-por
t blo
ck R
AM
wit
h en
able
.
module raminfr (clk, en, we, a, di, do);
input clk;
input en;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [4:0] read_a;
always @(posedge clk) begin
if (en)
begin
if (we)
ram[a] <= di;
read_a <= a;
end
end
assign do = ram[read_a];
endmodule
Dua
l-Por
t RA
M w
ith A
sync
hron
ous
Rea
dT
he fo
llow
ing
exam
ple
show
s w
here
the
two
outp
ut p
orts
are
use
d. I
t is
dir
ectl
y m
appa
ble
onto
Dis
trib
uted
RA
M o
nly.
X89
80
Dis
trib
uted
RA
MD
PO
SP
OW
E
DP
RA DI A
CLK
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m13
7
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a d
ual-
port
RA
M w
ith
asyn
chro
nous
rea
d.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a d
ual-
port
RA
M w
ith
asyn
chro
nous
rea
d.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
a: in std_logic_vector(4 downto 0);
dpra
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
spo
: out std_logic_vector(3 downto 0);
dpo
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
RAM(conv_integer(a)) <= di;
end if;
end if;
end process;
spo <= RAM(conv_integer(a));
dpo <= RAM(conv_integer(dpra));
end syn;
IO p
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
we
Sync
hron
ous
Wri
te E
nabl
e (a
ctiv
e H
igh)
aW
rite
Ad
dre
ss/
Pri
mar
y R
ead
Ad
dre
ss
dp
raD
ual R
ead
Add
ress
di
Dat
a In
put
spo
Prim
ary
Out
put P
ort
dpo
Dua
l Ou
tput
Por
t
138
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a d
ual-
port
RA
M w
ith
asyn
chro
nous
rea
d.
module raminfr (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg [3:0] ram [31:0];
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
assign spo = ram[a];
assign dpo = ram[dpra];
endmodule
Dua
l-Por
t RA
M w
ith F
alse
Syn
chro
nous
Rea
dT
he fo
llow
ing
desc
ript
ion
is m
appe
d on
to D
istr
ibut
ed R
AM
wit
h ad
dit
iona
l reg
iste
rs o
n th
e d
ata
outp
uts.
Ple
ase
note
that
this
tem
plat
e do
es n
ot d
escr
ibe
du
al-p
ort b
lock
RA
M.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a d
ual-
port
RA
M w
ith
fals
e sy
nchr
onou
s re
ad.
IO P
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
we
Sync
hron
ous
Wri
te E
nabl
e (a
ctiv
e H
igh)
aW
rite
Ad
dre
ss/
Pri
mar
y R
ead
Ad
dre
ss
dpr
aD
ual R
ead
Add
ress
di
Dat
a In
put
spo
Prim
ary
Out
put P
ort
dpo
Dua
l Ou
tput
Por
t
X89
81
Dis
trib
uted
RA
M
WE
DP
RA DI A
CLK
CLK
CLK
SP
OD
DP
OD
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m13
9
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a d
ual-
port
RA
M w
ith
fals
e sy
nchr
onou
s re
ad.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
a: in std_logic_vector(4 downto 0);
dpra
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
spo
: out std_logic_vector(3 downto 0);
dpo
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0)
of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
RAM(conv_integer(a)) <= di;
end if;
spo <= RAM(conv_integer(a));
dpo <= RAM(conv_integer(dpra));
end if;
end process;
end syn;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a d
ual-
port
RA
M w
ith
fals
e sy
nchr
onou
s re
ad.
module raminfr (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg [3:0] ram [31:0];
reg [3:0] spo;
reg [3:0] dpo;
always @(posedge clk) begin
if (we)
ram[a] <= di;
spo = ram[a];
dpo = ram[dpra];
end
endmodule
140
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR Dua
l-Por
t RA
M w
ith S
ynch
rono
us R
ead
(Rea
d T
hrou
gh)
The
follo
win
g d
escr
ipti
ons
are
dire
ctly
map
pabl
e on
to B
lock
RA
M, a
s sh
own
in th
e fo
llow
ing
figu
re. (
The
y m
ay a
lso
be im
plem
ente
d w
ith
Dis
trib
uted
RA
M.).
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a d
ual-
port
RA
M w
ith
sync
hron
ous
read
(r
ead
thro
ugh
).
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a d
ual-
port
RA
M w
ith
sync
hron
ous
read
(rea
d th
rou
gh).
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
a: in std_logic_vector(4 downto 0);
dpra
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
spo
: out std_logic_vector(3 downto 0);
dpo
: out std_logic_vector(3 downto 0)
);
end raminfr;
IO P
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
we
Sync
hron
ous
Wri
te E
nabl
e (A
ctiv
e H
igh)
aW
rite
Ad
dre
ss/
Pri
mar
y R
ead
Ad
dre
ss
dpr
aD
ual R
ead
Add
ress
di
Dat
a In
put
spo
Prim
ary
Out
put P
ort
dpo
Dua
l Ou
tput
Por
t
X89
82
Blo
ckR
AM
DP
O
SP
OW
E
DP
RA DI A
CLK
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m14
1
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
signal read_a
: std_logic_vector(4 downto 0);
signal read_dpra
: std_logic_vector(4 downto 0);
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
RAM(conv_integer(a)) <= di;
end if;
read_a <= a;
read_dpra <= dpra;
end if;
end process;
spo <= RAM(conv_integer(read_a));
dpo <= RAM(conv_integer(read_dpra));
end syn;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a d
ual-
port
RA
M w
ith
sync
hron
ous
read
(rea
d th
rou
gh).
module raminfr (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;
reg [3:0] ram [31:0];
reg [4:0] read_a;
reg [4:0] read_dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
read_a <= a;
read_dpra <= dpra;
end
assign spo = ram[read_a];
assign dpo = ram[read_dpra];
endmodule
Usi
ng M
ore
than
One
Clo
ck
The
two
RA
M p
orts
may
be
sync
hron
ized
on
dis
tinc
t clo
cks,
as
show
n in
the
follo
win
g d
escr
ipti
on. I
n th
is c
ase,
onl
y a
Blo
ck R
AM
impl
emen
tati
on is
app
licab
le.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a d
ual-
port
RA
M w
ith
sync
hron
ous
read
(r
ead
thro
ugh
) and
two
cloc
ks.
IO p
ins
Des
crip
tio
n
clk1
Posi
tive
-Ed
ge W
rite
/Pr
imar
y R
ead
Clo
ck
clk2
Pos
itiv
e-E
dge
Dua
l Rea
d C
lock
142
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
VH
DL
Follo
win
g is
the
VH
DL
cod
e.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk1
: in std_logic;
clk2
: in std_logic;
we
: in std_logic;
add1
: in std_logic_vector(4 downto 0);
add2
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do1
: out std_logic_vector(3 downto 0);
do2
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
signal read_add1
: std_logic_vector(4 downto 0);
signal read_add2
: std_logic_vector(4 downto 0);
begin
process (clk1)
begin
if (clk1’event and clk1 = ’1’) then
if (we = ’1’) then
RAM(conv_integer(add1)) <= di;
end if;
read_add1 <= add1;
end if;
end process;
do1 <= RAM(conv_integer(read_add1));
process (clk2)
begin
if (clk2’event and clk2 = ’1’) then
read_add2 <= add2;
end if;
end process;
do2 <= RAM(conv_integer(read_add2));
end syn;
we
Sync
hron
ous
Wri
te E
nabl
e (A
ctiv
e H
igh)
add
1W
rite
/P
rim
ary
Rea
d A
ddr
ess
add
2D
ual R
ead
Add
ress
di
Dat
a In
put
do1
Prim
ary
Out
put P
ort
do2
Dua
l Ou
tput
Por
t
IO p
ins
Des
crip
tio
n
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m14
3
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e.
module raminfr (clk, en, we, addra, addrb, di, doa, dob);
input clk;
input en;
input we;
input [4:0] addra;
input [4:0] addrb;
input [3:0] di;
output [3:0] doa;
output [3:0] dob;
reg [3:0] ram [31:0];
reg [4:0] read_addra;
reg [4:0] read_addrb;
always @(posedge clk) begin
if (en)
begin
if (we)
ram[addra] <= di;
read_addra <= addra;
read_addrb <= addrb;
end
end
assign doa = ram[read_addra];
assign dob = ram[read_addrb];
endmodule
Dua
l-Por
t RA
M w
ith O
ne E
nabl
e C
ontr
ollin
g B
oth
Por
tsT
he fo
llow
ing
des
crip
tion
s ar
e di
rect
ly m
appa
ble
onto
Blo
ck R
AM
, as
show
n in
the
follo
win
g fi
gure
.
X94
77
AD
DR
B
DO
B
DO
A
AD
DR
A
EN
WB DI
CLK
Blo
ckR
AM
144
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a d
ual-
port
RA
M w
ith
one
enab
le
cont
rolli
ng b
oth
port
s.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a d
ual-
port
RA
M w
ith
one
glob
al e
nabl
e co
ntro
lling
bot
h po
rts. library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
en
: in std_logic;
we
: in std_logic;
addra
: in std_logic_vector(4 downto 0);
addrb
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
doa
: out std_logic_vector(3 downto 0);
dob
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
signal read_addra
: std_logic_vector(4 downto 0);
signal read_addrb
: std_logic_vector(4 downto 0);
IO P
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
enPr
imar
y G
loba
l Ena
ble
(act
ive
Hig
h)
we
Prim
ary
Sync
hron
ous
Wri
te E
nabl
e (a
ctiv
e H
igh)
add
raW
rite
Ad
dre
ss/
Pri
mar
y R
ead
Ad
dre
ss
add
rbD
ual
Rea
d A
ddre
ss
di
Prim
ary
Dat
a In
put
doa
Prim
ary
Out
put P
ort
dob
Dua
l Ou
tput
Por
t
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m14
5
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (en = ’1’) then
if (we = ’1’) then
RAM(conv_integer(addra)) <= di;
end if;
read_addra <= addra;
read_addrb <= addrb;
end if;
end if;
end process;
doa <= RAM(conv_integer(read_addra));
dob <= RAM(conv_integer(read_addrb));
end syn;
Ver
ilog Fo
llow
ing
is th
e V
erilo
g co
de
for
a du
al-p
ort R
AM
wit
h on
e gl
obal
ena
ble
cont
rolli
ng b
oth
port
s. module raminfr (clk, en, we, addra, addrb, di, doa, dob);
input clk;
input en;
input we;
input [4:0] addra;
input [4:0] addrb;
input [3:0] di;
output [3:0] doa;
output [3:0] dob;
reg [3:0] ram [31:0];
reg [4:0] read_addra;
reg [4:0] read_addrb;
always @(posedge clk)
begin
if (ena)
begin
if (wea)
ram[addra] <= di;
read_aaddra <= addra;
read_aaddrb <= addrb;
end
end
assign doa = ram[read_addra];
assign dob = ram[read_addrb];
endmodule
146
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Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR Dua
l-Por
t RA
M w
ith E
nabl
e on
Eac
h P
ort
The
follo
win
g d
escr
ipti
ons
are
dire
ctly
map
pabl
e on
to B
lock
RA
M, a
s sh
own
in th
e fo
llow
ing
figu
re.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a du
al-p
ort R
AM
wit
h en
able
on
each
por
t.
IO P
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
ena
Prim
ary
Glo
bal E
nabl
e (A
ctiv
e H
igh)
enb
Dua
l Glo
bal E
nabl
e (A
ctiv
e H
igh)
wea
Prim
ary
Sync
hron
ous
Wri
te E
nabl
e (A
ctiv
e H
igh)
add
raW
rite
Ad
dre
ss/
Pri
mar
y R
ead
Ad
dre
ss
add
rbD
ual
Rea
d A
ddre
ss
dia
Prim
ary
Dat
a In
put
doa
Prim
ary
Out
put P
ort
dob
Dua
l Ou
tput
Por
t
X94
76
AD
DR
B
DO
B
DO
AA
DD
RA
EN
A
EN
B
DIA
WE
A
CLK
Blo
ckR
AM
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m14
7
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a d
ual-
port
RA
M w
ith
enab
le o
n ea
ch p
ort.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port (clka
: in std_logic;
clkb
: in std_logic;
wea
: in std_logic;
addra
: in std_logic_vector(4 downto 0);
addrb
: in std_logic_vector(4 downto 0);
dia
: in std_logic_vector(3 downto 0);
doa
: out std_logic_vector(3 downto 0);
dob
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
signal read_addra
: std_logic_vector(4 downto 0);
signal read_addrb
: std_logic_vector(4 downto 0);
begin
process (clka)
begin
if (clka’event and clka = ’1’) then
if (wea = ’1’) then
RAM(conv_integer(addra)) <= dia;
end if;
read_addra <= addra;
end if;
end process;
process (clkb)
begin
if (clkb’event and clkb = ’1’) then
read_addrb <= addrb;
end if;
end process;
doa <= RAM(conv_integer(read_addra));
dob <= RAM(conv_integer(read_addrb));
end syn;
148
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pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a d
ual-
port
RA
M w
ith
enab
le o
n ea
ch p
ort.
module raminfr (clka, clkb, wea, addra, addrb, dia, doa, dob);
input clka;
input clkb;
input wea;
input [4:0] addra;
input [4:0] addrb;
input [3:0] dia;
output [3:0] doa;
output [3:0] dob;
reg [3:0] RAM [31:0];
reg [4:0] addr_rega;
reg [4:0] addr_regb;
always @(posedge clka)
begin
if (wea == 1’b1)
RAM[addra] <= dia;
addr_rega <= addra;
end
always @(posedge clkb)
begin
addr_regb <= addrb;
end
assign doa = RAM[addr_rega];
assign dob = RAM[addr_regb];
endmodule
Dua
l-Por
t Blo
ck R
AM
with
Diff
eren
t Clo
cks
The
follo
win
g ex
ampl
e sh
ows
whe
re th
e tw
o cl
ocks
are
use
d.
X97
99
DIA
WE
A
DO
A
DO
B
AD
DR
A
AD
DR
B
CLK
A
CLK
B
BLO
CK
RA
M
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m14
9
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a d
ual-
port
RA
M w
ith
dif
fere
nt c
lock
s.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a d
ual-
port
RA
M w
ith
dif
fere
nt c
lock
s.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clka
: in std_logic;
clkb
: in std_logic;
wea
: in std_logic;
addra
: in std_logic_vector(4 downto 0);
addrb
: in std_logic_vector(4 downto 0);
dia
: in std_logic_vector(3 downto 0);
doa
: out std_logic_vector(3 downto 0);
dob
: out std_logic_vector(3 downto 0)
);
end raminfr;
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
signal read_addra
: std_logic_vector(4 downto 0);
signal read_addrb
: std_logic_vector(4 downto 0);
begin
process (clka)
begin
if (clka’event and clka = ’1’) then
if (wea = ’1’) then
RAM(conv_integer(addra)) <= dia;
end if;
read_addra <= addra;
end if;
end process;
IO P
ins
Des
crip
tio
n
clka
Pos
itiv
e-E
dge
Clo
ck
clkb
Pos
itiv
e-E
dge
Clo
ck
wea
Prim
ary
Sync
hron
ous
Wri
te E
nabl
e (A
ctiv
e H
igh)
add
raW
rite
Ad
dre
ss/
Pri
mar
y R
ead
Ad
dre
ss
add
rbD
ual
Rea
d A
ddre
ss
dia
Prim
ary
Dat
a In
put
doa
Prim
ary
Out
put P
ort
dob
Dua
l Ou
tput
Por
t
150
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uid
e1-
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pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
process (clkb)
begin
if (clkb’event and clkb = ’1’) then
read_addrb <= addrb;
end if;
process;
doa <= RAM(read_addra);
dob <= RAM(read_addrb);
end syn;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a d
ual-
port
RA
M w
ith
dif
fere
nt c
lock
s.
module raminfr (clka, clkb, wea, addra, addrb, dia, doa, dob);
input clka;
input clkb;
input wea;
input [4:0] addra;
input [4:0] addrb;
input [3:0] dia;
output [3:0] doa;
output [3:0] dob;
reg [3:0] RAM [31:0];
reg [4:0] read_addra;
reg [4:0] read_addrb;
always @(posedge clka)
begin
if (wea == 1’b1)
RAM[addra] <= dia;
addr_rega <= addra;
end
always @(posedge clkb)
begin
addr_regb <= addrb;
end
assign doa = RAM[addr_rega];
assign dob = RAM[addr_regb];
endmodule
Mul
tiple
-Por
t RA
M D
escr
iptio
nsX
ST c
an id
enti
fy R
AM
des
crip
tion
s w
ith
two
or m
ore
read
por
ts th
at a
cces
s th
e R
AM
co
nten
ts a
t ad
dre
sses
dif
fere
nt fr
om th
e w
rite
ad
dre
ss. H
owev
er, t
here
can
onl
y be
one
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m15
1
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
wri
te p
ort.
XST
impl
emen
ts th
e fo
llow
ing
des
crip
tion
s by
repl
icat
ing
the
RA
M c
onte
nts
for
each
out
put
por
t, as
sho
wn:
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a m
ulti
ple-
port
RA
M.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a m
ulti
ple-
port
RA
M.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity raminfr is
port ( clk
: in std_logic;
we
: in std_logic;
wa
: in std_logic_vector(4 downto 0);
ra1
: in std_logic_vector(4 downto 0);
ra2
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do1
: out std_logic_vector(3 downto 0);
do2
: out std_logic_vector(3 downto 0)
);
end raminfr;
IO p
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
we
Sync
hron
ous
Wri
te E
nabl
e (A
ctiv
e H
igh)
wa
Wri
te A
dd
ress
ra1
Rea
d A
dd
ress
of t
he F
irst
RA
M
ra2
Rea
d A
dd
ress
of t
he S
econ
d R
AM
di
Dat
a In
put
do1
Firs
t RA
M O
utpu
t Por
t
do2
Seco
nd R
AM
Ou
tpu
t Por
t
X89
83
RA
M 1
DO
1D
PO
SP
OW
EDI
WA
A
RA
1D
PR
A
CLK
RA
M 2
DO
2D
PO
SP
OW
EDI
WA
A
RA
2D
PR
A
CLK
152
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ST
Use
r G
uid
e1-
800-
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7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
architecture syn of raminfr is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal RAM
: ram_type;
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (we = ’1’) then
RAM(conv_integer(wa)) <= di;
end if;
end if;
end process;
do1 <= RAM(conv_integer(ra1));
do2 <= RAM(conv_integer(ra2));
end syn;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
a m
ult
iple
-por
t RA
M.
module raminfr (clk, we, wa, ra1, ra2, di, do1, do2);
input clk;
input we;
input [4:0] wa;
input [4:0] ra1;
input [4:0] ra2;
input [3:0] di;
output [3:0] do1;
output [3:0] do2;
reg [3:0] ram [31:0];
always @(posedge clk)
begin
if (we)
ram[wa] <= di;
end
assign do1 = ram[ra1];
assign do2 = ram[ra2];
endmodule
Blo
ck R
AM
with
Res
etX
ST s
upp
orts
blo
ck R
AM
wit
h re
set o
n th
e d
ata
outp
uts,
as
offe
red
wit
h V
irte
x™,
Vir
tex-
II™
and
rela
ted
blo
ck R
AM
reso
urce
s. O
pti
onal
ly, y
ou c
an in
clu
de a
syn
chro
nous
ly
cont
rolle
d in
itia
lizat
ion
of th
e R
AM
dat
a ou
tpu
ts.
Blo
ck R
AM
wit
h th
e fo
llow
ing
sync
hron
izat
ion
mod
es c
an h
ave
rese
tabl
e d
ata
port
s.
•R
ead
-Fir
st B
lock
RA
M w
ith
Res
et
•W
rite
-Fir
st B
lock
RA
M w
ith
Res
et
•N
o-C
hang
e B
lock
RA
M w
ith
Res
et
•R
egis
tere
d R
OM
wit
h R
eset
•Su
ppor
ted
Du
al-P
ort T
empl
ates
No
te:
Bec
ause
XS
T d
oes
not s
uppo
rt b
lock
RA
Ms
with
dua
l-writ
e in
a d
ual-r
ead
bloc
k R
AM
de
scrip
tion,
bot
h da
ta o
utpu
ts m
ay b
e re
set,
but t
he v
ario
us re
ad-w
rite
sync
hron
izat
ions
are
onl
y al
low
ed fo
r th
e pr
imar
y da
ta o
utpu
t. T
he d
ual o
utpu
t may
onl
y be
use
d in
rea
d-fir
st m
ode.
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m15
3
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
The
follo
win
g ex
ampl
e sh
ows
a R
ead
-Fir
st B
lock
RA
M w
ith
rese
t.
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a bl
ock
RA
M w
ith
rese
t.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
a re
ad-f
irst
RA
M w
ith
rese
t.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ramrst is
port ( clk
: in std_logic;
en
: in std_logic;
we
: in std_logic;
rst
: in std_logic;
addr
: in std_logic_vector(4 downto 0);
di
: in std_logic_vector(3 downto 0);
do
: out std_logic_vector(3 downto 0)
);
end ramrst;
IO p
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
enG
loba
l Ena
ble
we
Wri
te E
nabl
e (a
ctiv
e H
igh)
add
rR
ead
/Wri
te A
dd
ress
rst
Res
et fo
r d
ata
outp
ut
di
Dat
a In
put
do
RA
M O
utpu
t Por
t
X10
019
EN
DO
AD
DR
WE DI
CLK
RS
T
Blo
ck R
AM
with
Res
et
154
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w.x
ilin
x.co
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ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
architecture syn of ramrst is
type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0);
signal ram
: ram_type;
begin
process (clk)
begin
if clk’event and clk = ’1’ then
if en = ’1’ then
-- optional enable
if we = ’1’ then
-- write enable
ram(conv_integer(addr)) <= di;
end if;
if rst = ’1’ then
-- optional reset
do <= (others => ’0’);
else do <= ram(conv_integer(addr))
;end if;
end if;
end if;
end process;
end syn;
Ver
ilog
Tem
plat
e
Follo
win
g is
the
Veri
log
cod
e fo
r a
read
-fir
st R
AM
wit
h re
set.
module raminfr (clk, en, we, rst, addr, di, do);
input clk;
input en;
input we;
input rst;
input [4:0] addr;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [3:0] do;
always @(posedge clk)
begin
if en // optional enable
begin
if we // write enable
ram(addr) <= di;
if rst // optional reset
do <= reset_value;
else do <= ram(addr);
end
end
end module
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m15
5
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
Initi
aliz
ing
Blo
ck R
AM
VH
DL B
lock
RA
M in
itia
l con
tent
s ca
n be
spe
cifi
ed b
y in
itia
lizat
ion
of th
e si
gnal
des
crib
ing
the
mem
ory
arra
y in
you
r V
HD
L c
ode
as in
the
follo
win
g ex
ampl
e:
...
type ram_type is array (0 to 63) of std_logic_vector(19 downto 0);
signal RAM
: ram_type:=
( X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A",
X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002",
X"08201", X"00500", X"04001", X"02500", X"00340", X"00241",
X"04002", X"08300", X"08201", X"00500", X"08101", X"00602",
X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021",
X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B",
X"00900", X"00302", X"00102", X"04002", X"00900", X"08201",
X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",
X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",
X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",
X"0030D", X"02341", X"08201", X"0400D"
);
...
process (clk)
begin
if rising_edge(clk) then
if we = ’1’ then
RAM(conv_integer(a)) <= di;
end if;
ra <= a;
end if;
end process;
...
do <= RAM(conv_integer(ra));
The
RA
M in
itia
l con
tent
s ca
n be
spe
cifi
ed in
hex
adec
imal
, as
in th
e pr
evio
us e
xam
ple,
or i
n bi
nary
as
show
n in
the
follo
win
g ex
amp
le:
...
type ram_type is array (0 to SIZE-1) of std_logic_vector(15 downto 0);
signal RAM
: ram_type:=
( "0111100100000101",
"0000010110111101",
"1100001101010000",
...
"0000100101110011"
);
...
Ver
ilog XST
doe
s no
t sup
port
blo
ck R
AM
init
ializ
atio
n in
Ver
ilog.
156
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Lim
itatio
ns
•In
itia
lizat
ion
is o
nly
valid
for
bloc
k R
AM
res
ourc
es. I
f you
att
empt
to in
itia
lize
dis
trib
uted
RA
M, X
ST ig
nore
s th
e in
itia
lizat
ion,
and
issu
es a
war
ning
mes
sage
.
•In
itia
lizat
ion
is o
nly
valid
for
sing
le-p
ort R
AM
. If y
ou a
ttem
pt to
init
ializ
e m
ult
iple
-po
rt R
AM
, XST
igno
res
the
init
ializ
atio
n, a
nd is
sues
a w
arni
ng m
essa
ge.
•In
itia
lizat
ion
of in
ferr
ed R
AM
s fr
om R
TL
cod
e is
not
sup
port
ed v
ia IN
IT c
onst
rain
ts.
Use
of I
NIT
con
stra
ints
is o
nly
supp
orte
d if
RA
M p
rim
itiv
es a
re d
irec
tly
inst
anti
ated
fr
om th
e U
NIS
IM li
brar
y.
RO
Ms
Usi
ng B
lock
RA
M R
esou
rces
XST
can
use
blo
ck R
AM
res
ourc
es to
impl
emen
t RO
Ms
wit
h sy
nchr
onou
s ou
tput
s or
ad
dre
ss in
puts
. The
se R
OM
s ar
e im
plem
ent a
s si
ngle
-por
t blo
ck R
AM
s. T
he u
se o
f blo
ck
RA
M r
esou
rces
to im
plem
ent R
OM
s is
con
trol
led
by
the
RO
M_S
TY
LE
con
stra
int.
Ple
ase
see
Cha
pte
r 5, “
Des
ign
Con
stra
ints
” fo
r det
ails
abo
ut th
e R
OM
_SY
TL
E a
ttri
bute
. Ple
ase
see
Cha
pter
3, “
FPG
A O
ptim
izat
ion”
for
det
ails
on
RO
M im
plem
enta
tion
.
Her
e is
a li
st o
f VH
DL
/V
erilo
g te
mpl
ates
des
crib
ed b
elow
.
•R
OM
wit
h re
gist
ered
ou
tput
•R
OM
wit
h re
gist
ered
add
ress
The
follo
win
g ta
ble
show
s pi
n d
escr
ipti
ons
for
a re
gist
ered
RO
M.
VH
DL Fo
llow
ing
is th
e re
com
men
ded
VH
DL
cod
e fo
r a
RO
M w
ith
regi
ster
ed o
utpu
t.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rominfr is
port ( clk
: in std_logic;
en
: in std_logic;
addr
: in std_logic_vector(4 downto 0);
data
: out std_logic_vector(3 downto 0)
);
end rominfr;
IO P
ins
Des
crip
tio
n
clk
Posi
tive
-Ed
ge C
lock
enSy
nchr
onou
s E
nabl
e (a
ctiv
e H
igh)
add
rR
ead
Ad
dre
ss
dat
aD
ata
Out
put
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m15
7
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
architecture syn of rominfr is
type rom_type is array (31 downto 0) of std_logic_vector (3 downto 0);
constant ROM
: rom_type
:=
("0001","0010","0011","0100","0101","0110","0111","1000","1001","1010"
,"1011","1100","1101","1110","1111","0001","0010","0011","0100","0101"
,"0110","0111","1000","1001","1010","1011","1100","1101","1110","1111"
);
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (en = ’1’) then
data <= ROM(conv_integer(addr);
end if;
end if;
end process;
end syn;
Follo
win
g is
alt
erna
te V
HD
L c
ode
for
a R
OM
wit
h re
gist
ered
out
put.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rominfr is
port ( clk
: in std_logic;
en
: in std_logic;
addr
: in std_logic_vector(4 downto 0);
data
: out std_logic_vector(3 downto 0)
);
end rominfr;
architecture syn of rominfr is
type rom_type is array (31 downto 0) of std_logic_vector (3 downto 0);
constant ROM
: rom_type
:=
("0001","0010","0011","0100","0101","0110","0111","1000","1001","1010"
,"1011","1100","1101","1110","1111","0001","0010","0011","0100","0101"
,"0110","0111","1000","1001","1010","1011","1100","1101","1110","1111"
); signal rdata
: std_logic_vector(3 downto 0);
begin
rdata <= ROM(conv_integer(addr);
process (clk)
begin
if (clk’event and clk = ’1’) then
if (en = ’1’) then
data <= rdata;
end if;
end if;
end process;
end syn;
158
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ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Follo
win
g is
VH
DL
cod
e fo
r a
RO
M w
ith
regi
ster
ed a
dd
ress
.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rominfr is
port ( clk
: in std_logic;
en
: in std_logic;
addr
: in std_logic_vector(4 downto 0);
data
: out std_logic_vector(3 downto 0)
);
end rominfr;
architecture syn of rominfr is
type rom_type is array (31 downto 0) of std_logic_vector (3 downto 0);
constant ROM
: rom_type
:=
("0001","0010","0011","0100","0101","0110","0111","1000","1001","1010"
,"1011","1100","1101","1110","1111","0001","0010","0011","0100","0101"
,"0110","0111","1000","1001","1010","1011","1100","1101","1110","1111
);signal raddr
: std_logic_vector(4 downto 0);
begin
process (clk)
begin
if (clk’event and clk = ’1’) then
if (en = ’1’) then
raddr <= addr;
end if;
end if;
end process;
data <= ROM(conv_integer(raddr);
end syn;
Ver
ilog Fo
llow
ing
is V
erilo
g co
de
for
a R
OM
wit
h re
gist
ered
out
put.
module rominfr (clk, en, addr, data);
input clk;
input en;
input [4:0] addr;
output [3:0] data;
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m15
9
1-80
0-25
5-77
78
RA
Ms/
RO
Ms
R
always @(posedge clk) begin
if (en)
case(addr)
4’b0000: data = 4’b0010;
4’b0001: data = 4’b0010;
4’b0010: data = 4’b1110;
4’b0011: data = 4’b0010;
4’b0100: data = 4’b0100;
4’b0101: data = 4’b1010;
4’b0110: data = 4’b1100;
4’b0111: data = 4’b0000;
4’b1000: data = 4’b1010;
4’b1001: data = 4’b0010;
4’b1010: data = 4’b1110;
4’b1011: data = 4’b0010;
4’b1100: data = 4’b0100;
4’b1101: data = 4’b1010;
4’b1110: data = 4’b1100;
4’b1111: data = 4’b0000;
default: data = 4’bXXXX;
endcase
end
endmodule
Follo
win
g is
Ver
ilog
cod
e fo
r a
RO
M w
ith
regi
ster
ed a
dd
ress
.
module rominfr (clk, en, addr, data);
input clk;
input en;
input
[4:0] addr;
output
[3:0] data;
reg
[4:0] raddr;
always @(posedge clk) begin
if (en)
raddr = addr;
end
always @(raddr) begin
if (en)
case(raddr)
4’b0000: data = 4’b0010;
4’b0001: data = 4’b0010;
4’b0010: data = 4’b1110;
4’b0011: data = 4’b0010;
4’b0100: data = 4’b0100;
4’b0101: data = 4’b1010;
4’b0110: data = 4’b1100;
4’b0111: data = 4’b0000;
4’b1000: data = 4’b1010;
4’b1001: data = 4’b0010;
4’b1010: data = 4’b1110;
4’b1011: data = 4’b0010;
4’b1100: data = 4’b0100;
4’b1101: data = 4’b1010;
4’b1110: data = 4’b1100;
4’b1111: data = 4’b0000;
default: data = 4’bXXXX;
endcase
end
endmodule
160
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Sta
te M
ach
ine X
ST p
ropo
ses
a la
rge
set o
f tem
plat
es to
des
crib
e Fi
nite
Sta
te M
achi
nes
(FSM
s). B
y d
efau
lt,
XST
trie
s to
dis
ting
uish
FSM
s fr
om V
HD
L/V
erilo
g co
de,
and
app
ly s
ever
al s
tate
enc
odin
g te
chni
ques
(it c
an r
e-en
cod
e th
e us
er’s
init
ial e
ncod
ing)
to g
et b
ette
r pe
rfor
man
ce o
r le
ss
area
. How
ever
, you
can
dis
able
FSM
ext
ract
ion
by u
sing
the
FSM
_EX
TR
AC
T d
esig
n co
nstr
aint
.
Ple
ase
note
that
XST
can
han
dle
onl
y sy
nchr
onou
s st
ate
mac
hine
s.
The
re a
re m
any
way
s to
des
crib
e FS
Ms.
A tr
adit
iona
l FSM
rep
rese
ntat
ion
inco
rpor
ates
M
ealy
and
Moo
re m
achi
nes,
as
in th
e fo
llow
ing
figu
re. P
leas
e no
te th
at X
ST s
uppo
rts
both
of
thes
e m
odel
s:
For
HD
L, p
roce
ss (V
HD
L) a
nd a
lway
s bl
ocks
(Ver
ilog)
are
the
mos
t su
itab
le w
ays
for
des
crib
ing
FSM
s. (F
or d
escr
ipti
on c
onve
nien
ce X
ilinx
® u
ses
"pro
cess
" to
ref
er to
bot
h:
VH
DL
pro
cess
es a
nd V
erilo
g al
way
s bl
ocks
.)
You
may
hav
e se
vera
l pro
cess
es (1
, 2 o
r 3)
in y
our
des
crip
tion
, dep
end
ing
upon
how
you
co
nsid
er a
nd d
ecom
pose
the
dif
fere
nt p
arts
of t
he p
rece
ding
mod
el. F
ollo
win
g is
an
exam
ple
of th
e M
oore
Mac
hine
wit
h A
sync
hron
ous
Res
et, “
RE
SET
”.
•4
stat
es: s
1, s
2, s
3, s
4
•5
tran
siti
ons
•1
inpu
t: "x
1"
•1
outp
ut: "
outp
"
Thi
s m
odel
is r
epre
sent
ed b
y th
e fo
llow
ing
bubb
le d
iagr
am:
X89
93
Nex
tS
tate
Fun
ctio
n
Out
put
Fun
ctio
nS
tate
Reg
iste
r
RE
SE
T
Out
puts
Inpu
tsC
LOC
K
Onl
y fo
r M
ealy
Mac
hine
S1
S2
S3
S4
RE
SE
T
x1x1
outp
='1
'ou
tp=
'0'
outp
='1
'
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m16
1
1-80
0-25
5-77
78
Sta
te M
ach
ine
R
FS
M w
ith 1
Pro
cess
Plea
se n
ote,
in th
is e
xam
ple
outp
ut s
igna
l "ou
tp"
is a
reg
iste
r.
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
an F
SM w
ith
a si
ngle
pro
cess
.
library IEEE;
use IEEE.std_logic_1164.all;
entity fsm is
port ( clk, reset, x1
: IN std_logic;
outp
: OUT std_logic
);
end entity;
architecture beh1 of fsm is
type state_type is (s1,s2,s3,s4);
signal state: state_type;
begin process (clk, reset)
begin
if (reset =’1’) then
state <= s1;
outp <= ’1’;
elsif (clk=’1’ and clk’event) then
case state is
when s1 =>
if x1=’1’ then
state <= s2;
else state <= s3;
end if;
outp <= ’1’;
when s2 => state <= s4; outp <= ’1’;
when s3 => state <= s4; outp <= ’0’;
when s4 => state <= s1; outp <= ’0’;
end case;
end if;
end process;
end beh1;
162
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
an F
SM w
ith
a si
ngle
pro
cess
.
module fsm (clk, reset, x1, outp);
input clk, reset, x1;
output outp;
reg outp;
reg [1:0] state;
parameter s1 = 2’b00; parameter s2 = 2’b01;
parameter s3 = 2’b10; parameter s4 = 2’b11;
always@(posedge clk or posedge reset)
begin
if (reset)
begin
state = s1; outp = 1’b1;
end
else
begin
case (state)
s1: begin
if (x1 == 1’b1)
state = s2;
else
state = s3;
outp = 1’b1;
end
s2: begin
state = s4; outp = 1’b1;
end
s3: begin
state = s4; outp = 1’b0;
end
s4: begin
state = s1; outp = 1’b0;
end
endcase
end
end
endmodule
FS
M w
ith 2
Pro
cess
esTo
elim
inat
e a
regi
ster
from
the
"out
puts
", y
ou c
an r
emov
e al
l ass
ignm
ents
“ou
tp <
=…”
from
the
Clo
ck s
ynch
roni
zati
on s
ecti
on.
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m16
3
1-80
0-25
5-77
78
Sta
te M
ach
ine
R
Thi
s ca
n be
don
e by
intr
oduc
ing
two
proc
esse
s as
sho
wn
in th
e fo
llow
ing
figu
re.
VH
DL Fo
llow
ing
is V
HD
L c
ode
for
an F
SM w
ith
two
proc
esse
s.
library IEEE;
use IEEE.std_logic_1164.all;
entity fsm is
port ( clk, reset, x1
: IN std_logic;
outp
: OUT std_logic
);
end entity;
architecture beh1 of fsm is
type state_type is (s1,s2,s3,s4);
signal state: state_type;
begin
process1: process (clk, reset)
begin
if (reset =’1’) then
state <=s1;
elsif (clk=’1’ and clk’Event) then
case state is
when s1 =>
if x1=’1’ then
state <= s2;
else
state <= s3;
end if;
when s2 => state <= s4;
when s3 => state <= s4;
when s4 => state <= s1;
end case;
end if;
end process process1;
X89
86P
RO
CE
SS
1P
RO
CE
SS
2
Nex
tS
tate
Func
tion
Out
put
Func
tion
Sta
teR
egis
ter
RE
SE
T
Out
puts
Inpu
tsC
LOC
K
Onl
y fo
r Mea
ly M
achi
ne
164
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r G
uid
e1-
800-
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7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
process2
: process (state)
begin
case state is
when s1 => outp <= ’1’;
when s2 => outp <= ’1’;
when s3 => outp <= ’0’;
when s4 => outp <= ’0’;
end case;
end process process2;
end beh1;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
an F
SM w
ith
two
proc
esse
s.
module fsm (clk, reset, x1, outp);
input clk, reset, x1;
output outp;
reg outp;
reg [1:0] state;
parameter s1 = 2’b00; parameter s2 = 2’b01;
parameter s3 = 2’b10; parameter s4 = 2’b11;
always @(posedge clk or posedge reset)
begin
if (reset)
state = s1;
else begin
case (state)
s1: if (x1 == 1’b1)
state = s2;
else
state = s3;
s2: state = s4;
s3: state = s4;
s4: state = s1;
endcase
end
end
always @(state)
begin
case (state)
s1: outp = 1’b1;
s2: outp = 1’b1;
s3: outp = 1’b0;
s4: outp = 1’b0;
endcase
end
endmodule
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m16
5
1-80
0-25
5-77
78
Sta
te M
ach
ine
R
FS
M w
ith 3
Pro
cess
esYo
u ca
n al
so s
epar
ate
the
NEX
T S
tate
func
tion
from
the
stat
e re
gist
er:
Sepa
rati
ng th
e N
EX
T S
tate
func
tion
from
the
stat
e re
gist
er p
rovi
des
the
follo
win
g d
escr
ipti
on:
VH
DL Fo
llow
ing
is th
e V
HD
L c
ode
for
an F
SM w
ith
thre
e pr
oces
ses.
library IEEE;
use IEEE.std_logic_1164.all;
entity fsm is
port ( clk, reset, x1
: IN std_logic;
outp
: OUT std_logic
);
end entity;
architecture beh1 of fsm is
type state_type is (s1,s2,s3,s4);
signal state, next_state: state_type;
begin
process1: process (clk, reset)
begin if (reset =’1’) then
state <= s1;
elsif (clk = ’1’ and clk’Event) then
state <= next_state;
end if;
end process process1;
X89
87P
RO
CE
SS
1P
RO
CE
SS
3P
RO
CE
SS
2
Nex
tS
tate
Fun
ctio
n
Out
put
Fun
ctio
nS
tate
Reg
iste
r
RE
SE
T
Out
puts
Inpu
tsC
LOC
K
Onl
y fo
r M
ealy
Mac
hine
166
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w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
process2
: process (state, x1)
begin
case state is
when s1 =>
if x1=’1’ then
next_state <= s2;
else next_state <= s3;
end if;
when s2 => next_state <= s4;
when s3 => next_state <= s4;
when s4 => next_state <= s1;
end case;
end process process2;
process3
: process (state)
begin
case state is
when s1 => outp <= ’1’;
when s2 => outp <= ’1’;
when s3 => outp <= ’0’;
when s4 => outp <= ’0’;
end case;
end process process3;
end beh1;
Ver
ilog Fo
llow
ing
is th
e Ve
rilo
g co
de
for
an F
SM w
ith
thre
e pr
oces
ses.
module fsm (clk, reset, x1, outp);
input clk, reset, x1;
output outp;
reg outp;
reg [1:0] state;
reg [1:0] next_state;
parameter s1 = 2’b00; parameter s2 = 2’b01;
parameter s3 = 2’b10; parameter s4 = 2’b11;
always @(posedge clk or posedge reset)
begin
if (reset)
state = s1;
else
state = next_state;
end
always @(state or x1)
begin case (state)
s1:if (x1 == 1’b1)
next_state = s2;
else
next_state = s3;
s2: next_state = s4;
s3: next_state = s4;
s4: next_state = s1;
endcase
end
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m16
7
1-80
0-25
5-77
78
Sta
te M
ach
ine
R
always @(state)
begin
case (state)
s1: outp = 1’b1;
s2: outp = 1’b1;
s3: outp = 1’b0;
s4: outp = 1’b0;
endcase
end
endmodule
Sta
te R
egis
ters
Stat
e re
gist
ers
mus
t be
init
ializ
ed w
ith
an a
sync
hron
ous
or s
ynch
rono
us s
igna
l. X
ST d
oes
not s
uppo
rt F
SM w
itho
ut in
itia
lizat
ion
sign
als.
Ple
ase
refe
r to
“R
egis
ters
” in
this
cha
pter
fo
r te
mpl
ates
on
how
to w
rite
Asy
nchr
onou
s an
d S
ynch
rono
us in
itia
lizat
ion
sign
als.
In V
HD
L, t
he ty
pe o
f a s
tate
reg
iste
r ca
n be
a d
iffe
rent
type
: int
eger
, bit
_vec
tor,
std
_log
ic_v
ecto
r, fo
r ex
ampl
e. B
ut i
t is
com
mon
and
con
veni
ent t
o d
efin
e an
enu
mer
ated
ty
pe c
onta
inin
g al
l pos
sibl
e st
ate
valu
es a
nd to
dec
lare
you
r st
ate
regi
ster
wit
h th
at ty
pe.
In V
erilo
g, th
e ty
pe o
f sta
te r
egis
ter
can
be a
n in
tege
r or
a s
et o
f def
ined
par
amet
ers.
In th
e fo
llow
ing
Ver
ilog
exam
ples
the
stat
e as
sign
men
ts c
ould
hav
e be
en m
ade
like
this
:
parameter [3:0]
s1 = 4’b0001,
s2 = 4’b0010,
s3 = 4’b0100,
s4 = 4’b1000;
reg [3:0] state;
The
se p
aram
eter
s ca
n be
mod
ifie
d to
rep
rese
nt d
iffe
rent
sta
te e
ncod
ing
sche
mes
.
Nex
t Sta
te E
quat
ions
Nex
t sta
te e
quat
ions
can
be
des
crib
ed d
irec
tly
in th
e se
quen
tial
pro
cess
or
in a
dis
tinc
t co
mbi
nati
onal
pro
cess
. The
sim
ples
t tem
plat
e is
bas
ed o
n a
Cas
e st
atem
ent.
If u
sing
a
sepa
rate
com
bina
tion
al p
roce
ss, i
ts s
ensi
tivi
ty li
st s
hou
ld c
onta
in th
e st
ate
sign
al a
nd a
ll FS
M in
puts
.
Unr
each
able
Sta
tes
XST
can
det
ect u
nrea
chab
le s
tate
s in
an
FSM
. It l
ists
them
in th
e lo
g fi
le in
the
HD
L
Synt
hesi
s st
ep.
FS
M O
utpu
tsN
on-r
egis
tere
d o
utpu
ts a
re d
escr
ibed
eit
her
in th
e co
mbi
nati
onal
pro
cess
or
in c
oncu
rren
t as
sign
men
ts. R
egis
tere
d o
utp
uts
mus
t be
assi
gned
wit
hin
the
sequ
enti
al p
roce
ss.
FS
M In
puts R
egis
tere
d in
puts
are
des
crib
ed u
sing
inte
rnal
sig
nals
, whi
ch a
re a
ssig
ned
in th
e se
quen
tial
pr
oces
s.
168
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR Sta
te E
ncod
ing
Tech
niqu
esX
ST s
upp
orts
the
follo
win
g st
ate
enco
din
g te
chni
ques
.
•A
uto
•O
ne-H
ot
•G
ray
•C
ompa
ct
•Jo
hnso
n
•Se
quen
tial
•U
ser
Aut
o
In th
is m
ode,
XST
trie
s to
sel
ect t
he b
est s
uite
d e
ncod
ing
algo
rith
m fo
r ea
ch F
SM.
One
-Hot
One
-hot
enc
odin
g is
the
def
ault
enc
odin
g sc
hem
e. It
s pr
inci
ple
is to
ass
ocia
te o
ne c
ode
bit
and
als
o on
e fl
ip-f
lop
to e
ach
stat
e. A
t a g
iven
clo
ck c
ycle
dur
ing
oper
atio
n, o
ne a
nd o
nly
one
stat
e va
riab
le is
ass
erte
d. O
nly
two
stat
e va
riab
les
togg
le d
urin
g a
tran
siti
on b
etw
een
two
stat
es. O
ne-h
ot e
ncod
ing
is v
ery
appr
opri
ate
wit
h m
ost F
PG
A ta
rget
s w
here
a la
rge
num
ber
of fl
ip-f
lops
are
ava
ilabl
e. It
is a
lso
a go
od a
lter
nati
ve w
hen
tryi
ng to
opt
imiz
e sp
eed
or
to r
edu
ce p
ower
dis
sipa
tion
.
Gra
y Gra
y en
cod
ing
guar
ante
es th
at o
nly
one
stat
e va
riab
le s
wit
ches
bet
wee
n tw
o co
nsec
utiv
e st
ates
. It i
s ap
prop
riat
e fo
r co
ntro
llers
exh
ibit
ing
long
pat
hs w
itho
ut b
ranc
hing
. In
add
itio
n, th
is c
odin
g te
chni
que
min
imiz
es h
azar
ds
and
glit
ches
. Ver
y go
od r
esul
ts c
an b
e ob
tain
ed w
hen
impl
emen
ting
the
stat
e re
gist
er w
ith
T fl
ip-f
lops
.
Com
pact
Com
pact
enc
odin
g co
nsis
ts o
f min
imiz
ing
the
num
ber
of s
tate
var
iabl
es a
nd fl
ip-f
lops
. T
his
tech
niqu
e is
bas
ed o
n hy
perc
ube
imm
ersi
on. C
ompa
ct e
ncod
ing
is a
ppro
pria
te w
hen
tryi
ng to
opt
imiz
e ar
ea.
John
son
Lik
e G
ray,
John
son
enco
din
g sh
ows
bene
fits
wit
h st
ate
mac
hine
s co
ntai
ning
long
pat
hs
wit
h no
bra
nchi
ng.
Seq
uent
ial
Sequ
enti
al e
ncod
ing
cons
ists
of i
den
tify
ing
long
pat
hs a
nd a
ppl
ying
suc
cess
ive
rad
ix tw
o co
des
to th
e st
ates
on
thes
e pa
ths.
Nex
t sta
te e
quat
ions
are
min
imiz
ed.
Use
r In th
is m
ode,
XST
use
s or
igin
al e
ncod
ing,
sp
ecif
ied
in th
e H
DL
file
. For
exa
mpl
e, if
you
use
en
umer
ated
type
s fo
r a
stat
e re
gist
er, t
hen
in a
ddi
tion
you
can
use
the
EN
UM
_EN
CO
DIN
G c
onst
rain
t to
assi
gn a
spe
cifi
c bi
nary
val
ue to
eac
h st
ate.
Ple
ase
refe
r to
Cha
pter
5, “
Des
ign
Con
stra
ints
” fo
r m
ore
det
ails
.
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m16
9
1-80
0-25
5-77
78
Sta
te M
ach
ine
R
Log
File
The
XST
log
file
rep
orts
the
full
info
rmat
ion
of r
ecog
nize
d F
SM d
uri
ng th
e M
acro
R
ecog
niti
on s
tep.
Mor
eove
r, if
you
allo
w X
ST to
cho
ose
the
best
enc
odin
g al
gori
thm
for
your
FSM
s, it
rep
orts
the
one
it c
hose
for
each
FSM
.
RA
M-b
ased
FS
M S
ynth
esis
Lar
ge F
SMs
can
be m
ade
mor
e co
mpa
ct a
nd fa
ster
by
impl
emen
ting
them
in th
e bl
ock
RA
M r
esou
rces
pro
vid
ed in
Vir
tex™
and
late
r te
chno
logi
es. Y
ou c
an d
irec
t XST
to u
se
bloc
k R
AM
res
ourc
es fo
r FS
Ms
by u
sing
the
FSM
_ST
YL
E c
onst
rain
t. V
alue
s fo
r FS
M_S
TY
LE
are
lut,
and
bra
m. T
he lu
t opt
ion
is th
e d
efau
lt a
nd it
cau
ses
XST
to m
ap th
e FS
M u
sing
LU
Ts. T
he b
ram
opt
ion
dir
ects
XST
to m
ap th
e FS
M o
nto
bloc
k R
AM
.
In P
roje
ct N
avig
ator
, inv
oke
this
con
stra
int b
y ch
oosi
ng e
ithe
r L
UT
or
Bra
m fr
om th
e d
rop
dow
n lis
t to
the
righ
t of F
SM S
tyle
und
er th
e H
DL
Opt
ions
tab
of th
e P
roce
ss P
rope
rtie
s d
ialo
g bo
x. F
rom
the
com
man
d li
ne, u
se th
e –f
sm_s
tyle
com
man
d li
ne s
wit
ch. Y
ou c
an a
lso
use
the
FSM
_ST
YL
E c
onst
rain
t in
your
HD
L co
de.
See
the
Con
stra
ints
Gui
de fo
r m
ore
info
rmat
ion.
...
Synthesizing Unit <fsm>.
Related source file is state_machines_1.vhd.
Found finite state machine <FSM_0> for signal <state>.
-----------------------------------------------------------
|States
|4
|
|Transitions
|5
|
|Inputs
|1
|
|Outputs
|1
|
|Reset
type
|asynchronous
|
|Encoding
|automatic
|
|State
register
|D
flip-flops
|
----------------------------------------------------------
...Summary:
inferred
1 Finite State Machine(s).
...
Unit <fsm> synthesized.
===============================================================
HDL Synthesis Report
Macro Statistics
#FSMs
:1
#Registers
:1
1-bit
register
:1
================================================================
...
Optimizing FSM <FSM_0> with One-Hot encoding and D flip-flops....
...
170
ww
w.x
ilin
x.co
mX
ST
Use
r G
uid
e1-
800-
255-
7778
Cha
pter
2:
HD
L C
od
ing
Tec
hn
iqu
esR
If it
can
not i
mp
lem
ent a
sta
te m
achi
ne o
n bl
ock
RA
M, X
ST:
•ge
nera
tes
a w
arni
ng m
essa
ge w
ith
the
reas
on fo
r th
e w
arni
ng in
the
Ad
vanc
ed H
DL
Sy
nthe
sis
Step
of t
he lo
g fi
le.
•au
tom
atic
ally
impl
emen
ts th
e st
ate
mac
hine
usi
ng L
UTs
.
For e
xam
ple,
if F
SM h
as a
asy
nchr
onou
s re
set,
it c
anno
t be
impl
emen
ted
usi
ng b
lock
RA
M.
In th
is c
ase
XST
info
rms
the
user
:
Bla
ck B
ox
Su
pp
ort
Your
des
ign
may
con
tain
ED
IF o
r N
GC
file
s ge
nera
ted
by
synt
hesi
s to
ols,
sch
emat
ic
edit
ors
or a
ny o
ther
des
ign
entr
y m
echa
nism
. The
se m
odul
es m
ust b
e in
stan
tiat
ed in
you
r co
de
to b
e co
nnec
ted
to th
e re
st o
f you
r d
esig
n. Y
ou c
an d
o th
is in
XST
by
usin
g bl
ack
box
inst
anti
atio
n in
the
VH
DL
/V
erilo
g co
de.
The
net
list i
s pr
opag
ated
to th
e fi
nal
top-
leve
l net
list w
itho
ut b
eing
pro
cess
ed b
y X
ST. M
oreo
ver,
XST
allo
ws
you
to a
ttac
h sp
ecif
ic c
onst
rain
ts to
thes
e bl
ack
box
inst
anti
atio
ns, w
hich
are
pas
sed
to th
e N
GC
file
.
In a
dd
itio
n, y
ou m
ay h
ave
a d
esig
n bl
ock
for
whi
ch y
ou h
ave
an R
TL
mod
el, a
s w
ell a
s yo
ur o
wn
impl
emen
tati
on o
f thi
s bl
ock
in th
e fo
rm o
f an
ED
IF n
etlis
t. T
he R
TL
mod
el is
on
ly v
alid
for
sim
ulat
ion
purp
oses
, but
by
usin
g th
e B
OX
_TY
PE c
onst
rain
t you
can
dir
ect
XST
to s
kip
synt
hesi
s of
this
RT
L c
ode
and
cre
ate
a bl
ack
box.
The
ED
IF n
etlis
t is
linke
d to
th
e sy
nthe
size
d d
esig
n du
ring
NG
DB
uild
. Ple
ase
see
“Gen
eral
Con
stra
ints
” in
Cha
pter
5fo
r m
ore
info
rmat
ion.
Als
o se
e th
e C
onst
rain
ts G
uide
for
det
ails
.
No
te:
Rem
embe
r th
at o
nce
you
mak
e a
desi
gn a
bla
ck b
ox, e
ach
inst
ance
of t
hat d
esig
n is
a b
lack
bo
x. W
hile
you
can
atta
ch c
onst
rain
ts to
the
inst
ance
, XS
T ig
nore
s an
y co
nstr
aint
atta
ched
to th
e or
igin
al d
esig
n.
Log
File
From
the
flow
poi
nt o
f vie
w, t
he re
cogn
itio
n of
bla
ck b
oxes
in X
ST is
don
e be
fore
the
mac
ro
infe
renc
e pr
oces
s. T
here
fore
the
LO
G fi
le d
iffe
rs fr
om th
e on
e ge
nera
ted
for
othe
r m
acro
s.
...
====================================================================
*Advanced HDL Synthesis
*====================================================================
WARNING:Xst - Unable to fit FSM <FSM_0> in BRAM (reset is
asynchronous).
Selecting encoding for FSM_0
...
Optimizing FSM <FSM_0> on signal <current_state> with one-hot
encoding.
...
...
Analyzing Entity <black_b> (Architecture <archi>).
WARNING:Xst:766 - black_box_1.vhd (Line 15). Generating a BlackBox
for component <my_block>.
Entity <black_b> analyzed. Unit <black_b> generated
....
XS
T U
ser
Gu
ide
ww
w.x
ilin
x.co
m17
1
1-80
0-25
5-77
78
Bla
ck B
ox
Su
pp
ort
R
Rel
ated
Con
stra
ints
XST
has
a B
OX
_TY
PE
con
stra
int t
hat c
an b
e ap
plie
d to
bla
ck b
oxes
. How
ever
, it w
as
intr
odu
ced
esse
ntia
lly fo
r V
irte
x™ P
rim
itiv
e in
stan
tiat
ion
in X
ST. P
leas
e re
ad “
Vir
tex™
Pr
imit
ive
Supp
ort”
in C
hapt
er 3
in b
efor
e us
ing
this
con
stra
int.
VH
DL
Follo
win
g is
the
VH
DL
cod
e fo
r a
blac
k bo
x.
library ieee;
use ieee.std_logic_1164.all;
entity black_b is
port(DI_1, DI_2
: in std_logic;
DOUT
: out std_logic
);
end black_b;
architecture archi of black_b is
component my_block
port (
I1
: in std_logic;
I2
: in std_logic;
O: out std_logic
);
end component;
begin
inst: my_block port map (
I1=>DI_1,
I2=>DI_2,
O=>DOUT
);
end archi;
Ver
ilog
Follo
win
g is
the
Veri
log
cod
e fo
r a
blac
k bo
x.
module my_block (in1, in2, dout);
input in1, in2;
output dout;
endmodule
module black_b (DI_1, DI_2, DOUT);
input DI_1, DI_2;
output DOUT;
my_block inst (
.in1(DI_1),
.in2(DI_2),
.dout(DOUT)
);
endmodule
No
te:
Ple
ase
refe
r to
the
VH
DL/
Ver
ilog
lang
uage
ref
eren
ce m
anua
ls fo
r m
ore
info
rmat
ion
on
com
pone
nt in
stan
tiatio
n.
![XST Corporate Presentation May 2016 AGM FINAL.pptx [Read-Only] · 1 As at May 12, 2016 May 2016 2 San Francisco Sacramento XST Exploration Interests Approximate location of the XST](https://static.fdocuments.in/doc/165x107/5fb6bf9c88c26570130b2f18/xst-corporate-presentation-may-2016-agm-finalpptx-read-only-1-as-at-may-12-2016.jpg)
