forums.xilinx.com · Web viewWARNING:Xst:2838 - Path definition...

****** PlanAhead v14.4 (64-bit) **** Build 222254 by xbuild on Tue Dec 18 05:21:09 MST 2012 ** Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.

INFO: [Common 17-78] Attempting to get a license: PlanAheadINFO: [Common 17-290] Got license for PlanAheadINFO: [Device 21-36] Loading parts and site information from C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data/parts/arch.xmlParsing RTL primitives file [C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]Finished parsing RTL primitives file [C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]WARNING: [Common 17-376] Your XILINX_EDK environment variable is undefined. You may not be able to run some features properly. Please set up your XILINX_EDK environment to get full functionality.source C:/NIFPGA/jobs/vcnPe3C_D7RFefX/planAheadScript.tcl# create_project -part xc5vsx50tff1136-1 Puma20Top C:/NIFPGA/jobs/vcnPe3C_D7RFefX# add_files C:/NIFPGA/jobs/vcnPe3C_D7RFefX# set_property top Puma20Top [get_property srcset [current_run]]# open_rtl_designDesign is defaulting to project part: xc5vsx50tff1136-1Using Verific elaborationParsing VHDL file "C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplifyParsing VHDL file "C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplifyParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiUtilities.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaUtilities.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxp.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxpArithmetic.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpShiftCore.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgOneHot.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFpgaDeviceSpecs.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFloat.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgADPRAM36KUtil.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandlerSlv.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpDynamicShift.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlop.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBase.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinch.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgByteArray.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandler.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixedCore.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpNormalize.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncAsyncInBase.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopSlvResetVal.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopFallingEdge.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ADPRAM36K.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBool.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiLvPrims.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgGray.vhd" into library work

Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommIntConfiguration.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchConfig.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCoerce.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixed.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFixedToFloat.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCoreBase.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPulseSyncBaseWrapper.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM32Bits.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBase.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBoolFallingEdge.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBool.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ResetSync.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgSwitchedChinch.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgInStrmFifoUtil.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDataPackingFifo.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommunicationInterface.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToInteger.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFloatingPoint.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFixedPoint.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCore.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPortReset.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoPtrClockCrossing.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM64Bits.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBool.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimeoutManager.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgStreamStates.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaFifo.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaBoolOp.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNi6587.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchCommunicationInterface.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifoFlags.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmDPRAM.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtractCore.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCoerce.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFlipFlopFifo.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoClearControl.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDoWrite.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmRAMArray.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifoFlags.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBaseResetCross.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBase.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FeedbackNonSctlCore.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SubVICtlOrIndOpt.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Serializer.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_w_opt.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_r_opt.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/RegionalClockBuf.vhd" into library work

Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaFifos.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifo.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpSubtract.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompare.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtract.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareCore.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAddCore.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPopBuffer.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoCountControl.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOpNot.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOp.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005a_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifo.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cIssueCycle.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV_Ack.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FloatingFeedbackGInit.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSlAsyncIn.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSL.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Deserializer.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchInterface.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStreamStateEnableChain.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStateTransitionEnableChain.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentOutputStateHolder.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentInputStateHolder.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentEnableChain.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimingEngine.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopDomainCrosser.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopController.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaIrqRegisters.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpDecrement.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompareToZero.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpAdd.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatDecrement.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareToZero.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompare.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAdd.vhd" into library work

Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaSelect.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderWrite.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderRead.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderRead.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDiRead.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbPowerOf2.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000061_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005f_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005d_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0001.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0000.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructure_62.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587Base.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cReadWrite.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueBase.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/GenerationEngine.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSL.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSLV.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBoolAsyncIn.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchSourceSelect.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputFifoInterface.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputFifoInterface.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/AcquisitionEngine.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNodeOut.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNode.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopCore.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SafeBusCrossing.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgRegister.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaViControlRegister.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaArbiter.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaRegs.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchArbiter.vhd" into library work

Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvDecrement.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompareToZero.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompare.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvAdd.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaTopEnInSyncForExternalClk.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaShiftReg.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegFrameworkShiftReg.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLvJoinNumbers.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaHostAccessibleRegister.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderWrite.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPushPopControl.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltInFifoResetControl.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltinFifoCounter.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbSerializeAccess.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbDelayer.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0000.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructure_149.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0004.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0003.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd" into library work

Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004b_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000049_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000045_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000002c_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0001.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0000.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000001a_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000005_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000003_SequenceFrame.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587CoreSerdes.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueSLV.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSLV.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaIrq.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaFifos.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViSignature.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViControl.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TopEnablePassThru.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/StrmArbiter.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamTcrUpdateController.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamDataReceiver.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmOutputHandler.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalOutput.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalInput.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaCtrlIndRegister.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaClockManagerControl.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbRW.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_181.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_180.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_179.vhd" into library work

Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_178.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000098_TimedLoopDiagram.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000043_TimedLoopDiagram.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000018_TimedLoopDiagram.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000001_TimedLoopDiagram.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587ConnectorSerdes.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InvisibleResholder.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Interface.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn1.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn0.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopEnInIClk.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viBit00.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DiagramReset.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForTopEnablesPortOnResTopEnablePassThru.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForSoftware_Trigger_ctl_12RHFpgaReadPortOnResbushold.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viSoftware_Trigger8.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Gen_Reset7.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viFetch_Length9.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viClear_T2H_DMA_Timeout10.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viBit00.vhd" into library work

Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForMiteIoLikePortOnResInterface.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Xpoint_Switch_Write_ctl_0RHFpgaReadPortOnResbushold.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Program_Onboard_Clock_ctl_11RHFpgaReadPortOnResbushold.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RHFpgaReadPortOnResbushold.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RHFpgaReadPortOnResbushold.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpgaReadPortOnResbushold.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchInterfaceDmaRegisters.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSourceStreamStateController.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSinkStreamStateController.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputController.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputController.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/bushold.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgIoPort2.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PacketSink.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaClipContainer.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaStockDcm.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_FPGA_Generate_and_Acquire.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/IoPort2LvFpga.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_infrastructure.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchSinkStream.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchRegisterAccess.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchIrqInterface.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutput.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInput.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchCommIfcArbiterBase.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TheWindow.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20TimingEngine.vhd" into library work

Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20DramMain.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20ClkDetect.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgPuma20.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgLvFpgaConst.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ClockGenXilinxV5.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaInterface.vhd" into library workParsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.vhd" into library workCRITICAL WARNING: [EDIF 20-96] Could not resolve non-primitive black box cell 'InvisibleResholder(2,1)' instantiated as 'n_InvisibleResholder' [C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_FPGA_Generate_and_Acquire.vhd:1050]Resolution: File names need to match cell names: an EDIF definition will be found in InvisibleResholder(2,1).edf; an HDL definition may be placed in any Verilog/VHDL file.CRITICAL WARNING: [EDIF 20-96] Could not resolve non-primitive black box cell 'BuiltinFIFOCoreFPGAwFIFOn0' instantiated as 'BuiltinFifoIP' [C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn0.vhd:504]Resolution: File names need to match cell names: an EDIF definition will be found in BuiltinFIFOCoreFPGAwFIFOn0.edf; an HDL definition may be placed in any Verilog/VHDL file.CRITICAL WARNING: [EDIF 20-96] Could not resolve non-primitive black box cell 'BuiltinFIFOCoreFPGAwFIFOn1' instantiated as 'BuiltinFifoIP' [C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn1.vhd:504]Resolution: File names need to match cell names: an EDIF definition will be found in BuiltinFIFOCoreFPGAwFIFOn1.edf; an HDL definition may be placed in any Verilog/VHDL file.Release 14.4 - ngc2edif P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

Reading design Puma20IoPort2Glue.ngc ...

WARNING:NetListWriters:298 - No output is written to Puma20IoPort2Glue.xncf,

ignored.

Processing design ...

Preping design's networks ...

Preping design's macros ...

finished :Prep

Writing EDIF netlist file Puma20IoPort2Glue.edif ...

ngc2edif: Total memory usage is 82456 kilobytes

Reading core file 'C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20IoPort2Glue.ngc' for (cell view 'Puma20IoPort2Glue', library 'work', file 'Puma20Top.vhd')Parsing EDIF File [./.Xil/PlanAhead-20668-/ngc2edif/Puma20IoPort2Glue.edif]Finished Parsing EDIF File [./.Xil/PlanAhead-20668-/ngc2edif/Puma20IoPort2Glue.edif]Release 14.4 - ngc2edif P.49d (nt64)

Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

Reading design PumaFixedLogic.ngc ...

WARNING:NetListWriters:298 - No output is written to PumaFixedLogic.xncf,

ignored.

Processing design ...

Preping design's networks ...

Preping design's macros ...

WARNING:NetListWriters:306 - Signal bus

PumaTbMgrx/TbIdReaderx/mLocalCtrl_WtData[2 : 0] on block PumaFixedLogic is

not reconstructed, because there are some missing bus signals.


PumaFixedRegsx/GND_46_o_GND_46_o_mux_48_OUT[5 : 0] on block PumaFixedLogic is

not reconstructed, because there are some missing bus signals.


PumaFixedRegsx/GND_46_o_GND_46_o_mux_50_OUT[23 : 0] on block PumaFixedLogic

is not reconstructed, because there are some missing bus signals.


PumaFixedRegsx/GND_46_o_GND_46_o_mux_72_OUT[31 : 0] on block PumaFixedLogic


WARNING:NetListWriters:306 - Signal bus PumaFixedRegsx/mReadDataArray_16[23 : 0]

on block PumaFixedLogic is not reconstructed, because there are some missing

bus signals.

WARNING:NetListWriters:306 - Signal bus PumaFixedRegsx/mReadDataArray_14[5 : 0]

on block PumaFixedLogic is not reconstructed, because there are some missing

bus signals.

WARNING:NetListWriters:306 - Signal bus PumaSpiMgrx/mDacWord[18 : 0] on block

PumaFixedLogic is not reconstructed, because there are some missing bus

signals.


PumaSpiMgrx/SpiControllerx/mDacWordInt[21 : 0] on block PumaFixedLogic is not

reconstructed, because there are some missing bus signals.


PumaSpiMgrx/SpiControllerx/SpiTempx/mCurState[1]_mDataOut[15]_wide_mux_15_OUT

[14 : 5] on block PumaFixedLogic is not reconstructed, because there are some

missing bus signals.

WARNING:NetListWriters:306 - Signal bus PumaTbMgrx/I2cArbiterx/_n0082[3 : 0] on

block PumaFixedLogic is not reconstructed, because there are some missing bus

signals.


TbStatusClkXingx/PcbTempHS/HBx/iLclStoredData[15 : 0] on block PumaFixedLogic


finished :Prep

Writing EDIF netlist file PumaFixedLogic.edif ...

ngc2edif: Total memory usage is 85912 kilobytes

Reading core file 'C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PumaFixedLogic.ngc' for (cell view 'PumaFixedLogic', library 'work', file 'Puma20Top.vhd')Parsing EDIF File [./.Xil/PlanAhead-20668-/ngc2edif/PumaFixedLogic.edif]Finished Parsing EDIF File [./.Xil/PlanAhead-20668-/ngc2edif/PumaFixedLogic.edif]CRITICAL WARNING: [EDIF 20-96] Could not resolve non-primitive black box cell 'IoPort2Wrapper(16,false,false,false)' instantiated as 'IoPort2Wrapperx' [C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.vhd:1104]Resolution: File names need to match cell names: an EDIF definition will be found in IoPort2Wrapper(16,false,false,false).edf; an HDL definition may be placed in any Verilog/VHDL file.INFO: [Designutils 20-910] Reading macro library C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data\./parts/xilinx/virtex5/virtex5sx/hd_int_macros.ednParsing EDIF File [C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data\./parts/xilinx/virtex5/virtex5sx/hd_int_macros.edn]

Finished Parsing EDIF File [C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data\./parts/xilinx/virtex5/virtex5sx/hd_int_macros.edn]INFO: [Device 21-21] Reading bus macro file C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data\./parts/xilinx/virtex5/pr_bus_macros.xmlLoading clock regions from C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data\parts/xilinx/virtex5/virtex5sx/xc5vsx50t/ClockRegion.xmlLoading clock buffers from C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data\parts/xilinx/virtex5/virtex5sx/xc5vsx50t/ClockBuffers.xmlLoading package from C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data\parts/xilinx/virtex5/virtex5sx/xc5vsx50t/ff1136/Package.xmlLoading io standards from C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data\./parts/xilinx/virtex5/IOStandards.xmlINFO: [Device 21-19] Loading pkg sso from C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data\parts/xilinx/virtex5/virtex5sx/xc5vsx50t/ff1136/SSORules.xmlLoading list of drcs for the architecture : C:/NIFPGA/programs/Xilinx14_4/PlanAhead/data\./parts/xilinx/virtex5/drc.xmlINFO: [Project 1-111] Unisim Transformation Summary:No Unisim elements were transformed.

Phase 0 | Netlist Checksum: 58a786a0open_rtl_design: Time (s): elapsed = 00:00:22 . Memory (MB): peak = 469.613 ; gain = 350.180# report_resources -file Puma20Top_planAheadResults.xml -format xmlINFO: [Designutils 20-301] Performing resource estimation on Puma20Top targeting virtex5...INFO: [Designutils 20-286] Found 9765 primitives in netlistINFO: [Designutils 20-295] Found reset/set on shift register ending at sRefClkPrsnt. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.HandshakeSLV_Ackx/HBx/BlkOut.oPushToggle1. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.HandshakeSLV_Ackx/HBx/BlkRdy.iRdyPushToggle. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.HandshakeSLV_Ackx/HBx/BlkRdy.iReset. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.HandshakeSLVx/HBx/BlkOut.oPushToggle1. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.HandshakeSLVx/HBx/BlkRdy.iRdyPushToggle. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.HandshakeSLVx/HBx/BlkRdy.iReset. Adding 1 LUTs and 2 Flops to estimation.

INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.HandshakeSLV_Ackx/HBx/BlkOut.oPushToggle1. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.HandshakeSLV_Ackx/HBx/BlkRdy.iRdyPushToggle. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.HandshakeSLV_Ackx/HBx/BlkRdy.iReset. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.HandshakeSLVx/HBx/BlkOut.oPushToggle1. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.HandshakeSLVx/HBx/BlkRdy.iRdyPushToggle. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.HandshakeSLVx/HBx/BlkRdy.iReset. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.HandshakeSLV_Ackx/HBx/BlkOut.oPushToggle1. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.HandshakeSLV_Ackx/HBx/BlkRdy.iRdyPushToggle. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.HandshakeSLV_Ackx/HBx/BlkRdy.iReset. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.HandshakeSLVx/HBx/BlkOut.oPushToggle1. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.HandshakeSLVx/HBx/BlkRdy.iRdyPushToggle. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.HandshakeSLVx/HBx/BlkRdy.iReset. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/IO_Module_arAcqDataSample6_din/cSecondRegister. Adding 0 LUTs and 1 Flops to estimation.

INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/IO_Module_arAcqDataSample5_din/cSecondRegister. Adding 0 LUTs and 1 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/IO_Module_arAcqDataSample4_din/cSecondRegister. Adding 0 LUTs and 1 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/IO_Module_arAcqDataSample3_din/cSecondRegister. Adding 0 LUTs and 1 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/IO_Module_arAcqDataSample2_din/cSecondRegister. Adding 0 LUTs and 1 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/IO_Module_arAcqDataSample1_din/cSecondRegister. Adding 0 LUTs and 1 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/IO_Module_arAcqDataSample0_din/cSecondRegister. Adding 0 LUTs and 1 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/IO_Module_rXpointInterfaceRdy_din/cSecondRegister[0]. Adding 0 LUTs and 1 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/IO_Module_rI2cReadWriteRdy_din/cSecondRegister[0]. Adding 0 LUTs and 1 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzFromInterface/BlkOut.SyncOReset/c1ResetFromClk2. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzToInterface/BlkOut.SyncIReset/c1ResetFromClk2. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzToInterface/BlkOut.SyncOReset/c2ResetLcl. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.SyncOReset/c1ResetFromClk2. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/BlkOut.SyncIReset/c1ResetFromClk2. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/BlkOut.SyncOReset/c2ResetLcl. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmFifoFlagsx/OClkToIClkCrossing.SyncToIClk/oPushRcvd. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmFifoFlagsx/OClkToIClkCrossing.SyncToIClk/iAckRcvd. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.Chinch

DmaInputFifoInterfacex/InStrmFifox/InStrmFifoFlagsx/oWritesDisabledLoc. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/c1ResetFromClk2. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.SyncOReset/c2ResetLcl. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncIReset/c1ResetFromClk2. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetLcl. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/c1ResetFromClk2. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.SyncOReset/c2ResetLcl. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncIReset/c1ResetFromClk2. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetLcl. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/c1ResetFromClk2. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkOut.SyncOReset/c2ResetLcl. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncIReset/c1ResetFromClk2. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/

HandshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetLcl. Adding 1 LUTs and 2 Flops to estimation.INFO: [Designutils 20-295] Found reset/set on shift register ending at Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.GenDefaultStateCrossing.HandshakeStateToDefaultClkDomain/HBx/BlkOut.oPushToggle1. Adding 1 LUTs and 2 Flops to estimation.INFO: [Common 17-14] Message 'Designutils 20-295' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_limit to change the current settings.INFO: [Designutils 20-303] Reporting estimation...INFO: [Designutils 20-300] Optimized 270 multiplexer treesINFO: [Designutils 20-298] Merged 112 multiplexers with driving combinational logicINFO: [Designutils 20-285] Found 459 multiplexers used for register control logicINFO: [Designutils 20-296] Inferred 214 shift registers using 214 SRL32sINFO: [Designutils 20-275] 2-bit shift registers : 213INFO: [Designutils 20-275] 32-bit shift registers : 1INFO: [Designutils 20-289] Found 2 registers consumed by IOBsINFO: [Designutils 20-297] Merged 618 bitwise logic elementsINFO: [Designutils 20-283] Found 1183 elements classified as dangling or disabled logicINFO: [Designutils 20-282] Found 16 ROMsWARNING: [Designutils 20-278] Estimation does not include 4 empty CellViews (see warnings)INFO: [Designutils 20-277] Completed resource estimation on Puma20Top - Slices: 2662, LUTs: 5941, Flops: 6783, BRAMs: 6, DSP48s: 0INFO: [Common 17-206] Exiting PlanAhead at Tue May 20 14:12:28 2014...INFO: [Common 17-83] Releasing license: PlanAheadPuma20Top INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ADPRAM36K.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/AcquisitionEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchCommIfcArbiterBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentInputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentOutputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStateTransitionEnableChain. vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStreamStateEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSinkStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSourceStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchInterfaceDmaRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchIrqInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaIrq.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchRegisterAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchSinkStream.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ClockGenXilinxV5.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchSourceSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForBit0_ctl_3RHFpgaReadPortOnResbush old.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpg aReadPortOnResbushold.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Program_Onboard_Cl ock_ctl_11RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Xpoint_Switch_Writ e_ctl_0RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForMiteIoLikePortOnResInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viAc q_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viBi t00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viCl ear_T2H_DMA_Timeout10.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viFe tch_Length9.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Acq_Reset12.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Gen_Reset7.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viSo ftware_Trigger8.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForSoftware_Trigger_ctl_12RHFpgaRead PortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForTopEnablesPortOnResTopEnablePassT hru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlop.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBoolFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopSlvResetVal.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM32Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM64Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Deserializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DiagramReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncAsyncInBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBoolAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSlAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viBit00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FeedbackNonSctlCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopE nInIClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoPtrClockCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FloatingFeedbackGInit.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpDynamicShift.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpNormalize.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpShiftCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/GenerationEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBaseResetCross.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV_Ack.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cIssueCycle.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cReadWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmRAMArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Interface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InvisibleResholder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/IoPort2LvFpga.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co_2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587Base.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587ConnectorSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587CoreSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000001_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000003_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000005_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000018_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000001a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructure_62.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000002c_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000043_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000045_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000049_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004b_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0003.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0004.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd

" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructure_149.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005d_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005f_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000061_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000098_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_FPGA_Generate_and_Acquire.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_178.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_179.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_180.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_181.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbDelayer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbPowerOf2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbRW.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbSerializeAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOpNot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltInFifoResetControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltinFifoCounter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaClockManagerControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaCtrlIndRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDiRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDoWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoClearControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoCountControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPopBuffer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPortReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPushPopControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFlipFlopFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaHostAccessibleRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLvJoinNumbers.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPipelinedOrGateTreeSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPulseSyncBaseWrapper.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegFrameworkShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCoreBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaStockDcm.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaTopEnInSyncForExternalClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFixedToFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAddCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtractCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixed.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixedCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaClipContainer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandlerSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFixedPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFloatingPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToInteger.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Add.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Equal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Greater.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32GreaterOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Less.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32LessOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32NotEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Subtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmDPRAM.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmOutputHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PacketSink.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgADPRAM36KUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgByteArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchConfig.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommIntConfiguration.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDataPackingFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaRegs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFpgaDeviceSpecs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxpArithmetic.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgGray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgInStrmFifoUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgIoPort2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgLvFpgaConst.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNi6587.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaIrqRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaViControlRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiLvPrims.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgOneHot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgPuma20.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgStreamStates.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgSwitchedChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20ClkDetect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20DramMain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/RegionalClockBuf.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ResetSync.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SafeBusCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Serializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamDataReceiver.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamTcrUpdateController.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/StrmArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SubVICtlOrIndOpt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TheWindow.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopDomainCrosser.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimeoutManager.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TopEnablePassThru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViSignature.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNode.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNodeOut.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/bushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_idelay_ctrl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_infrastructure.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Sy nchronous_Lat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_r_opt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_w_opt.vhd" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.WARNING:ProjectMgmt - Circular Reference: work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtlINFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. Please set the new top explicitly by running the "project set top" command. To re-calculate the new top automatically, set the "Auto Implementation Top" property to true.

Started : "Synthesize - XST".Running xst...Command Line: xst -intstyle ise -ifn "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.xst" -ofn "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.syr"Reading design: Puma20Top.prj

=========================================================================* HDL Parsing *=========================================================================WARNING:Xst:2838 - Path definition '$XILINX/verilog/xst/nt/cpld_det_ver' in file C:/NIFPGA/programs/Xilinx14_4/ISE/vhdl/xst/nt/hdc.ini is invalid and being ignored. Check the path and ensure that any environment variable specification is legal.WARNING:Xst:2838 - Path definition '$XILINX/verilog/xst/nt/unimacro_ver' in file C:/NIFPGA/programs/Xilinx14_4/ISE/vhdl/xst/nt/hdc.ini is invalid and being ignored. Check the path and ensure that any environment variable specification is legal.WARNING:Xst:2838 - Path definition '$XILINX/verilog/xst/nt/unisim_ver' in file C:/NIFPGA/programs/Xilinx14_4/ISE/vhdl/xst/nt/hdc.ini is invalid and being ignored. Check the path and ensure that any environment variable specification is legal.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgNiUtilities.vhd" into library workParsing package <PkgNiUtilities>.Parsing package body <PkgNiUtilities>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgNiFpgaUtilities.vhd" into library workParsing package <PkgNiFpgaUtilities>.Parsing package body <PkgNiFpgaUtilities>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgFxp.vhd" into library workParsing package <PkgFxp>.Parsing package body <PkgFxp>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgFxpArithmetic.vhd" into library workParsing package <PkgFxpArithmetic>.Parsing package body <PkgFxpArithmetic>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FxpShiftCore.vhd" into library workParsing entity <FxpShiftCore>.Parsing architecture <rtl> of entity <fxpshiftcore>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgOneHot.vhd" into library workParsing package <pkgOneHot>.Parsing package body <pkgOneHot>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgFpgaDeviceSpecs.vhd" into library workParsing package <PkgFpgaDeviceSpecs>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgFloat.vhd" into library workParsing package <PkgFloat>.Parsing package body <PkgFloat>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgADPRAM36KUtil.vhd" into library workParsing package <PkgADPRAM36KUtil>.Parsing package body <PkgADPRAM36KUtil>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpEnableHandlerSlv.vhd" into library workParsing entity <NiLvFxpEnableHandlerSlv>.Parsing architecture <rtl> of entity <nilvfxpenablehandlerslv>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FxpDynamicShift.vhd" into library workParsing entity <FxpDynamicShift>.Parsing architecture <rtl> of entity <fxpdynamicshift>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlop.vhd" into library workParsing entity <DFlop>.Parsing architecture <rtl> of entity <dflop>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PulseSyncBase.vhd" into library workParsing entity <PulseSyncBase>.Parsing architecture <behavior> of entity <pulsesyncbase>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgChinch.vhd" into library workParsing package <PkgChinch>.Parsing package body <PkgChinch>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgByteArray.vhd" into library workParsing package <PkgByteArray>.Parsing package body <PkgByteArray>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpEnableHandler.vhd" into library workParsing entity <NiLvFxpEnableHandler>.Parsing architecture <rtl> of entity <nilvfxpenablehandler>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFloatToFixedCore.vhd" into library workParsing entity <NiLvFloatToFixedCore>.Parsing architecture <rtl> of entity <nilvfloattofixedcore>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FxpNormalize.vhd" into library workParsing entity <FxpNormalize>.Parsing architecture <rtl> of entity <fxpnormalize>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncAsyncInBase.vhd" into library workParsing entity <DoubleSyncAsyncInBase>.Parsing architecture <rtl> of entity <doublesyncasyncinbase>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlopSlvResetVal.vhd" into library workParsing entity <DFlopSlvResetVal>.Parsing architecture <rtl> of entity <dflopslvresetval>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlopFallingEdge.vhd" into library workParsing entity <DFlopFallingEdge>.Parsing architecture <rtl> of entity <dflopfallingedge>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ADPRAM36K.vhd" into library workParsing entity <ADPRAM36K>.Parsing architecture <rtl> of entity <adpram36k>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PulseSyncBool.vhd" into library workParsing entity <PulseSyncBool>.Parsing architecture <behavior> of entity <pulsesyncbool>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgNiLvPrims.vhd" into library workParsing package <PkgNiLvPrims>.Parsing package body <PkgNiLvPrims>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgGray.vhd" into library workParsing package <PkgGray>.Parsing package body <PkgGray>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgCommIntConfiguration.vhd" into library workParsing package <PkgCommIntConfiguration>.Parsing package body <PkgCommIntConfiguration>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgChinchConfig.vhd" into library workParsing package <PkgChinchConfig>.Parsing package body <PkgChinchConfig>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCoerce.vhd" into library workParsing entity <NiLvFxpCoerce>.Parsing architecture <rtl> of entity <nilvfxpcoerce>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFloatToFixed.vhd" into library workParsing entity <NiLvFloatToFixed>.Parsing architecture <rtl> of entity <nilvfloattofixed>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFixedToFloat.vhd" into library workParsing entity <NiLvFixedToFloat>.Parsing architecture <rtl> of entity <nilvfixedtofloat>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaRegisterCoreBase.vhd" into library workParsing entity <NiFpgaRegisterCoreBase>.Parsing architecture <rtl> of entity <nifpgaregistercorebase>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaPulseSyncBaseWrapper.vhd" into library workParsing entity <NiFpgaPulseSyncBaseWrapper>.Parsing architecture <rtl> of entity <nifpgapulsesyncbasewrapper>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DPRAM32Bits.vhd" into library workParsing entity <DPRAM32Bits>.Parsing architecture <rtl> of entity <dpram32bits>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncBase.vhd" into library workParsing entity <DoubleSyncBase>.Parsing architecture <behavior> of entity <doublesyncbase>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlopBoolFallingEdge.vhd" into library workParsing entity <DFlopBoolFallingEdge>.Parsing architecture <rtl> of entity <dflopboolfallingedge>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlopBool.vhd" into library workParsing entity <DFlopBool>.Parsing architecture <rtl> of entity <dflopbool>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ResetSync.vhd" into library workParsing entity <ResetSync>.Parsing architecture <rtl> of entity <resetsync>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgSwitchedChinch.vhd" into library workParsing package <PkgSwitchedChinch>.Parsing package body <PkgSwitchedChinch>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgInStrmFifoUtil.vhd" into library workParsing package <PkgInStrmFifoUtil>.Parsing package body <PkgInStrmFifoUtil>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgDataPackingFifo.vhd" into library workParsing package <PkgDataPackingFifo>.Parsing package body <PkgDataPackingFifo>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgCommunicationInterface.vhd" into library workParsing package <PkgCommunicationInterface>.Parsing package body <PkgCommunicationInterface>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvToInteger.vhd" into library workParsing entity <NiLvToInteger>.Parsing architecture <rtl> of entity <nilvtointeger>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvToFloatingPoint.vhd" into library workParsing entity <NiLvToFloatingPoint>.Parsing architecture <rtl> of entity <nilvtofloatingpoint>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvToFixedPoint.vhd" into library workParsing entity <NiLvToFixedPoint>.Parsing architecture <rtl> of entity <nilvtofixedpoint>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaRegisterCore.vhd" into library workParsing entity <NiFpgaRegisterCore>.Parsing architecture <rtl> of entity <nifpgaregistercore>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPortReset.vhd" into library workParsing entity <NiFpgaFifoPortReset>.Parsing architecture <rtl> of entity <nifpgafifoportreset>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FifoPtrClockCrossing.vhd" into library workParsing entity <FifoPtrClockCrossing>.

Parsing architecture <rtl> of entity <fifoptrclockcrossing>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DPRAM64Bits.vhd" into library workParsing entity <DPRAM64Bits>.Parsing architecture <rtl> of entity <dpram64bits>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncBool.vhd" into library workParsing entity <DoubleSyncBool>.Parsing architecture <behavior> of entity <doublesyncbool>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimeoutManager.vhd" into library workParsing entity <TimeoutManager>.Parsing architecture <rtl> of entity <timeoutmanager>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgStreamStates.vhd" into library workParsing package <PkgStreamStates>.Parsing package body <PkgStreamStates>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgNiFpgaFifo.vhd" into library workParsing package <PkgNiFpgaFifo>.Parsing package body <PkgNiFpgaFifo>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgNiFpgaBoolOp.vhd" into library workParsing package <PkgNiFpgaBoolOp>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgNi6587.vhd" into library workParsing package <PkgNi6587>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgChinchCommunicationInterface.vhd" into library workParsing package <PkgChinchCommunicationInterface>.Parsing package body <PkgChinchCommunicationInterface>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\OutStrmFifoFlags.vhd" into library workParsing entity <OutStrmFifoFlags>.Parsing architecture <rtl> of entity <outstrmfifoflags>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\OutStrmDPRAM.vhd" into library workParsing entity <OutStrmDPRAM>.Parsing architecture <rtl> of entity <outstrmdpram>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFloatSubtractCore.vhd" into library workParsing entity <NiLvFloatSubtractCore>.Parsing architecture <rtl> of entity <nilvfloatsubtractcore>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvCoerce.vhd" into library workParsing entity <NiLvCoerce>.Parsing architecture <rtl> of entity <nilvcoerce>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFlipFlopFifo.vhd" into library workParsing entity <NiFpgaFlipFlopFifo>.Parsing architecture <rtl> of entity <nifpgaflipflopfifo>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoClearControl.vhd" into library workParsing entity <NiFpgaFifoClearControl>.Parsing architecture <rtl> of entity <nifpgafifoclearcontrol>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaDoWrite.vhd" into library workParsing entity <NiFpgaDoWrite>.Parsing architecture <rtl> of entity <nifpgadowrite>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmRAMArray.vhd" into library workParsing entity <InStrmRAMArray>.Parsing architecture <rtl> of entity <instrmramarray>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmFifoFlags.vhd" into library workParsing entity <InStrmFifoFlags>.Parsing architecture <rtl> of entity <instrmfifoflags>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBaseResetCross.vhd" into library workParsing entity <HandshakeBaseResetCross>.Parsing architecture <rtl> of entity <handshakebaseresetcross>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBase.vhd" into library workParsing entity <HandshakeBase>.Parsing architecture <behavior> of entity <handshakebase>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FeedbackNonSctlCore.vhd" into library workParsing entity <FeedbackNonSctlCore>.Parsing architecture <rtl> of entity <feedbacknonsctlcore>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SubVICtlOrIndOpt.vhd" into library workParsing entity <SubVICtlOrIndOpt>.Parsing architecture <rtl> of entity <subvictlorindopt>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" into library workParsing entity <Serializer>.Parsing architecture <RTL> of entity <serializer>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\resholder_w_opt.vhd" into library workParsing entity <resholder_w_opt>.Parsing architecture <rtl> of entity <resholder_w_opt>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\resholder_r_opt.vhd" into library workParsing entity <resholder_r_opt>.Parsing architecture <rtl> of entity <resholder_r_opt>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\RegionalClockBuf.vhd" into library workParsing entity <RegionalClockBuf>.Parsing architecture <RTL> of entity <regionalclockbuf>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgDmaFifos.vhd" into library workParsing package <PkgDmaFifos>.Parsing package body <PkgDmaFifos>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\OutStrmFifo.vhd" into library workParsing entity <OutStrmFifo>.Parsing architecture <rtl> of entity <outstrmfifo>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpSubtract.vhd" into library workParsing entity <NiLvFxpSubtract>.Parsing architecture <rtl> of entity <nilvfxpsubtract>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCompare.vhd" into library workParsing entity <NiLvFxpCompare>.Parsing architecture <rtl> of entity <nilvfxpcompare>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFloatSubtract.vhd" into library workParsing entity <NiLvFloatSubtract>.Parsing architecture <rtl> of entity <nilvfloatsubtract>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFloatCompareCore.vhd" into library workParsing entity <NiLvFloatCompareCore>.Parsing architecture <rtl> of entity <nilvfloatcomparecore>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFloatAddCore.vhd" into library workParsing entity <NiLvFloatAddCore>.Parsing architecture <rtl> of entity <nilvfloataddcore>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPopBuffer.vhd" into library workParsing entity <NiFpgaFifoPopBuffer>.Parsing architecture <rtl> of entity <nifpgafifopopbuffer>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoCountControl.vhd" into library workParsing entity <NiFpgaFifoCountControl>.Parsing architecture <rtl> of entity <nifpgafifocountcontrol>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBoolOpNot.vhd" into library workParsing entity <NiFpgaBoolOpNot>.Parsing architecture <rtl> of entity <nifpgaboolopnot>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBoolOp.vhd" into library workParsing entity <NiFpgaBoolOp>.Parsing architecture <rtl> of entity <nifpgaboolop>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005a_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_0000005a_SequenceFrame>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000005a_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmFifo.vhd" into library workParsing entity <InStrmFifo>.Parsing architecture <rtl> of entity <instrmfifo>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\I2cIssueCycle.vhd" into library workParsing entity <I2cIssueCycle>.Parsing architecture <behavioral> of entity <i2cissuecycle>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeSLV_Ack.vhd" into library workParsing entity <HandshakeSLV_Ack>.Parsing architecture <struct> of entity <handshakeslv_ack>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeSLV.vhd" into library workParsing entity <HandshakeSLV>.Parsing architecture <struct> of entity <handshakeslv>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FloatingFeedbackGInit.vhd" into library workParsing entity <FloatingFeedbackGInit>.Parsing architecture <rtl> of entity <floatingfeedbackginit>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncSlAsyncIn.vhd" into library workParsing entity <DoubleSyncSlAsyncIn>.Parsing architecture <rtl> of entity <doublesyncslasyncin>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncSL.vhd" into library workParsing entity <DoubleSyncSL>.Parsing architecture <behavior> of entity <doublesyncsl>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" into library workParsing entity <Deserializer>.Parsing architecture <RTL> of entity <deserializer>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CrossSwitchInterface.vhd" into library workParsing entity <CrossSwitchInterface>.Parsing architecture <rtl> of entity <crossswitchinterface>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStreamStateEnableChain.vhd" into library workParsing entity <ChinchDmaComponentStreamStateEnableChain>.Parsing architecture <rtl> of entity <chinchdmacomponentstreamstateenablechain>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStateTransitionEnableChain.vhd" into library workParsing entity <ChinchDmaComponentStateTransitionEnableChain>.Parsing architecture <rtl> of entity <chinchdmacomponentstatetransitionenablechain>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentOutputStateHolder.vhd" into library workParsing entity <ChinchDmaComponentOutputStateHolder>.Parsing architecture <rtl> of entity <chinchdmacomponentoutputstateholder>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentInputStateHolder.vhd" into library workParsing entity <ChinchDmaComponentInputStateHolder>.

Parsing architecture <rtl> of entity <chinchdmacomponentinputstateholder>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentEnableChain.vhd" into library workParsing entity <ChinchDmaComponentEnableChain>.Parsing architecture <rtl> of entity <chinchdmacomponentenablechain>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimingEngine.vhd" into library workParsing entity <TimingEngine>.Parsing architecture <RTL> of entity <timingengine>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimedLoopDomainCrosser.vhd" into library workParsing entity <TimedLoopDomainCrosser>.Parsing architecture <rtl> of entity <timedloopdomaincrosser>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimedLoopController.vhd" into library workParsing entity <TimedLoopController>.Parsing architecture <rtl> of entity <timedloopcontroller>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgNiFpgaIrqRegisters.vhd" into library workParsing package <PkgNiFpgaIrqRegisters>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd" into library workParsing entity <NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2>.Parsing architecture <vhdl_labview> of entity <ni_flexrio_helper_vis_lvlib_colon_rising_edge_detect_vi_co_2>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpDecrement.vhd" into library workParsing entity <NiLvFxpDecrement>.Parsing architecture <rtl> of entity <nilvfxpdecrement>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCompareToZero.vhd" into library workParsing entity <NiLvFxpCompareToZero>.Parsing architecture <rtl> of entity <nilvfxpcomparetozero>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpAdd.vhd" into library workParsing entity <NiLvFxpAdd>.Parsing architecture <rtl> of entity <nilvfxpadd>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFloatDecrement.vhd" into library workParsing entity <NiLvFloatDecrement>.Parsing architecture <rtl> of entity <nilvfloatdecrement>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFloatCompareToZero.vhd" into library workParsing entity <NiLvFloatCompareToZero>.Parsing architecture <rtl> of entity <nilvfloatcomparetozero>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFloatCompare.vhd" into library workParsing entity <NiLvFloatCompare>.Parsing architecture <rtl> of entity <nilvfloatcompare>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFloatAdd.vhd" into library workParsing entity <NiLvFloatAdd>.Parsing architecture <rtl> of entity <nilvfloatadd>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" into library workParsing entity <niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat>.Parsing architecture <vhdl_labview> of entity <niinstr_basic_elements_v1_fpga_lvlib_colon_synchronous_lat>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaSelect.vhd" into library workParsing entity <NiFpgaSelect>.Parsing architecture <rtl> of entity <nifpgaselect>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaLocalResHolderWrite.vhd" into library workParsing entity <NiFpgaLocalResHolderWrite>.Parsing architecture <rtl> of entity <nifpgalocalresholderwrite>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaLocalResHolderRead.vhd" into library workParsing entity <NiFpgaLocalResHolderRead>.Parsing architecture <rtl> of entity <nifpgalocalresholderread>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaGlobalResHolderRead.vhd" into library workParsing entity <NiFpgaGlobalResHolderRead>.Parsing architecture <rtl> of entity <nifpgaglobalresholderread>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaDiRead.vhd" into library workParsing entity <NiFpgaDiRead>.Parsing architecture <rtl> of entity <nifpgadiread>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbPowerOf2.vhd" into library workParsing entity <NiFpgaArbPowerOf2>.Parsing architecture <rtl> of entity <nifpgaarbpowerof2>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000061_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_00000061_SequenceFrame>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000061_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005f_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_0000005f_SequenceFrame>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000005f_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005d_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_0000005d_SequenceFrame>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000005d_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000059_CaseStructureFrame_0001.vhd" into library workParsing entity <NiFpgaAG_00000059_CaseStructureFrame_0001>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000059_casestructureframe_0001>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000059_CaseStructureFrame_0000.vhd" into library workParsing entity <NiFpgaAG_00000059_CaseStructureFrame_0000>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000059_casestructureframe_0000>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructure_62.vhd" into library workParsing entity <NiFpgaAG_00000029_CaseStructure_62>.Parsing architecture <vhdl_modgen> of entity <nifpgaag_00000029_casestructure_62>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" into library workParsing entity <Ni6587Base>.Parsing architecture <RTL> of entity <ni6587base>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\I2cReadWrite.vhd" into library workParsing entity <I2cReadWrite>.Parsing architecture <rtl> of entity <i2creadwrite>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeWithResetValueBase.vhd" into library workParsing entity <HandshakeWithResetValueBase>.Parsing architecture <behavior> of entity <handshakewithresetvaluebase>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\GenerationEngine.vhd" into library workParsing entity <GenerationEngine>.Parsing architecture <RTL> of entity <generationengine>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncWithResetValueSL.vhd" into library workParsing entity <DoubleSyncWithResetValueSL>.Parsing architecture <behavior> of entity <doublesyncwithresetvaluesl>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncSLV.vhd" into library workParsing entity <DoubleSyncSLV>.Parsing architecture <struct> of entity <doublesyncslv>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncBoolAsyncIn.vhd" into library workParsing entity <DoubleSyncBoolAsyncIn>.Parsing architecture <rtl> of entity <doublesyncboolasyncin>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CrossSwitchSourceSelect.vhd" into library workParsing entity <CrossSwitchSourceSelect>.Parsing architecture <rtl> of entity <crossswitchsourceselect>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" into library workParsing entity <ChinchDmaOutputFifoInterface>.Parsing architecture <structure> of entity <chinchdmaoutputfifointerface>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" into library workParsing entity <ChinchDmaInputFifoInterface>.Parsing architecture <structure> of entity <chinchdmainputfifointerface>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\AcquisitionEngine.vhd" into library workParsing entity <AcquisitionEngine>.Parsing architecture <RTL> of entity <acquisitionengine>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\XDataNodeOut.vhd" into library workParsing entity <XDataNodeOut>.Parsing architecture <rtl> of entity <xdatanodeout>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\XDataNode.vhd" into library workParsing entity <XDataNode>.Parsing architecture <rtl> of entity <xdatanode>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimedLoopCore.vhd" into library workParsing entity <TimedLoopCore>.Parsing architecture <rtl> of entity <timedloopcore>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SafeBusCrossing.vhd" into library workParsing entity <SafeBusCrossing>.Parsing architecture <rtl> of entity <safebuscrossing>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgRegister.vhd" into library workParsing package <PkgRegister>.Parsing package body <PkgRegister>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgNiFpgaViControlRegister.vhd" into library workParsing package <PkgNiFpgaViControlRegister>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgNiFpgaArbiter.vhd" into library workParsing package <PkgNiFpgaArbiter>.Parsing package body <PkgNiFpgaArbiter>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgDmaRegs.vhd" into library workParsing package <PkgDmaRegs>.Parsing package body <PkgDmaRegs>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgChinchArbiter.vhd" into library workParsing package <PkgCHInChArbiter>.Parsing package body <PkgCHInChArbiter>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd" into library workParsing entity <NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co>.Parsing architecture <vhdl_labview> of entity <ni_flexrio_helper_vis_lvlib_colon_rising_edge_detect_vi_co>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvDecrement.vhd" into library workParsing entity <NiLvDecrement>.Parsing architecture <rtl> of entity <nilvdecrement>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvCompareToZero.vhd" into library workParsing entity <NiLvCompareToZero>.Parsing architecture <rtl> of entity <nilvcomparetozero>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvCompare.vhd" into library workParsing entity <NiLvCompare>.Parsing architecture <rtl> of entity <nilvcompare>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvAdd.vhd" into library workParsing entity <NiLvAdd>.Parsing architecture <rtl> of entity <nilvadd>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaTopEnInSyncForExternalClk.vhd" into library workParsing entity <NiFpgaTopEnInSyncForExternalClk>.Parsing architecture <rtl> of entity <nifpgatopeninsyncforexternalclk>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaShiftReg.vhd" into library workParsing entity <NiFpgaShiftReg>.Parsing architecture <rtl> of entity <nifpgashiftreg>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaRegFrameworkShiftReg.vhd" into library workParsing entity <NiFpgaRegFrameworkShiftReg>.Parsing architecture <rtl> of entity <nifpgaregframeworkshiftreg>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaLvJoinNumbers.vhd" into library workParsing entity <NiFpgaLvJoinNumbers>.Parsing architecture <rtl> of entity <nifpgalvjoinnumbers>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaHostAccessibleRegister.vhd" into library workParsing entity <NiFpgaHostAccessibleRegister>.Parsing architecture <rtl> of entity <nifpgahostaccessibleregister>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaGlobalResHolderWrite.vhd" into library workParsing entity <NiFpgaGlobalResHolderWrite>.Parsing architecture <rtl> of entity <nifpgaglobalresholderwrite>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPushPopControl.vhd" into library workParsing entity <NiFpgaFifoPushPopControl>.Parsing architecture <rtl> of entity <nifpgafifopushpopcontrol>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBuiltInFifoResetControl.vhd" into library workParsing entity <NiFpgaBuiltInFifoResetControl>.Parsing architecture <rtl> of entity <nifpgabuiltinfiforesetcontrol>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBuiltinFifoCounter.vhd" into library work

Parsing entity <NiFpgaBuiltinFifoCounter>.Parsing architecture <rtl> of entity <nifpgabuiltinfifocounter>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbSerializeAccess.vhd" into library workParsing entity <NiFpgaArbSerializeAccess>.Parsing architecture <rtl> of entity <nifpgaarbserializeaccess>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbDelayer.vhd" into library workParsing entity <NiFpgaArbDelayer>.Parsing architecture <rtl> of entity <nifpgaarbdelayer>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" into library workParsing entity <NiFpgaAG_0000009c_CaseStructureFrame_0001>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000009c_casestructureframe_0001>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0000.vhd" into library workParsing entity <NiFpgaAG_0000009c_CaseStructureFrame_0000>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000009c_casestructureframe_0000>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructure_149.vhd" into library workParsing entity <NiFpgaAG_0000004d_CaseStructure_149>.Parsing architecture <vhdl_modgen> of entity <nifpgaag_0000004d_casestructure_149>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd" into library workParsing entity <NiFpgaAG_0000004d_CaseStructureFrame_0005>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000004d_casestructureframe_0005>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0004.vhd" into library workParsing entity <NiFpgaAG_0000004d_CaseStructureFrame_0004>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000004d_casestructureframe_0004>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0003.vhd" into library workParsing entity <NiFpgaAG_0000004d_CaseStructureFrame_0003>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000004d_casestructureframe_0003>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd" into library workParsing entity <NiFpgaAG_0000004d_CaseStructureFrame_0002>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000004d_casestructureframe_0002>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd" into library workParsing entity <NiFpgaAG_0000004d_CaseStructureFrame_0001>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000004d_casestructureframe_0001>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd" into library workParsing entity <NiFpgaAG_0000004d_CaseStructureFrame_0000>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000004d_casestructureframe_0000>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004b_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_0000004b_SequenceFrame>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000004b_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000049_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_00000049_SequenceFrame>.

Parsing architecture <vhdl_labview> of entity <nifpgaag_00000049_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000045_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_00000045_SequenceFrame>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000045_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000002c_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_0000002c_SequenceFrame>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000002c_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructureFrame_0001.vhd" into library workParsing entity <NiFpgaAG_00000029_CaseStructureFrame_0001>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000029_casestructureframe_0001>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructureFrame_0000.vhd" into library workParsing entity <NiFpgaAG_00000029_CaseStructureFrame_0000>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000029_casestructureframe_0000>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_0000001a_SequenceFrame>.Parsing architecture <vhdl_labview> of entity <nifpgaag_0000001a_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_00000005_SequenceFrame>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000005_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000003_SequenceFrame.vhd" into library workParsing entity <NiFpgaAG_00000003_SequenceFrame>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000003_sequenceframe>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587CoreSerdes.vhd" into library workParsing entity <Ni6587CoreSerdes>.Parsing architecture <RTL> of entity <ni6587coreserdes>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeWithResetValueSLV.vhd" into library workParsing entity <HandshakeWithResetValueSLV>.Parsing architecture <struct> of entity <handshakewithresetvalueslv>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncWithResetValueSLV.vhd" into library workParsing entity <DoubleSyncWithResetValueSLV>.Parsing architecture <struct> of entity <doublesyncwithresetvalueslv>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaIrq.vhd" into library workParsing entity <ChinchLvFpgaIrq>.Parsing architecture <rtl> of entity <chinchlvfpgairq>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaFifos.vhd" into library workParsing entity <ChinchDmaFifos>.Parsing architecture <struct> of entity <chinchdmafifos>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ViSignature.vhd" into library workParsing entity <ViSignature>.Parsing architecture <rtl> of entity <visignature>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ViControl.vhd" into library workParsing entity <ViControl>.Parsing architecture <rtl> of entity <vicontrol>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TopEnablePassThru.vhd" into library workParsing entity <TopEnablePassThru>.Parsing architecture <rtl> of entity <topenablepassthru>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\StrmArbiter.vhd" into library workParsing entity <StrmArbiter>.Parsing architecture <rtl> of entity <strmarbiter>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SinkStreamTcrUpdateController.vhd" into library workParsing entity <SinkStreamTcrUpdateController>.Parsing architecture <rtl> of entity <sinkstreamtcrupdatecontroller>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SinkStreamDataReceiver.vhd" into library workParsing entity <SinkStreamDataReceiver>.Parsing architecture <rtl> of entity <sinkstreamdatareceiver>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\OutStrmOutputHandler.vhd" into library workParsing entity <OutStrmOutputHandler>.Parsing architecture <rtl> of entity <outstrmoutputhandler>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFpgaStockDigitalOutput.vhd" into library workParsing entity <NiLvFpgaStockDigitalOutput>.Parsing architecture <rtl> of entity <nilvfpgastockdigitaloutput>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFpgaStockDigitalInput.vhd" into library workParsing entity <NiLvFpgaStockDigitalInput>.Parsing architecture <rtl> of entity <nilvfpgastockdigitalinput>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaCtrlIndRegister.vhd" into library workParsing entity <NiFpgaCtrlIndRegister>.Parsing architecture <rtl> of entity <nifpgactrlindregister>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaClockManagerControl.vhd" into library workParsing entity <NiFpgaClockManagerControl>.Parsing architecture <rtl> of entity <nifpgaclockmanagercontrol>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbRW.vhd" into library workParsing entity <NiFpgaArbRW>.Parsing architecture <rtl> of entity <nifpgaarbrw>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_181.vhd" into library workParsing entity <NiFpgaAG_TimedLoopControllerContainer_181>.Parsing architecture <rtl> of entity <nifpgaag_timedloopcontrollercontainer_181>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_180.vhd" into library workParsing entity <NiFpgaAG_TimedLoopControllerContainer_180>.Parsing architecture <rtl> of entity <nifpgaag_timedloopcontrollercontainer_180>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_179.vhd" into library workParsing entity <NiFpgaAG_TimedLoopControllerContainer_179>.Parsing architecture <rtl> of entity <nifpgaag_timedloopcontrollercontainer_179>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_178.vhd" into library workParsing entity <NiFpgaAG_TimedLoopControllerContainer_178>.Parsing architecture <rtl> of entity <nifpgaag_timedloopcontrollercontainer_178>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" into library work

Parsing entity <NiFpgaAG_00000098_TimedLoopDiagram>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000098_timedloopdiagram>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" into library workParsing entity <NiFpgaAG_00000043_TimedLoopDiagram>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000043_timedloopdiagram>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" into library workParsing entity <NiFpgaAG_00000018_TimedLoopDiagram>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000018_timedloopdiagram>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" into library workParsing entity <NiFpgaAG_00000001_TimedLoopDiagram>.Parsing architecture <vhdl_labview> of entity <nifpgaag_00000001_timedloopdiagram>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587ConnectorSerdes.vhd" into library workParsing entity <Ni6587ConnectorSerdes>.Parsing architecture <RTL> of entity <ni6587connectorserdes>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InvisibleResholder.vhd" into library workParsing entity <InvisibleResholder>.Parsing architecture <rtl> of entity <invisibleresholder>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" into library workParsing entity <Interface>.Parsing architecture <rtl> of entity <interface>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn1.vhd" into library workParsing entity <FPGAwFIFOn1>.Parsing architecture <rtl> of entity <fpgawfifon1>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn0.vhd" into library workParsing entity <FPGAwFIFOn0>.Parsing architecture <rtl> of entity <fpgawfifon0>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopEnInIClk.vhd" into library workParsing entity <FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopEnInIClk>.Parsing architecture <rtl> of entity <fifoio_modulea_aacqclkbufrtolvfpgawfifon0topeniniclk>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd" into library workParsing entity <FGPA_Globals_viIO_Module_bksl_Acq_Reset12>.Parsing architecture <rtl> of entity <fgpa_globals_viio_module_bksl_acq_reset12>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FGPA_Globals_viBit00.vhd" into library workParsing entity <FGPA_Globals_viBit00>.Parsing architecture <rtl> of entity <fgpa_globals_vibit00>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" into library workParsing entity <FGPA_Globals_viAcq_Regional_Clock_Loop11>.Parsing architecture <rtl> of entity <fgpa_globals_viacq_regional_clock_loop11>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DiagramReset.vhd" into library workParsing entity <DiagramReset>.Parsing architecture <rtl> of entity <diagramreset>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForTopEnablesPortOnResTopEnablePassThru.vhd" into library workParsing entity <CustomArbForTopEnablesPortOnResTopEnablePassThru>.Parsing architecture <rtl> of entity <customarbfortopenablesportonrestopenablepassthru>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForSoftware_Trigger_ctl_12RHFpgaReadPortOnResbushold.vhd" into library workParsing entity <CustomArbForSoftware_Trigger_ctl_12RHFpgaReadPortOnResbushold>.Parsing architecture <rtl> of entity <customarbforsoftware_trigger_ctl_12rhfpgareadportonresbushold>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viSoftware_Trigger8.vhd" into library workParsing entity <CustomArbForOutPortPortOnResFGPA_Globals_viSoftware_Trigger8>.Parsing architecture <rtl> of entity <customarbforoutportportonresfgpa_globals_visoftware_trigger8>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Gen_Reset7.vhd" into library workParsing entity <CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Gen_Reset7>.Parsing architecture <rtl> of entity <customarbforoutportportonresfgpa_globals_viio_module_bksl_gen_reset7>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd" into library workParsing entity <CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Acq_Reset12>.Parsing architecture <rtl> of entity <customarbforoutportportonresfgpa_globals_viio_module_bksl_acq_reset12>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viFetch_Length9.vhd" into library workParsing entity <CustomArbForOutPortPortOnResFGPA_Globals_viFetch_Length9>.Parsing architecture <rtl> of entity <customarbforoutportportonresfgpa_globals_vifetch_length9>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viClear_T2H_DMA_Timeout10.vhd" into library workParsing entity <CustomArbForOutPortPortOnResFGPA_Globals_viClear_T2H_DMA_Timeout10>.Parsing architecture <rtl> of entity <customarbforoutportportonresfgpa_globals_viclear_t2h_dma_timeout10>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viBit00.vhd" into library workParsing entity <CustomArbForOutPortPortOnResFGPA_Globals_viBit00>.Parsing architecture <rtl> of entity <customarbforoutportportonresfgpa_globals_vibit00>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" into library workParsing entity <CustomArbForOutPortPortOnResFGPA_Globals_viAcq_Regional_Clock_Loop11>.Parsing architecture <rtl> of entity <customarbforoutportportonresfgpa_globals_viacq_regional_clock_loop11>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForMiteIoLikePortOnResInterface.vhd" into library workParsing entity <CustomArbForMiteIoLikePortOnResInterface>.Parsing architecture <rtl> of entity <customarbformiteiolikeportonresinterface>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForIO_Module_bksl_Xpoint_Switch_Write_ctl_0RHFpgaReadPortOnResbushold.vhd" into library workParsing entity <CustomArbForIO_Module_bksl_Xpoint_Switch_Write_ctl_0RHFpgaReadPortOnResbushold>.Parsing architecture <rtl> of entity <customarbforio_module_bksl_xpoint_switch_write_ctl_0rhfpgareadportonresbushold>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForIO_Module_bksl_Program_Onboard_Clock_ctl_11RHFpgaReadPortOnResbushold.vhd" into library workParsing entity <CustomArbForIO_Module_bksl_Program_Onboard_Clock_ctl_11RHFpgaReadPortOnResbushold>.Parsing architecture <rtl> of entity <customarbforio_module_bksl_program_onboard_clock_ctl_11rhfpgareadportonresbushold>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RHFpgaReadPortOnResbushold.vhd" into library workParsing entity <CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RHFpgaReadPortOnResbushold>.Parsing architecture <rtl> of entity <customarbforio_module_bksl_gen_reset_ctl_10rhfpgareadportonresbushold>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RHFpgaReadPortOnResbushold.vhd" into library workParsing entity <CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RHFpgaReadPortOnResbushold>.Parsing architecture <rtl> of entity <customarbforio_module_bksl_acq_reset_ctl_18rhfpgareadportonresbushold>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpgaReadPortOnResbushold.vhd" into library workParsing entity <CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpgaReadPortOnResbushold>.Parsing architecture <rtl> of entity <customarbforclear_t2h_dma_timeout_ctl_15rhfpgareadportonresbushold>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold.vhd" into library workParsing entity <CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold>.Parsing architecture <rtl> of entity <customarbforbit0_ctl_3rhfpgareadportonresbushold>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchInterfaceDmaRegisters.vhd" into library workParsing entity <ChinchInterfaceDmaRegisters>.Parsing architecture <behavior> of entity <chinchinterfacedmaregisters>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaSourceStreamStateController.vhd" into library workParsing entity <ChinchDmaSourceStreamStateController>.Parsing architecture <behavior> of entity <chinchdmasourcestreamstatecontroller>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaSinkStreamStateController.vhd" into library workParsing entity <ChinchDmaSinkStreamStateController>.Parsing architecture <behavior> of entity <chinchdmasinkstreamstatecontroller>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputController.vhd" into library workParsing entity <ChinchDmaOutputController>.Parsing architecture <rtl> of entity <chinchdmaoutputcontroller>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputController.vhd" into library workParsing entity <ChinchDmaInputController>.Parsing architecture <rtl> of entity <chinchdmainputcontroller>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" into library workParsing entity <bushold>.Parsing architecture <rtl> of entity <bushold>.

Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgIoPort2.vhd" into library workParsing package <PkgIoPort2>.Parsing package body <PkgIoPort2>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PacketSink.vhd" into library workParsing entity <PacketSink>.Parsing architecture <rtl> of entity <packetsink>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFpgaClipContainer.vhd" into library workParsing entity <NiLvFpgaClipContainer>.Parsing architecture <ClipContainer_VHDL> of entity <nilvfpgaclipcontainer>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaStockDcm.vhd" into library workParsing entity <NiFpgaStockDcm>.Parsing architecture <rtl> of entity <nifpgastockdcm>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" into library workParsing entity <NiFpgaAG_FPGA_Generate_and_Acquire>.Parsing architecture <vhdl_labview> of entity <nifpgaag_fpga_generate_and_acquire>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\IoPort2LvFpga.vhd" into library workParsing entity <IoPort2LvFpga>.Parsing architecture <rtl> of entity <ioport2lvfpga>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ddr2_infrastructure.vhd" into library workParsing entity <ddr2_infrastructure>.Parsing architecture <syn> of entity <ddr2_infrastructure>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchSinkStream.vhd" into library workParsing entity <ChinchSinkStream>.Parsing architecture <structure> of entity <chinchsinkstream>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchRegisterAccess.vhd" into library workParsing entity <ChinchRegisterAccess>.Parsing architecture <rtl> of entity <chinchregisteraccess>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchIrqInterface.vhd" into library workParsing entity <ChinchIrqInterface>.Parsing architecture <rtl> of entity <chinchirqinterface>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutput.vhd" into library workParsing entity <ChinchDmaOutput>.Parsing architecture <structure> of entity <chinchdmaoutput>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInput.vhd" into library workParsing entity <ChinchDmaInput>.Parsing architecture <structure> of entity <chinchdmainput>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchCommIfcArbiterBase.vhd" into library workParsing entity <CHInChCommIfcArbiterBase>.Parsing architecture <rtl> of entity <chinchcommifcarbiterbase>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" into library workParsing entity <TheWindow>.Parsing architecture <behavioral> of entity <thewindow>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20TimingEngine.vhd" into library workParsing entity <Puma20TimingEngine>.Parsing architecture <STRUCT> of entity <puma20timingengine>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" into library workParsing entity <Puma20DramMain>.Parsing architecture <Struct> of entity <puma20drammain>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20ClkDetect.vhd" into library workParsing entity <Puma20ClkDetect>.

Parsing architecture <rtl> of entity <puma20clkdetect>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgPuma20.vhd" into library workParsing package <PkgPuma20>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgLvFpgaConst.vhd" into library workParsing package <PkgLvFpgaConst>.Parsing package body <PkgLvFpgaConst>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ClockGenXilinxV5.vhd" into library workParsing entity <ClockGenXilinxV5>.Parsing architecture <RTL> of entity <clockgenxilinxv5>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaInterface.vhd" into library workParsing entity <ChinchLvFpgaInterface>.Parsing architecture <struct> of entity <chinchlvfpgainterface>.Parsing VHDL file "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" into library workParsing entity <Puma20Top>.Parsing architecture <rtl> of entity <puma20top>.

=========================================================================* HDL Elaboration *=========================================================================

Elaborating entity <Puma20Top> (architecture <rtl>) from library <work>.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" Line 387: <ibufds> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" Line 380: <ibufgds> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" Line 406: <obufds> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" Line 394: <ibufg> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" Line 400: <bufg> remains a black-box since it has no binding entity.

Elaborating entity <Puma20ClkDetect> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20ClkDetect.vhd" Line 163. Case statement is complete. others clause is never selected

Elaborating entity <Puma20TimingEngine> (architecture <STRUCT>) with generics from library <work>.

Elaborating entity <TheWindow> (architecture <behavioral>) from library <work>.WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" Line 389: Assignment to internal_rexpectediomodid_din ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" Line 390: Assignment to internal_rlvfpgainsertediomodid_din ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" Line 391: Assignment to internal_rlvfpgapcbtemp_din ignored, since the identifier is never used

Elaborating entity <NiFpgaStockDcm> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaClockManagerControl> (architecture <rtl>) with generics from library <work>.

INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaClockManagerControl.vhd" Line 331. Case statement is complete. others clause is never selected

Elaborating entity <DoubleSyncBoolAsyncIn> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DoubleSyncSlAsyncIn> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DoubleSyncAsyncInBase> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBool> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" Line 251: <bufg> remains a black-box since it has no binding entity.WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" Line 471: Assignment to io_modulea_apficlkbufrtolvthrubuf ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" Line 472: Assignment to chinchclkthrubuf ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" Line 473: Assignment to reliableclkinthrubuf ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" Line 474: Assignment to io_modulea_aacqclkbufrtolvthrubuf ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" Line 475: Assignment to io_modulea_agenclkbufrtolvthrubuf ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" Line 476: Assignment to rioclk40thrubuf ignored, since the identifier is never used

Elaborating entity <NiFpgaAG_FPGA_Generate_and_Acquire> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" Line 104: Using initial value "0000000000000000" for s_enum_3837 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" Line 105: Using initial value "0" for s_acq_regional_clock_loop_7377 since it is never assigned

Elaborating entity <XDataNode> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_00000001_TimedLoopDiagram> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" Line 57: Using initial value "0" for s_constant_7346 since it is never assigned

Elaborating entity <NiFpgaGlobalResHolderRead> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaGlobalResHolderRead> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_00000003_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaDoWrite> (architecture <rtl>) with generics from library <work>.



Elaborating entity <XDataNodeOut> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_TimedLoopControllerContainer_178> (architecture <rtl>) with generics from library <work>.

Elaborating entity <TimedLoopCore> (architecture <rtl>) with generics from library <work>.

Elaborating entity <TimedLoopDomainCrosser> (architecture <rtl>) with generics from library <work>.

Elaborating entity <HandshakeSLV_Ack> (architecture <struct>) with generics from library <work>.

Elaborating entity <HandshakeBase> (architecture <behavior>) with generics from library <work>.

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.

Elaborating entity <PulseSyncBool> (architecture <behavior>) from library <work>.

Elaborating entity <PulseSyncBase> (architecture <behavior>) from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimedLoopDomainCrosser.vhd" Line 270. Case statement is complete. others clause is never selected

Elaborating entity <HandshakeSLV> (architecture <struct>) with generics from library <work>.

Elaborating entity <TimedLoopController> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_00000018_TimedLoopDiagram> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" Line 61: Using initial value "0" for s_constant_13353 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" Line 62: Using initial value "0000000000000000" for s_fetch_length_5926 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" Line 69: Using initial value "0000000000000000" for s_hi_7298 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" Line 70: Using initial value "1" for s_y_10431 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" Line 71: Using initial value "0" for s_constant_11215 since it is never assigned

Elaborating entity <FloatingFeedbackGInit> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaRegisterCore> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaRegisterCoreBase> (architecture <rtl>) with generics from library <work>.




Elaborating entity <NiFpgaBoolOp> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvToInteger> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpCoerce> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpEnableHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpEnableHandlerSlv> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaGlobalResHolderWrite> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_0000001a_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaDiRead> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaLvJoinNumbers> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaLvJoinNumbers> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd" Line 27: Using initial value "1" for s_constant_167 since it is never assigned

Elaborating entity <resholder_r_opt> (architecture <rtl>) with generics from library <work>.




Elaborating entity <NiFpgaBoolOpNot> (architecture <rtl>) with generics from library <work>.


Elaborating entity <resholder_w_opt> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SubVICtlOrIndOpt> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SubVICtlOrIndOpt> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaSelect> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaSelect.vhd" Line 57: Using initial value '0' for cdummyoverflowloc since it is never assigned

Elaborating entity <NiLvFxpEnableHandlerSlv> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvDecrement> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpDecrement> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpSubtract> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpEnableHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvCompareToZero> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpCompareToZero> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpCompare> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCompare.vhd" Line 92: Using initial value "0" for cdummyfxp since it is never assigned

Elaborating entity <NiFpgaAG_00000029_CaseStructure_62> (architecture <vhdl_modgen>) from library <work>.

Elaborating entity <NiFpgaAG_00000029_CaseStructureFrame_0000> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructureFrame_0000.vhd" Line 28: Using initial value "00000000000000000000000000000000" for s_timeout_9575 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructureFrame_0000.vhd" Line 29: Using initial value "00000000000000000000000000000000" for s_timeout_9716 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructureFrame_0000.vhd" Line 39: Using initial value '0' for cerrorstatus since it is never assignedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructureFrame_0000.vhd" Line 42: Assignment to eo00000003 ignored, since the identifier is never usedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructureFrame_0000.vhd" Line 48: Using initial value '0' for cerrorstatus since it is never assignedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructureFrame_0000.vhd" Line 51: Assignment to eo00000005 ignored, since the identifier is never used

Elaborating entity <NiFpgaAG_00000029_CaseStructureFrame_0001> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_0000002c_SequenceFrame> (architecture <vhdl_labview>) from library <work>.


Elaborating entity <NiFpgaAG_00000043_TimedLoopDiagram> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" Line 152: Using initial value "0" for s_constant_7322 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" Line 215: Using initial value "0000000000000000" for s_y_10001 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" Line 216: Using initial value "0000000000000101" for s_y_10393 since it is never assigned

Elaborating entity <NiFpgaShiftReg> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaShiftReg> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaLocalResHolderRead> (architecture <rtl>) with generics from library <work>.



Elaborating entity <NiFpgaGlobalResHolderWrite> (architecture <rtl>) with generics from library <work>.


Elaborating entity <NiFpgaDiRead> (architecture <rtl>) with generics from library <work>.


Elaborating entity <NiFpgaLocalResHolderWrite> (architecture <rtl>) with generics from library <work>.


Elaborating entity <NiFpgaAG_0000004b_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiLvToInteger> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpCoerce> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvAdd> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpAdd> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvCompare> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpCompare> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_0000004d_CaseStructure_149> (architecture <vhdl_modgen>) from library <work>.

Elaborating entity <NiFpgaAG_0000004d_CaseStructureFrame_0000> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd" Line 33: Using initial value "0000000000000001" for s_enum_7134 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd" Line 34: Using initial value "0000000000000000" for s_f_7344 since it is never assigned

Elaborating entity <NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd" Line 27: Using initial value "1" for s_constant_167 since it is never assigned

Elaborating entity <NiFpgaAG_0000004d_CaseStructureFrame_0001> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd" Line 28: Using initial value "00000000000000000000000000000000" for s_timeout_3764 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd" Line 54: Using initial value '0' for cerrorstatus since it is never assignedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd" Line 57: Assignment to eo00000002 ignored, since the identifier is never used

Elaborating entity <NiFpgaAG_00000059_CaseStructureFrame_0000> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000059_CaseStructureFrame_0000.vhd" Line 26: Using initial value "0000000000000010" for s_enum_6118 since it is never assigned

Elaborating entity <NiFpgaAG_0000005a_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_00000059_CaseStructureFrame_0001> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000059_CaseStructureFrame_0001.vhd" Line 23: Using initial value "0000000000000000" for s_enum_4554 since it is never assignedINFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd" Line 116. Case statement is complete. others clause is never selected

Elaborating entity <NiFpgaAG_0000004d_CaseStructureFrame_0002> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd" Line 26: Using initial value "0" for s_io_module_bksl_onboard_clock_write_4327 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd" Line 27: Using initial value "0000000000000011" for s_enum_3079 since it is never assigned

Elaborating entity <NiFpgaAG_0000005d_SequenceFrame> (architecture <vhdl_labview>) from library <work>.


Elaborating entity <NiFpgaAG_0000005f_SequenceFrame> (architecture <vhdl_labview>) from library <work>.



Elaborating entity <NiFpgaAG_0000004d_CaseStructureFrame_0005> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd" Line 24: Using initial value "0000000000000001" for s_enum_3325 since it is never assigned

WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd" Line 25: Using initial value "0000000000000101" for s_f_3464 since it is never assigned


Elaborating entity <TimedLoopController> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_00000098_TimedLoopDiagram> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" Line 39: Using initial value "00000000000000000000000000000000" for s_timeout_11170 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" Line 40: Using initial value "00000000000000000000000000000000" for s_timeout_11195 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" Line 41: Using initial value "0" for s_constant_11391 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" Line 99: Using initial value '0' for cerrorstatus since it is never assignedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" Line 102: Assignment to eo00000004 ignored, since the identifier is never usedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" Line 131: Using initial value '0' for cerrorstatus since it is never assignedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" Line 134: Assignment to eo00000008 ignored, since the identifier is never used

Elaborating entity <NiFpgaAG_0000009c_CaseStructureFrame_0000> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_0000009c_CaseStructureFrame_0001> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" Line 34: Using initial value "00000000000000000000000000000000" for s_timeout_3920 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" Line 35: Using initial value "00000000000000000000000000000000" for s_timeout_7874 since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" Line 76: Using initial value '0' for cerrorstatus since it is never assignedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" Line 79: Assignment to eo00000005 ignored, since the identifier is never used

WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" Line 85: Using initial value '0' for cerrorstatus since it is never assignedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" Line 88: Assignment to eo00000007 ignored, since the identifier is never used


Elaborating entity <niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat> (architecture <vhdl_labview>) from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" Line 26: Using initial value "0" for s_constant_97 since it is never assigned



Elaborating entity <TimedLoopCore> (architecture <rtl>) with generics from library <work>.

Elaborating entity <TimedLoopDomainCrosser> (architecture <rtl>) with generics from library <work>.

Elaborating entity <InvisibleResholder> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFpgaStockDigitalOutput> (architecture <rtl>) with generics from library <work>.


Elaborating entity <FGPA_Globals_viBit00> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FGPA_Globals_viBit00.vhd" Line 33: Assignment to clkwrenableclr ignored, since the identifier is never used

Elaborating entity <FGPA_Globals_viIO_Module_bksl_Acq_Reset12> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd" Line 33: Assignment to clkwrenableclr ignored, since the identifier is never used

Elaborating entity <NiLvFpgaStockDigitalInput> (architecture <rtl>) with generics from library <work>.

Elaborating entity <TopEnablePassThru> (architecture <rtl>) with generics from library <work>.

Elaborating entity <FPGAwFIFOn0> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaBuiltInFifoResetControl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaFifoPushPopControl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaFifoPushPopControl> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn0.vhd" Line 233: <builtinfifocorefpgawfifon0> remains a black-box since it has no binding entity.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn0.vhd" Line 257: Net <iDisablePushFromClearControl> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn0.vhd" Line 271: Net <oDisablePopFromClearControl> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn0.vhd" Line 294: Net <oPopFromClearControl> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn0.vhd" Line 299: Net <iCountEmptyCountLoc[10]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn0.vhd" Line 303: Net <oCountFullCountLoc[10]> does not have a driver.

Elaborating entity <FPGAwFIFOn1> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn1.vhd" Line 233: <builtinfifocorefpgawfifon1> remains a black-box since it has no binding entity.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn1.vhd" Line 257: Net <iDisablePushFromClearControl> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn1.vhd" Line 271: Net <oDisablePopFromClearControl> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn1.vhd" Line 294: Net <oPopFromClearControl> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn1.vhd" Line 299: Net <iCountEmptyCountLoc[10]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn1.vhd" Line 303: Net <oCountFullCountLoc[10]> does not have a driver.

Elaborating entity <FGPA_Globals_viAcq_Regional_Clock_Loop11> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" Line 33: Assignment to clkwrenableclr ignored, since the identifier is never used

Elaborating entity <NiLvFpgaStockDigitalInput> (architecture <rtl>) with generics from library <work>.


Elaborating entity <bushold> (architecture <rtl>) with generics from library <work>.

Elaborating entity <HandshakeBaseResetCross> (architecture <rtl>) with generics from library <work>.


Elaborating entity <ResetSync> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBool> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBoolFallingEdge> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopFallingEdge> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ResetSync> (architecture <rtl>) with generics from library <work>.


Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 574: Using initial value 0 for rioclk40derived5x1c00mhzsrcount since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 575: Using initial value false for cregread since it is never assignedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 579: Assignment to ccount ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 580: Assignment to rioclk40derived5x1c00mhzwideread ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 581: Assignment to rioclk40derived5x1c00mhzwidewrite ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 591: Assignment to rioclk40derived5x1c00mhzwidedataout ignored, since the identifier is never usedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 743: Using initial value 0 for rioclk40srcount since it is never assignedWARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 744: Using initial value false for cregread since it is never assignedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 748: Assignment to ccount ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 749: Assignment to rioclk40wideread ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 750: Assignment to rioclk40widewrite ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 760: Assignment to rioclk40widedataout ignored, since the identifier is never usedWARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 1103: Assignment to chinchclkwidewrite ignored, since the identifier is never used

Elaborating entity <NiFpgaRegFrameworkShiftReg> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DoubleSyncBoolAsyncIn> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 573: Net <RioClk40Derived5x1C00MHzShifter.RioClk40Derived5x1C00MHzSrDataOut[31]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" Line 742: Net <RioClk40Shifter.RioClk40SrDataOut[31]> does not have a driver.

Elaborating entity <Interface> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ChinchDmaFifos> (architecture <struct>) from library <work>.

Elaborating entity <ChinchDmaInputFifoInterface> (architecture <structure>) with generics from library <work>.

Elaborating entity <ChinchDmaComponentEnableChain> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaFifoClearControl> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoClearControl.vhd" Line 229. Case statement is complete. others clause is never selected

Elaborating entity <DoubleSyncBool> (architecture <behavior>) from library <work>.

Elaborating entity <DoubleSyncBase> (architecture <behavior>) with generics from library <work>.

Elaborating entity <NiFpgaFifoPortReset> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaPulseSyncBaseWrapper> (architecture <rtl>) from library <work>.

Elaborating entity <InStrmFifo> (architecture <rtl>) with generics from library <work>.

Elaborating entity <InStrmFifoFlags> (architecture <rtl>) with generics from library <work>.

Elaborating entity <FifoPtrClockCrossing> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FifoPtrClockCrossing.vhd" Line 154. Case statement is complete. others clause is never selected

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmFifoFlags.vhd" Line 457: Range is empty (null range)WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmFifoFlags.vhd" Line 456: Range is empty (null range)WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmFifoFlags.vhd" Line 456: Assignment ignored

Elaborating entity <InStrmRAMArray> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmRAMArray.vhd" Line 211: Range is empty (null range)

Elaborating entity <ADPRAM36K> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmRAMArray.vhd" Line 256: Range is empty (null range)

Elaborating entity <NiFpgaFifoCountControl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ChinchDmaComponentStreamStateEnableChain> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ChinchDmaComponentStreamStateEnableChain> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ChinchDmaComponentStateTransitionEnableChain> (architecture <rtl>) from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStateTransitionEnableChain.vhd" Line 223. Case statement is complete. others clause is never selected




Elaborating entity <HandshakeBase> (architecture <behavior>) with generics from library <work>.

Elaborating entity <ChinchDmaComponentInputStateHolder> (architecture <rtl>) from library <work>.

Elaborating entity <ChinchDmaOutputFifoInterface> (architecture <structure>) with generics from library <work>.

Elaborating entity <ChinchDmaComponentEnableChain> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaFifoClearControl> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoClearControl.vhd" Line 229. Case statement is complete. others clause is never selected

Elaborating entity <NiFpgaFifoPortReset> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaFifoPopBuffer> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:92 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPopBuffer.vhd" Line 212: cpendingpushes should be on the sensitivity list of the process

Elaborating entity <NiFpgaFlipFlopFifo> (architecture <rtl>) with generics from library <work>.

Elaborating entity <OutStrmFifo> (architecture <rtl>) with generics from library <work>.

Elaborating entity <OutStrmFifoFlags> (architecture <rtl>) with generics from library <work>.

Elaborating entity <FifoPtrClockCrossing> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FifoPtrClockCrossing.vhd" Line 154. Case statement is complete. others clause is never selected


Elaborating entity <OutStrmDPRAM> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DPRAM64Bits> (architecture <rtl>) from library <work>.

Elaborating entity <DPRAM32Bits> (architecture <rtl>) from library <work>.


Elaborating entity <NiFpgaFifoCountControl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ChinchDmaComponentOutputStateHolder> (architecture <rtl>) from library <work>.



Elaborating entity <ChinchLvFpgaIrq> (architecture <rtl>) from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaIrq.vhd" Line 370. Case statement is complete. others clause is never selected




Elaborating entity <HandshakeBase> (architecture <behavior>) with generics from library <work>.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 48: Net <DmaClkArray[3]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 50: Net <DmaRwDataInArray[2][63]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 52: Net <DmaRwTimeoutArray[3][31]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 53: Net <DmaRwEnableInArray[3]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 55: Net <DmaRwEnableOutClearArray[3]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 56: Net <DmaCtEnableInArray[0]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 58: Net <DmaCtEnableOutClearArray[0]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 60: Net <DmaStreamStateEnableInArray[3]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 62: Net <DmaStreamStateEnableClearArray[3]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 64: Net <dStreamStateEnableInArray[3]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 66: Net <dStreamStateEnableClearArray[3]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 69: Net <dStartRequestEnableInArray[3]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 71: Net <dStartRequestEnableClearArray[3]> does not have a driver.

WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 72: Net <dStopRequestEnableInArray[3]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 74: Net <dStopRequestEnableClearArray[3]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 75: Net <dStopWithFlushRequestEnableInArray[2]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 77: Net <dStopWithFlushRequestEnableClearArray[2]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 78: Net <dStopWithFlushRequestTimeoutArray[2][31]> does not have a driver.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" Line 92: Net <iIrqOutArray[0]_IrqNum[4]> does not have a driver.

Elaborating entity <FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopEnInIClk> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ViControl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SafeBusCrossing> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SafeBusCrossing.vhd" Line 215. Case statement is complete. others clause is never selectedINFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ViControl.vhd" Line 562. Case statement is complete. others clause is never selected

Elaborating entity <DiagramReset> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SafeBusCrossing> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SafeBusCrossing.vhd" Line 215. Case statement is complete. others clause is never selected


Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DiagramReset.vhd" Line 710. Case statement is complete. others clause is never selected

Elaborating entity <ViSignature> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaCtrlIndRegister.vhd" Line 59: Range is empty (null range)WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaCtrlIndRegister.vhd" Line 60: Range is empty (null range)WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PkgNiUtilities.vhd" Line 403: Range is empty (null range)

Elaborating entity <NiFpgaCtrlIndRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaHostAccessibleRegister> (architecture <rtl>) with generics from library <work>.


Elaborating entity <NiFpgaHostAccessibleRegister> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaCtrlIndRegister.vhd" Line 56: Range is empty (null range)WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaCtrlIndRegister.vhd" Line 57: Range is empty (null range)






Elaborating entity <CustomArbForOutPortPortOnResFGPA_Globals_viBit00> (architecture <rtl>) with generics from library <work>.

Elaborating entity <HandshakeWithResetValueSLV> (architecture <struct>) with generics from library <work>.

Elaborating entity <HandshakeWithResetValueBase> (architecture <behavior>) with generics from library <work>.


Elaborating entity <CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Gen_Reset7> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DoubleSyncWithResetValueSLV> (architecture <struct>) with generics from library <work>.

Elaborating entity <DoubleSyncWithResetValueSL> (architecture <behavior>) with generics from library <work>.

Elaborating entity <CustomArbForTopEnablesPortOnResTopEnablePassThru> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaTopEnInSyncForExternalClk> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaTopEnInSyncForExternalClk.vhd" Line 225. Case statement is complete. others clause is never selectedINFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaTopEnInSyncForExternalClk.vhd" Line 392. Case statement is complete. others clause is never selected

Elaborating entity <NiFpgaTopEnInSyncForExternalClk> (architecture <rtl>) with generics from library <work>.

INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaTopEnInSyncForExternalClk.vhd" Line 225. Case statement is complete. others clause is never selectedINFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaTopEnInSyncForExternalClk.vhd" Line 392. Case statement is complete. others clause is never selected

Elaborating entity <DoubleSyncSLV> (architecture <struct>) with generics from library <work>.

Elaborating entity <DoubleSyncSL> (architecture <behavior>) from library <work>.

Elaborating entity <CustomArbForOutPortPortOnResFGPA_Globals_viSoftware_Trigger8> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForOutPortPortOnResFGPA_Globals_viFetch_Length9> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Acq_Reset12> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForIO_Module_bksl_Program_Onboard_Clock_ctl_11RHFpgaReadPortOnResbushold> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbRW.vhd" Line 196: Range is empty (null range)WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbRW.vhd" Line 216: Assignment ignoredWARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbRW.vhd" Line 219: Range is empty (null range)WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbRW.vhd" Line 219: Assignment ignoredWARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbRW.vhd" Line 226: Range is empty (null range)WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbRW.vhd" Line 224: Range is empty (null range)WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbRW.vhd" Line 224: Assignment ignored

Elaborating entity <CustomArbForIO_Module_bksl_Xpoint_Switch_Write_ctl_0RHFpgaReadPortOnResbushold> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold> (architecture <rtl>) with generics from library <work>.








Elaborating entity <CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RHFpgaReadPortOnResbushold> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForSoftware_Trigger_ctl_12RHFpgaReadPortOnResbushold> (architecture <rtl>) with generics from library <work>.


Elaborating entity <CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpgaReadPortOnResbushold> (architecture <rtl>) with generics from library <work>.


Elaborating entity <CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RHFpgaReadPortOnResbushold> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForOutPortPortOnResFGPA_Globals_viAcq_Regional_Clock_Loop11> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForOutPortPortOnResFGPA_Globals_viClear_T2H_DMA_Timeout10> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForMiteIoLikePortOnResInterface> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForMiteIoLikePortOnResInterface.vhd" Line 53: Assignment to interfaceclockregportin ignored, since the identifier is never used

Elaborating entity <NiLvFpgaClipContainer> (architecture <ClipContainer_VHDL>) from library <work>.

Elaborating entity <Ni6587ConnectorSerdes> (architecture <RTL>) from library <work>.

Elaborating entity <Ni6587CoreSerdes> (architecture <RTL>) from library <work>.

Elaborating entity <Ni6587Base> (architecture <RTL>) from library <work>.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" Line 70: <ibufds_diff_out> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" Line 77: <obuftds> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" Line 84: <ibufds> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" Line 90: <ibufgds> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" Line 96: <ibufg> remains a black-box since it has no binding entity.

Elaborating entity <AcquisitionEngine> (architecture <RTL>) from library <work>.

Elaborating entity <Deserializer> (architecture <RTL>) with generics from library <work>.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" Line 56: <iodelay> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" Line 77: <iserdes_nodelay> remains a black-box since it has no binding entity.

Elaborating entity <GenerationEngine> (architecture <RTL>) from library <work>.

Elaborating entity <Serializer> (architecture <RTL>) with generics from library <work>.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" Line 54: <oserdes> remains a black-box since it has no binding entity.

Elaborating entity <I2cReadWrite> (architecture <rtl>) from library <work>.

Elaborating entity <I2cIssueCycle> (architecture <behavioral>) from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\I2cIssueCycle.vhd" Line 96. Case statement is complete. others clause is never selectedINFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\I2cReadWrite.vhd" Line 187. Case statement is complete. others clause is never selected

Elaborating entity <CrossSwitchSourceSelect> (architecture <rtl>) from library <work>.

Elaborating entity <CrossSwitchInterface> (architecture <rtl>) from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CrossSwitchInterface.vhd" Line 194. Case statement is complete. others clause is never selected

Elaborating entity <TimingEngine> (architecture <RTL>) from library <work>.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimingEngine.vhd" Line 59: <idelayctrl> remains a black-box since it has no binding entity.

Elaborating entity <RegionalClockBuf> (architecture <RTL>) with generics from library <work>.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\RegionalClockBuf.vhd" Line 50: <iodelay> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\RegionalClockBuf.vhd" Line 70: <bufio> remains a black-box since it has no binding entity.

WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\RegionalClockBuf.vhd" Line 75: <bufr> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimingEngine.vhd" Line 66: <bufgce> remains a black-box since it has no binding entity.

Elaborating entity <Puma20DramMain> (architecture <Struct>) with generics from library <work>.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" Line 308: <obufds> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" Line 315: <ibufds> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" Line 209: <puma20ioport2glue> remains a black-box since it has no binding entity.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" Line 232: <pumafixedlogic> remains a black-box since it has no binding entity.

Elaborating entity <ChinchLvFpgaInterface> (architecture <struct>) with generics from library <work>.WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaInterface.vhd" Line 269: Range is empty (null range)WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaInterface.vhd" Line 335: Range is empty (null range)

Elaborating entity <ChinchRegisterAccess> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchRegisterAccess.vhd" Line 620. Case statement is complete. others clause is never selectedINFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchRegisterAccess.vhd" Line 716. Case statement is complete. others clause is never selected

Elaborating entity <ChinchDmaInput> (architecture <structure>) with generics from library <work>.

Elaborating entity <ChinchDmaInputController> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputController.vhd" Line 859. Case statement is complete. others clause is never selectedINFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputController.vhd" Line 1299. Case statement is complete. others clause is never selected

Elaborating entity <ChinchInterfaceDmaRegisters> (architecture <behavior>) with generics from library <work>.

Elaborating entity <ChinchDmaSourceStreamStateController> (architecture <behavior>) from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaSourceStreamStateController.vhd" Line 410. Case statement is complete. others clause is never selected

Elaborating entity <ChinchDmaInput> (architecture <structure>) with generics from library <work>.

Elaborating entity <ChinchDmaInputController> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputController.vhd" Line 859. Case statement is complete. others clause is never selected

INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputController.vhd" Line 1299. Case statement is complete. others clause is never selected


Elaborating entity <ChinchDmaOutput> (architecture <structure>) with generics from library <work>.

Elaborating entity <ChinchDmaOutputController> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputController.vhd" Line 494. Case statement is complete. others clause is never selected

Elaborating entity <OutStrmOutputHandler> (architecture <rtl>) with generics from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\OutStrmOutputHandler.vhd" Line 369. Case statement is complete. others clause is never selected


Elaborating entity <ChinchDmaSinkStreamStateController> (architecture <behavior>) from library <work>.

Elaborating entity <ChinchIrqInterface> (architecture <rtl>) with generics from library <work>.

Elaborating entity <IoPort2LvFpga> (architecture <rtl>) from library <work>.

Elaborating entity <PacketSink> (architecture <rtl>) from library <work>.INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PacketSink.vhd" Line 189. Case statement is complete. others clause is never selected

Elaborating entity <CHInChCommIfcArbiterBase> (architecture <rtl>) with generics from library <work>.

Elaborating entity <StrmArbiter> (architecture <rtl>) with generics from library <work>.WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\StrmArbiter.vhd" Line 185: Assignment to saccgntlocuns ignored, since the identifier is never usedWARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\StrmArbiter.vhd" Line 133: Range is empty (null range)INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\StrmArbiter.vhd" Line 337. Case statement is complete. others clause is never selectedINFO:HDLCompiler:679 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchCommIfcArbiterBase.vhd" Line 653. Case statement is complete. others clause is never selectedWARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchCommIfcArbiterBase.vhd" Line 114: Net <sOutStrmsArbHighDone> does not have a driver.WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" Line 303: <ioport2wrapper> remains a black-box since it has no binding entity.

Elaborating entity <ClockGenXilinxV5> (architecture <RTL>) with generics from library <work>.WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ClockGenXilinxV5.vhd" Line 102: Net <bLclClockGenDebug[1][7]> does not have a driver.

WARNING:Xst:2972 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 301. All outputs of instance <n_N9Cud_de_sortie_96_Diagram> of block <XDataNodeOut> are unconnected in block <NiFpgaAG_00000001_TimedLoopDiagram>. Underlying logic will be removed.WARNING:Xst:2972 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 662. All outputs of instance <n_N9Cud_de_sortie_8116_Diagram> of block <XDataNodeOut> are unconnected in block <NiFpgaAG_00000018_TimedLoopDiagram>. Underlying logic will be removed.WARNING:Xst:2972 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1485. All outputs of instance <n_N9Cud_de_sortie_4552_Diagram> of block <XDataNodeOut> are unconnected in block <NiFpgaAG_00000043_TimedLoopDiagram>. Underlying logic will be removed.WARNING:Xst:2972 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" line 240. All outputs of instance <n_N9Cud_de_sortie_14533_Diagram> of block <XDataNodeOut> are unconnected in block <NiFpgaAG_00000098_TimedLoopDiagram>. Underlying logic will be removed.

=========================================================================* HDL Synthesis *=========================================================================

Synthesizing Unit <Puma20Top>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 725: Output port <TopLevelClkOut> of the instance <Puma20Window> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 725: Output port <tDiagramActive> of the instance <Puma20Window> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 725: Output port <ReliableClkOut> of the instance <Puma20Window> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 725: Output port <aDiagramReset> of the instance <Puma20Window> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 725: Output port <rDerivedClockLostLockError> of the instance <Puma20Window> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 725: Output port <aSafeToEnableGatedClks> of the instance <Puma20Window> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 957: Output port <mFixedRegsDataOE> of the instance <PumaFixedLogicx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 957: Output port <mFixedRegsNotReady> of the instance <PumaFixedLogicx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 957: Output port <mFixedRegsReadyOE> of the instance <PumaFixedLogicx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientInputStreamInterfaceToFifo[0]_BytesRead> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientInputStreamInterfaceToFifo[0]_StreamState> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientOutputStreamInterfaceToFifo[0]_WriteLengthInBytes> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientOutputStreamInterfaceToFifo[0]_FifoData> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientOutputStreamInterfaceToFifo[0]_NumWriteSpaces> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientOutputStreamInterfaceToFifo[0]_StreamState> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientInputStreamInterfaceToFifo[0]_DmaReset> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientInputStreamInterfaceToFifo[0]_Pop> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientInputStreamInterfaceToFifo[0]_UpdateByteLanePtr> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientOutputStreamInterfaceToFifo[0]_DmaReset> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientOutputStreamInterfaceToFifo[0]_FifoWrite> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientOutputStreamInterfaceToFifo[0]_RsrvWriteSpaces> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1046: Output port <bClientOutputStreamInterfaceToFifo[0]_ReportDisabledToDiagram> of the instance <ChinchLvFpgaInterfacex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1104: Output port <bRegAddr> of the instance <IoPort2Wrapperx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1104: Output port <bRegWriteData> of the instance <IoPort2Wrapperx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1104: Output port <bRegStart> of the instance <IoPort2Wrapperx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20Top.vhd" line 1104: Output port <bRegWrite> of the instance <IoPort2Wrapperx> is unconnected or connected to loadless signal. Found 1-bit register for signal <fRefClkPrsnt>. Found 1-bit register for signal <sRefClkPrsnt_ms>. Found 1-bit register for signal <sRefClkPrsnt>. Found 1-bit register for signal <fRefClkPrsnt_ms>. Found 1-bit register for signal <aPxieSync100>. Found 1-bit register for signal <bBusReset_ms>. Found 1-bit register for signal <bBusReset>. Found 1-bit tristate buffer for signal <aRsvd<1>> created at line 568 Found 1-bit tristate buffer for signal <aRsvd<0>> created at line 568 Found 1-bit tristate buffer for signal <aSclToTB> created at line 571 Found 1-bit tristate buffer for signal <aSdaToTB> created at line 572

Found 1-bit tristate buffer for signal <aFPGA_1V_ModeCntrl> created at line 583 Summary:

inferred 7 D-type flip-flop(s).inferred 5 Tristate(s).

Unit <Puma20Top> synthesized.

Synthesizing Unit <Puma20ClkDetect>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20ClkDetect.vhd". Found 1-bit register for signal <bSafeStart>. Found 4-bit register for signal <bDetectState>. Found 3-bit register for signal <bFixedDelayCount>. Found 1-bit register for signal <bWriteValue>. Found 1-bit register for signal <bClkDetectDoneLcl>. Found 1-bit register for signal <bPxieClk100DetectedLcl>. Found 1-bit register for signal <pSampleValue_ms>. Found 1-bit register for signal <pSampleValue>. Found 1-bit register for signal <bReadBackValue_ms>. Found 1-bit register for signal <bReadBackValue>. Found 1-bit register for signal <bPll200Locked_ms>. Found 1-bit register for signal <bPll200Locked>. Found 1-bit register for signal <bSafeStart_ms>. Found finite state machine <FSM_0> for signal <bDetectState>. ----------------------------------------------------------------------- | States | 10 | | Transitions | 17 | | Inputs | 5 | | Outputs | 6 | | Clock | BusClk (rising_edge) | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 3-bit adder for signal <bFixedDelayCount[2]_GND_27_o_add_8_OUT> created at line 1241. Summary:

inferred 1 Adder/Subtractor(s).inferred 14 D-type flip-flop(s).inferred 3 Multiplexer(s).inferred 1 Finite State Machine(s).

Unit <Puma20ClkDetect> synthesized.

Synthesizing Unit <Puma20TimingEngine>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20TimingEngine.vhd". Found 1-bit register for signal <bLockPllToOsc100>. Found 32-bit register for signal <bPllRstReg>. Found 1-bit register for signal <rPllLockedNoRst_ms>. Found 1-bit register for signal <rPllLockedNoRst>. Found 1-bit register for signal <rBaseClocksValidInt>. Found 14-bit register for signal <rLockedFilterCount>. Found 1-bit register for signal <rLastPllLocked>. Found 1-bit register for signal <rPllLockFallingEdge>. Found 1-bit register for signal <rPll200UnlockedStickyLcl>. Found 1-bit register for signal <SlowBusClkLcl>.

Found 1-bit register for signal <bSlowClkCnt>. Found 1-bit register for signal <bLockPllToOsc100_ms>. Found 2-bit subtractor for signal <n0043> created at line 278. Found 14-bit subtractor for signal <GND_28_o_GND_28_o_sub_4_OUT<13:0>> created at line 237. Summary:

inferred 2 Adder/Subtractor(s).inferred 56 D-type flip-flop(s).inferred 1 Multiplexer(s).

Unit <Puma20TimingEngine> synthesized.

Synthesizing Unit <TheWindow>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd". Set property "S = TRUE" for signal <RioClk40Derived5x1C00MHz>. Set property "S = TRUE" for signal <RioClk40Derived5x1C00MHzClkFXFromDCM0>.WARNING:Xst:647 - Input <rExpectedIoModId> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rLvFpgaInsertedIoModId> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rLvFpgaPcbTemp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <PxiClk10Fpga> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DramClkDiv100> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DramClk200> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DStarAClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <LvFpgaIoModClipClock0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <LvFpgaIoModClipClock1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aPxi10Dio> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <StarClkpin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aPxieDStarB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <aPxieSync100> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rLvFpgaIoModPresent> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rLvFpgaIoModPowerGd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rLvFpgaIoModPowerEn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rLvFpgaIoModVeepromEn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rLvFpgaIoModIoEn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClk100PllUnlockedSticky> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[15]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[14]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[13]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[12]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[11]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[10]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[9]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[8]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[7]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[6]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[5]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[4]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[3]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[2]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[1]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[0]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <STATUS> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <rBufgEn> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <aBufgEn> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <CLK90> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <CLK180> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <CLK270> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <CLK2X> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <CLK2X180> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <CLKDV> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <CLKFX180> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 414: Output port <PSDONE> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 514: Output port <rAssumeExternalClkInvalid> of the instance <theVI> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 606: Output port <IO_Module_aSePfiIn0> of the instance <theCLIPs> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 606: Output port <IO_Module_aSePfiIn1> of the instance <theCLIPs> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 606: Output port <IO_Module_aSePfiIn2> of the instance <theCLIPs> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 606: Output port <IO_Module_aSePfiIn3> of the instance <theCLIPs> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TheWindow.vhd" line 606: Output port <IO_Module_PfiClkBufRToLv> of the instance <theCLIPs> is unconnected or connected to loadless signal. Found 1-bit tristate buffer for signal <local_aLvTrig0_driver> created at line 146 Found 1-bit tristate buffer for signal <local_aLvTrig1_driver> created at line 149 Found 1-bit tristate buffer for signal <local_aLvTrig2_driver> created at line 152 Found 1-bit tristate buffer for signal <local_aLvTrig3_driver> created at line 155 Found 1-bit tristate buffer for signal <local_aLvTrig4_driver> created at line 158 Found 1-bit tristate buffer for signal <local_aLvTrig5_driver> created at line 161 Found 1-bit tristate buffer for signal <local_aLvTrig6_driver> created at line 164 Found 1-bit tristate buffer for signal <local_aLvTrig7_driver> created at line 167 Summary:

inferred 8 Tristate(s).Unit <TheWindow> synthesized.

Synthesizing Unit <NiFpgaStockDcm>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaStockDcm.vhd". Summary:

no macro.Unit <NiFpgaStockDcm> synthesized.

Synthesizing Unit <NiFpgaClockManagerControl>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaClockManagerControl.vhd". Set property "syn_keep = true" for signal <aBufgEnLoc>. Found 6-bit register for signal <rTimerCount>. Found 1-bit register for signal <rRstLoc>. Found 1-bit register for signal <rDerivedClkValidLoc>. Found 3-bit register for signal <rCmState>.INFO:Xst:1799 - State waitforbufgenassertionduration is never reached in FSM <rCmState>.INFO:Xst:1799 - State waitforbufgendeassertionduration is never reached in FSM <rCmState>. Found finite state machine <FSM_1> for signal <rCmState>. ----------------------------------------------------------------------- | States | 6 | | Transitions | 11 | | Inputs | 3 | | Outputs | 3 | | Clock | ReliableClk (rising_edge) | | Power Up State | waitforclkintobecomevalid | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 6-bit subtractor for signal <GND_39_o_GND_39_o_sub_18_OUT<5:0>> created at line 352. Found 1-bit 3-to-1 multiplexer for signal <rDerivedClkValidAssert> created at line 261. Found 1-bit 3-to-1 multiplexer for signal <rDerivedClkValidDeassert> created at line 261. Summary:


Unit <NiFpgaClockManagerControl> synthesized.

Synthesizing Unit <DoubleSyncBoolAsyncIn_1>.

Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncBoolAsyncIn.vhd". Summary:

no macro.Unit <DoubleSyncBoolAsyncIn_1> synthesized.

Synthesizing Unit <DoubleSyncSlAsyncIn>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncSlAsyncIn.vhd". Summary:

no macro.Unit <DoubleSyncSlAsyncIn> synthesized.

Synthesizing Unit <DoubleSyncAsyncInBase>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncAsyncInBase.vhd". Set property "syn_maxfan = 1000000" for signal <oSig_ms>. Set property "syn_keep = true" for signal <oSig_ms>. Summary:

no macro.Unit <DoubleSyncAsyncInBase> synthesized.

Synthesizing Unit <DFlop_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlop.vhd".WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored.WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored. Set property "use_clock_enable = yes" for signal <cQ>. Summary:

no macro.Unit <DFlop_1> synthesized.

Synthesizing Unit <DFlopBool_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlopBool.vhd". Set property "syn_preserve = true". Summary:

no macro.Unit <DFlopBool_1> synthesized.

Synthesizing Unit <NiFpgaAG_FPGA_Generate_and_Acquire>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 648: Output port <oClkTimeOut> of the instance <n_Boucle_cadencE9e_43> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 648: Output port <iClkLoopinit> of the instance <n_Boucle_cadencE9e_43> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 677: Output port <cErrorOut> of the instance <n_N9Cud_de_sortie_78_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 752: Output port <oClkTimeOut> of the instance <n_Boucle_cadencE9e_8065> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 752: Output port <iClkLoopinit> of the instance <n_Boucle_cadencE9e_8065> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 781: Output port <cErrorOut> of the instance <n_N9Cud_de_sortie_8098_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 923: Output port <iClkTimeOut> of the instance <n_Boucle_cadencE9e_4094> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 959: Output port <cErrorOut> of the instance <n_N9Cud_de_sortie_4534_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1012: Output port <oClkTimeOut> of the instance <n_Boucle_cadencE9e_14482> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1012: Output port <iClkLoopinit> of the instance <n_Boucle_cadencE9e_14482> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1037: Output port <cErrorOut> of the instance <n_N9Cud_de_sortie_14515_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1415: Output port <iCountEmptyCount> of the instance <FPGAwFIFOn0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1415: Output port <oCountFullCount> of the instance <FPGAwFIFOn0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1415: Output port <oReturnTopEnIn> of the instance <FPGAwFIFOn0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1415: Output port <cClearEnableOut> of the instance <FPGAwFIFOn0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1415: Output port <iCountEnableOut> of the instance <FPGAwFIFOn0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1415: Output port <oCountEnableOut> of the instance <FPGAwFIFOn0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1473: Output port <iCountEmptyCount> of the instance <FPGAwFIFOn1> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1473: Output port <oCountFullCount> of the instance <FPGAwFIFOn1> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1473: Output port <oReturnTopEnIn> of the instance <FPGAwFIFOn1> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1473: Output port <cClearEnableOut> of the instance <FPGAwFIFOn1> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1473: Output port <iCountEnableOut> of the instance <FPGAwFIFOn1> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 1473: Output port <oCountEnableOut> of the instance <FPGAwFIFOn1> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2222: Output port <rDataValueOut> of the instance <IO_Module_bksl_Xpoint_Switch_Write_ctl_0> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2255: Output port <rDataValueOut> of the instance <IO_Module_bksl_Gen_IO_Clock_Source_ctl_1> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2288: Output port <rDataValueOut> of the instance <IO_Module_bksl_Xpoint_Switch_Ready_ind_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2321: Output port <rDataValueOut> of the instance <Bit0_ctl_3> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2354: Output port <rDataValueOut> of the instance <Bit1_ctl_4> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2387: Output port <rDataValueOut> of the instance <Bit2_ctl_5> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2420: Output port <rDataValueOut> of the instance <Bit3_ctl_6> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2453: Output port <rDataValueOut> of the instance <Bit4_ctl_7> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2486: Output port <rDataValueOut> of the instance <Bit5_ctl_8> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2519: Output port <rDataValueOut> of the instance <Bit6_ctl_9> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2552: Output port <rDataValueOut> of the instance <IO_Module_bksl_Gen_Reset_ctl_10> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2585: Output port <rDataValueOut> of the instance <Software_Trigger_ctl_12> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2618: Output port <rDataValueOut> of the instance <Fetch_Length_ctl_13> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2651: Output port <rDataValueOut> of the instance <T2H_DMA_Timeout_ind_14> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2684: Output port <rDataValueOut> of the instance <Clear_T2H_DMA_Timeout_ctl_15> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2717: Output port <rDataValueOut> of the instance <Acq_Regional_Clock_Loop_ind_16> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2750: Output port <rDataValueOut> of the instance <IO_Module_bksl_Acq_IO_Clock_Source_ctl_17> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2783: Output port <rDataValueOut> of the instance <IO_Module_bksl_Acq_Reset_ctl_18> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_FPGA_Generate_and_Acquire.vhd" line 2816: Output port <rDataValueOut> of the instance <IO_Module_bksl_Program_Onboard_Clock_ctl_11> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_FPGA_Generate_and_Acquire> synthesized.

Synthesizing Unit <XDataNode>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\XDataNode.vhd".WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <XDataNode> synthesized.

Synthesizing Unit <NiFpgaAG_00000001_TimedLoopDiagram>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd".WARNING:Xst:647 - Input <iteration> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 102: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_entrE9e_106_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 115: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_753> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 133: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_1270> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 151: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_1282> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 169: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_1289> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 187: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_1298> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 205: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_1306> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 223: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_4263> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 241: Output port <enable_out> of the instance <n_NiFpgaAG_00000003_SequenceFrame_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 253: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_1314> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 271: Output port <enable_out> of the instance <n_NiFpgaAG_00000005_SequenceFrame_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 301: Output port <cErrorOut> of the instance <n_N9Cud_de_sortie_96_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000001_TimedLoopDiagram.vhd" line 301: Output port <cEnableOut> of the instance <n_N9Cud_de_sortie_96_Diagram> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_00000001_TimedLoopDiagram> synthesized.

Synthesizing Unit <NiFpgaGlobalResHolderRead_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaGlobalResHolderRead.vhd".WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaGlobalResHolderRead_1> synthesized.

Synthesizing Unit <NiFpgaGlobalResHolderRead_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaGlobalResHolderRead.vhd".WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaGlobalResHolderRead_2> synthesized.

Synthesizing Unit <NiFpgaAG_00000003_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000003_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000003_SequenceFrame.vhd" line 30: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3315_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000003_SequenceFrame.vhd" line 30: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3315_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000003_SequenceFrame.vhd" line 30: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3315_Diagram> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_00000003_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaDoWrite_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaDoWrite.vhd".WARNING:Xst:647 - Input <cFromEnableResource> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:653 - Signal <cToEnableResource> is used but never assigned. This sourceless signal will be automatically connected to value GND. Summary:

inferred 1 Multiplexer(s).Unit <NiFpgaDoWrite_1> synthesized.

Synthesizing Unit <NiFpgaAG_00000005_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 72: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 72: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 72: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 90: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 90: Output port <cToEnableResource> of the instance

<n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 90: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 108: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_3> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 108: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_3> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 108: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_3> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 126: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_4> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 126: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_4> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 126: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_4> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 144: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_5> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 144: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_5> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 144: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_5> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 162: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_6> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 162: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_6> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 162: Output port <cEnableOut> of the instance

<n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_6> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 180: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_7> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 180: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_7> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000005_SequenceFrame.vhd" line 180: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_1536_Diagram_7> is unconnected or connected to loadless signal. Summary:




Synthesizing Unit <XDataNodeOut>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\XDataNodeOut.vhd".WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <XDataNodeOut> synthesized.

Synthesizing Unit <NiFpgaAG_TimedLoopControllerContainer_178>.

Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_178.vhd".WARNING:Xst:647 - Input <iClkFromResTopEnablePassThruTopEnables<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <iClkFromResTopEnablePassThruTopEnables<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <iClkSubdiag_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_178.vhd" line 71: Output port <oEnableOut> of the instance <TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_TimedLoopControllerContainer_178> synthesized.

Synthesizing Unit <TimedLoopCore_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimedLoopCore.vhd". Summary:

no macro.Unit <TimedLoopCore_1> synthesized.

Synthesizing Unit <TimedLoopDomainCrosser_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimedLoopDomainCrosser.vhd". Found 1-bit register for signal <oLEnableOut>. Found 1-bit register for signal <iEnableClrDelayed>. Found 3-bit register for signal <EnableInAndClr.IClkIsExternal.iEnableInState>. Found 3-bit register for signal <iEnableInDelays>. Found 2-bit register for signal <iEoState>. Found finite state machine <FSM_2> for signal <EnableInAndClr.IClkIsExternal.iEnableInState>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 19 | | Inputs | 4 | | Outputs | 3 | | Clock | IClk (rising_edge) | | Reset | aReset (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_3> for signal <iEoState>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 6 | | Inputs | 2 | | Outputs | 1 |

| Clock | IClk (rising_edge) | | Reset | aReset (positive) | | Reset type | asynchronous | | Reset State | waitingforloopenableoutassertion | | Power Up State | waitingforloopenableoutassertion | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit 5-to-1 multiplexer for signal <iLoopReady> created at line 221. Summary:

inferred 5 D-type flip-flop(s).inferred 13 Multiplexer(s).inferred 2 Finite State Machine(s).

Unit <TimedLoopDomainCrosser_1> synthesized.

Synthesizing Unit <HandshakeSLV_Ack>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeSLV_Ack.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeSLV_Ack.vhd" line 57: Output port <iStoredData> of the instance <HBx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <HandshakeSLV_Ack> synthesized.

Synthesizing Unit <HandshakeBase_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBase.vhd". Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>. Set property "syn_maxfan = 1000000" for signal <BlkRdy.iReset_ms>. Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>. Found 1-bit register for signal <BlkRdy.iReset>. Found 1-bit register for signal <BlkRdy.iReset_ms>. Found 1-bit register for signal <iPushToggle>. Found 1-bit register for signal <BlkOut.oPushToggle0_ms>. Found 1-bit register for signal <BlkOut.oPushToggle1>. Found 1-bit register for signal <BlkOut.oPushToggle2>. Found 1-bit register for signal <oDataValid>. Found 1-bit register for signal <oPushToggleToReady>. Found 1-bit register for signal <BlkRdy.iRdyPushToggle_ms>. Found 1-bit register for signal <BlkRdy.iRdyPushToggle>. Found 1-bit register for signal <iLclReady>. Found 1-bit register for signal <iDlyPush>. Found 33-bit register for signal <iLclStoredData>. Summary:

inferred 45 D-type flip-flop(s).Unit <HandshakeBase_1> synthesized.

Synthesizing Unit <DFlopSlvResetVal_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlopSlvResetVal.vhd". Summary:

no macro.Unit <DFlopSlvResetVal_1> synthesized.

Synthesizing Unit <PulseSyncBool>.

Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PulseSyncBool.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PulseSyncBool.vhd" line 58: Output port <iStatusOfoSig> of the instance <PulseSyncBasex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PulseSyncBool.vhd" line 58: Output port <oSig> of the instance <PulseSyncBasex> is unconnected or connected to loadless signal. Summary:

no macro.Unit <PulseSyncBool> synthesized.

Synthesizing Unit <PulseSyncBase>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PulseSyncBase.vhd". Set property "syn_maxfan = 1000000" for signal <iSigOut_ms>. Set property "syn_maxfan = 1000000" for signal <oHoldSigIn_ms>. Summary:

no macro.Unit <PulseSyncBase> synthesized.

Synthesizing Unit <HandshakeSLV_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeSLV.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeSLV.vhd" line 55: Output port <iStoredData> of the instance <HBx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <HandshakeSLV_1> synthesized.

Synthesizing Unit <TimedLoopController_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimedLoopController.vhd". Found 1-bit register for signal <iLEnableOut>. Summary:

inferred 1 D-type flip-flop(s).Unit <TimedLoopController_1> synthesized.

Synthesizing Unit <NiFpgaAG_00000018_TimedLoopDiagram>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd".WARNING:Xst:647 - Input <iteration> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_8000000f<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_8000000f<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 226: Output port <cEnableOut> of the instance <n_OU_exclusif_10067> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 257: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_9282> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 272: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_entrE9e_8126_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 285: Output port <enable_out> of the instance <n_NiFpgaAG_0000001a_SequenceFrame_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 315: Output port <cEnableOut> of the instance <n_Regrouper_des_nombres_7026> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 337: Output port <cEnableOut> of the instance <n_Regrouper_des_nombres_7686> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 359: Output port <cEnableOut> of the instance <n_Regrouper_des_nombres_3519> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 381: Output port <cEnableOut> of the instance <n_Regrouper_des_nombres_7796> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 403: Output port <cEnableOut> of the instance <n_Regrouper_des_nombres_7173> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 425: Output port <cEnableOut> of the instance <n_Regrouper_des_nombres_7936> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 447: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_4497> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 465: Output port <enable_out> of the instance <n_Sous_dash_VI_NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Ed_4879> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 478: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_4511> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 496: Output port <cEnableOut> of the instance <n_SE9lectionner_4673> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 516: Output port <cEnableOut> of the instance <n_DE9crE9menter_5980> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 549: Output port <cEnableOut> of the instance <n_C9gal_E0_0_ques_3521> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 571: Output port <binenc_muxselect> of the instance <n_NiFpgaAG_00000029_CaseStructure> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 571: Output port <enable_out> of the instance <n_NiFpgaAG_00000029_CaseStructure> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 612: Output port <cEnableOut> of the instance <n_SE9lectionner_3589> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 632: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_7469> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 650: Output port <enable_out> of the instance <n_NiFpgaAG_0000002c_SequenceFrame_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 662: Output port <cErrorOut> of the instance <n_N9Cud_de_sortie_8116_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000018_TimedLoopDiagram.vhd" line 662: Output port <cEnableOut> of the instance <n_N9Cud_de_sortie_8116_Diagram> is unconnected or connected to loadless signal.WARNING:Xst:653 - Signal <res_80000010> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <res_80000012> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <res_80000014> is used but never assigned. This sourceless signal will be automatically connected to value GND. Summary:


Synthesizing Unit <FloatingFeedbackGInit_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FloatingFeedbackGInit.vhd".WARNING:Xst:647 - Input <cFromResTopEnablePassThruTopEnables<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cFromResTopEnablePassThruTopEnables<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cInitEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cLeftEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <FloatingFeedbackGInit_1> synthesized.

Synthesizing Unit <NiFpgaRegisterCore_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaRegisterCore.vhd". Summary:

no macro.Unit <NiFpgaRegisterCore_1> synthesized.

Synthesizing Unit <NiFpgaRegisterCoreBase_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaRegisterCoreBase.vhd". Found 16-bit register for signal <cRegArray<0>>. Summary:

inferred 16 D-type flip-flop(s).inferred 1 Multiplexer(s).

Unit <NiFpgaRegisterCoreBase_1> synthesized.

Synthesizing Unit <FloatingFeedbackGInit_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FloatingFeedbackGInit.vhd".WARNING:Xst:647 - Input <cFromResTopEnablePassThruTopEnables<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cFromResTopEnablePassThruTopEnables<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cInitEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cLeftEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:






Unit <NiFpgaRegisterCoreBase_2> synthesized.

Synthesizing Unit <NiFpgaBoolOp_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBoolOp.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBoolOp.vhd" line 233: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal. Summary:Unit <NiFpgaBoolOp_1> synthesized.

Synthesizing Unit <NiLvToInteger_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvToInteger.vhd". Summary:

no macro.Unit <NiLvToInteger_1> synthesized.

Synthesizing Unit <NiLvFxpCoerce_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCoerce.vhd".

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCoerce.vhd" line 170: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiLvFxpCoerce_1> synthesized.

Synthesizing Unit <NiLvFxpEnableHandler_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpEnableHandler.vhd". Summary:

no macro.Unit <NiLvFxpEnableHandler_1> synthesized.

Synthesizing Unit <NiLvFxpEnableHandlerSlv_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpEnableHandlerSlv.vhd".WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiLvFxpEnableHandlerSlv_1> synthesized.

Synthesizing Unit <NiFpgaGlobalResHolderWrite_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaGlobalResHolderWrite.vhd". Summary:

no macro.Unit <NiFpgaGlobalResHolderWrite_1> synthesized.

Synthesizing Unit <NiFpgaAG_0000001a_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 79: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 79: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 98: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 98: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 117: Output port <cErrorOut> of the instance

<n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_3> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 117: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_3> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 136: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_4> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 136: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_4> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 155: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_5> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 155: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_5> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 174: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_6> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 174: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_6> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 193: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_7> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000001a_SequenceFrame.vhd" line 193: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_11056_Diagram_7> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_0000001a_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaDiRead_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaDiRead.vhd". Set property "syn_maxfan = 1000000" for signal <cSyncRegister>.WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cFromResource<48:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaDiRead_1> synthesized.

Synthesizing Unit <NiFpgaLvJoinNumbers_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaLvJoinNumbers.vhd".WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaLvJoinNumbers_1> synthesized.

Synthesizing Unit <NiFpgaLvJoinNumbers_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaLvJoinNumbers.vhd".WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaLvJoinNumbers_2> synthesized.

Synthesizing Unit <NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd" line 52: Output port <enable_out> of the instance <n_resholder_r_opt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd" line 98: Output port <cEnableOut> of the instance <n_NotPrimitive> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd" line 120: Output port <cEnableOut> of the instance <n_OpE9rateur_arithmE9tique_117> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd" line 151: Output port <enable_out> of the instance <n_resholder_w_opt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd" line 168: Output port <res_wo> of the instance <n_SubVICtlOrIndOpt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd" line 168: Output port <data> of the instance <n_SubVICtlOrIndOpt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co.vhd" line 192: Output port <res_ro> of the instance <n_SubVICtlOrIndOpt_2> is unconnected or connected to loadless signal.WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND. Summary:

no macro.Unit <NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co> synthesized.

Synthesizing Unit <resholder_r_opt>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\resholder_r_opt.vhd".WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <resholder_r_opt> synthesized.

Synthesizing Unit <FloatingFeedbackGInit_3>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FloatingFeedbackGInit.vhd".WARNING:Xst:647 - Input <cFromResTopEnablePassThruTopEnables> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cInitEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cLeftEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:





inferred 1 D-type flip-flop(s).Unit <NiFpgaRegisterCoreBase_3> synthesized.

Synthesizing Unit <NiFpgaBoolOpNot>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBoolOpNot.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBoolOpNot.vhd" line 143: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaBoolOpNot> synthesized.

Synthesizing Unit <NiFpgaBoolOp_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBoolOp.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBoolOp.vhd" line 233: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaBoolOp_2> synthesized.

Synthesizing Unit <resholder_w_opt>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\resholder_w_opt.vhd".WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <resholder_w_opt> synthesized.

Synthesizing Unit <SubVICtlOrIndOpt_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SubVICtlOrIndOpt.vhd".WARNING:Xst:647 - Input <res_ri<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_wi<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <enable_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <SubVICtlOrIndOpt_1> synthesized.

Synthesizing Unit <SubVICtlOrIndOpt_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SubVICtlOrIndOpt.vhd".WARNING:Xst:647 - Input <res_ri<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_wi<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <enable_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <SubVICtlOrIndOpt_2> synthesized.

Synthesizing Unit <NiFpgaSelect>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaSelect.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaSelect.vhd" line 75: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal. Summary:

inferred 1 Multiplexer(s).Unit <NiFpgaSelect> synthesized.

Synthesizing Unit <NiLvFxpEnableHandlerSlv_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpEnableHandlerSlv.vhd".WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiLvFxpEnableHandlerSlv_2> synthesized.

Synthesizing Unit <NiLvDecrement>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvDecrement.vhd".WARNING:Xst:647 - Input <cTopLevelEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiLvDecrement> synthesized.

Synthesizing Unit <NiLvFxpDecrement>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpDecrement.vhd". Summary:

no macro.Unit <NiLvFxpDecrement> synthesized.

Synthesizing Unit <NiLvFxpSubtract>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpSubtract.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpSubtract.vhd" line 145: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerx> is unconnected or connected to loadless signal. Found 18-bit subtractor for signal <n0017> created at line 2093. Summary:

inferred 1 Adder/Subtractor(s).Unit <NiLvFxpSubtract> synthesized.

Synthesizing Unit <NiLvFxpEnableHandler_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpEnableHandler.vhd". Summary:

no macro.Unit <NiLvFxpEnableHandler_2> synthesized.

Synthesizing Unit <NiLvCompareToZero>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvCompareToZero.vhd". Summary:

no macro.Unit <NiLvCompareToZero> synthesized.

Synthesizing Unit <NiLvFxpCompareToZero>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCompareToZero.vhd". Summary:

no macro.Unit <NiLvFxpCompareToZero> synthesized.

Synthesizing Unit <NiLvFxpCompare_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCompare.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCompare.vhd" line 240: Output port <cOut> of the instance <NiLvFxpEnableHandlerx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiLvFxpCompare_1> synthesized.

Synthesizing Unit <NiFpgaAG_00000029_CaseStructure_62>.

Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructure_62.vhd".WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

inferred 1 Multiplexer(s).Unit <NiFpgaAG_00000029_CaseStructure_62> synthesized.

Synthesizing Unit <NiFpgaAG_00000029_CaseStructureFrame_0000>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructureFrame_0000.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000001> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000003> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <IO_ModuleA_AAcqClkBufRToLv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaAG_00000029_CaseStructureFrame_0000> synthesized.

Synthesizing Unit <NiFpgaAG_00000029_CaseStructureFrame_0001>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000029_CaseStructureFrame_0001.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <tunnel_hi_lo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <tunnel_hi_lo_2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <enable_clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Summary:no macro.

Unit <NiFpgaAG_00000029_CaseStructureFrame_0001> synthesized.

Synthesizing Unit <NiFpgaAG_0000002c_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000002c_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000002c_SequenceFrame.vhd" line 30: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_7526_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000002c_SequenceFrame.vhd" line 30: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_7526_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000002c_SequenceFrame.vhd" line 30: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_7526_Diagram> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_0000002c_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_TimedLoopControllerContainer_179>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_179.vhd".WARNING:Xst:647 - Input <iClkFromResTopEnablePassThruTopEnables<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <iClkFromResTopEnablePassThruTopEnables<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <iClkSubdiag_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_179.vhd" line 71: Output port <oEnableOut> of the instance <TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <NiFpgaAG_00000043_TimedLoopDiagram>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd".WARNING:Xst:647 - Input <iteration> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_8000000b<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <res_8000000b<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_8000000d<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_8000000d<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_8000000f<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_8000000f<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000011<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000011<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000013<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000013<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000015<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000015<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 319: Output port <shift_out> of the instance <n_ishiftreg> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 319: Output port <enable_out> of the instance <n_ishiftreg> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 339: Output port <enable_out> of the instance <n_ishiftreg_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 359: Output port <enable_out> of the instance <n_ishiftreg_3> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 379: Output port <enable_out> of the instance <n_ishiftreg_4> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 399: Output port <enable_out> of the instance <n_ishiftreg_5> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 419: Output port <shift_out> of the instance <n_ishiftreg_6> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 419: Output port <enable_out> of the instance <n_ishiftreg_6> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 439: Output port <cEnableOut> of the instance <n_Control> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 456: Output port <cEnableOut> of the instance <n_Control_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 473: Output port <cEnableOut> of the instance <n_Control_3> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 490: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_3791> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 505: Output port <cEnableOut> of the instance <n_Control_4> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 522: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_3253> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 537: Output port <cEnableOut> of the instance <n_Control_5> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 554: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_3297> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 569: Output port <cEnableOut> of the instance <n_Control_6> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 586: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_3319> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 601: Output port <cEnableOut> of the instance <n_Control_7> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 618: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_3341> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 633: Output port <cEnableOut> of the instance <n_Control_8> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 650: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_3363> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 665: Output port <cEnableOut> of the instance <n_Control_9> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 682: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_3385> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 697: Output port <cEnableOut> of the instance <n_Control_10> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 714: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_3098> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 729: Output port <cEnableOut> of the instance <n_Control_11> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 746: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_388> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 761: Output port <cEnableOut> of the instance <n_Control_12> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 778: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_1375> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 793: Output port <cEnableOut> of the instance <n_Control_13> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 810: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_336> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 825: Output port <cEnableOut> of the instance <n_Control_14> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 842: Output port <cEnableOut> of the instance <n_Control_15> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 859: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_1624> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 874: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_entrE9e_4562_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 887: Output port <enable_out> of the instance <n_NiFpgaAG_00000045_SequenceFrame_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 905: Output port <cEnableOut> of the instance <n_Indicator> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 923: Output port <enable_out> of the instance <n_NiFpgaAG_00000049_SequenceFrame_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 935: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_6979> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 953: Output port <enable_out> of the instance <n_NiFpgaAG_0000004b_SequenceFrame_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 965: Output port <cEnableOut> of the instance <n_BoolE9en_en_0_comma_1_8118> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 994: Output port <cEnableOut> of the instance <n_BoolE9en_en_0_comma_1_8069> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1023: Output port <cEnableOut> of the instance <n_BoolE9en_en_0_comma_1_8023> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1052: Output port <cEnableOut> of the instance <n_OpE9rateur_arithmE9tique_196> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1093: Output port <cEnableOut> of the instance <n_BoolE9en_en_0_comma_1_7961> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1122: Output port <cEnableOut> of the instance <n_BoolE9en_en_0_comma_1_7938> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1151: Output port <cEnableOut> of the instance <n_OpE9rateur_arithmE9tique_196_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1192: Output port <cEnableOut> of the instance <n_OpE9rateur_arithmE9tique_196_3> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1233: Output port <cEnableOut> of the instance <n_OpE9rateur_arithmE9tique_196_4> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1274: Output port <cEnableOut> of the instance <n_DiffE9rents_ques_10003> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1305: Output port <cEnableOut> of the instance <n_DiffE9rents_ques_9902> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1336: Output port <cEnableOut> of the instance <n_ET_10525> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1367: Output port <cEnableOut> of the instance <n_Indicator_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1485: Output port <cErrorOut> of the instance <n_N9Cud_de_sortie_4552_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000043_TimedLoopDiagram.vhd" line 1485: Output port <cEnableOut> of the instance <n_N9Cud_de_sortie_4552_Diagram> is unconnected or connected to loadless signal.WARNING:Xst:653 - Signal <res_8000000c> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <res_8000000e> is used but never assigned. This sourceless signal will be automatically connected to value GND.

WARNING:Xst:653 - Signal <res_80000010> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <res_80000012> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <res_80000014> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <res_80000016> is used but never assigned. This sourceless signal will be automatically connected to value GND. Found 16-bit 6-to-1 multiplexer for signal <s_4129> created at line 1564. Summary:

inferred 1 Multiplexer(s).Unit <NiFpgaAG_00000043_TimedLoopDiagram> synthesized.

Synthesizing Unit <NiFpgaShiftReg_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaShiftReg.vhd". Found 16-bit register for signal <nextdata>. Summary:


Unit <NiFpgaShiftReg_1> synthesized.

Synthesizing Unit <NiFpgaShiftReg_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaShiftReg.vhd". Found 1-bit register for signal <nextdata>. Summary:


Unit <NiFpgaShiftReg_2> synthesized.

Synthesizing Unit <NiFpgaLocalResHolderRead_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaLocalResHolderRead.vhd".WARNING:Xst:647 - Input <cFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaLocalResHolderRead_1> synthesized.

Synthesizing Unit <NiFpgaLocalResHolderRead_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaLocalResHolderRead.vhd".WARNING:Xst:647 - Input <cFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:


Synthesizing Unit <NiFpgaLocalResHolderRead_3>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaLocalResHolderRead.vhd".WARNING:Xst:647 - Input <cFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:


Synthesizing Unit <NiFpgaGlobalResHolderWrite_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaGlobalResHolderWrite.vhd". Summary:

no macro.Unit <NiFpgaGlobalResHolderWrite_2> synthesized.

Synthesizing Unit <NiFpgaAG_00000045_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000045_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000045_SequenceFrame.vhd" line 45: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3487_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000045_SequenceFrame.vhd" line 45: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3487_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000045_SequenceFrame.vhd" line 64: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3487_Diagram_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000045_SequenceFrame.vhd" line 64: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3487_Diagram_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000045_SequenceFrame.vhd" line 64: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3487_Diagram_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000045_SequenceFrame.vhd" line 82: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3487_Diagram_3> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000045_SequenceFrame.vhd" line 82: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3487_Diagram_3> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000045_SequenceFrame.vhd" line 82: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3487_Diagram_3> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <NiFpgaDiRead_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaDiRead.vhd". Set property "syn_maxfan = 1000000" for signal <cSyncRegister>.WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cFromResource<3:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaDiRead_2> synthesized.



Synthesizing Unit <NiFpgaLocalResHolderWrite>.

Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaLocalResHolderWrite.vhd".WARNING:Xst:647 - Input <cFromRes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaLocalResHolderWrite> synthesized.

Synthesizing Unit <NiFpgaAG_00000049_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000049_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000049_SequenceFrame.vhd" line 31: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3403_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000049_SequenceFrame.vhd" line 31: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_3403_Diagram> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <NiFpgaAG_0000004b_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004b_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004b_SequenceFrame.vhd" line 30: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_2237_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004b_SequenceFrame.vhd" line 30: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_2237_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004b_SequenceFrame.vhd" line 30: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_2237_Diagram> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_0000004b_SequenceFrame> synthesized.

Synthesizing Unit <NiLvToInteger_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvToInteger.vhd". Summary:

no macro.Unit <NiLvToInteger_2> synthesized.

Synthesizing Unit <NiLvFxpCoerce_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCoerce.vhd".

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCoerce.vhd" line 170: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiLvFxpCoerce_2> synthesized.

Synthesizing Unit <NiLvAdd>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvAdd.vhd".WARNING:Xst:647 - Input <cTopLevelEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiLvAdd> synthesized.

Synthesizing Unit <NiLvFxpAdd>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpAdd.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpAdd.vhd" line 137: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerx> is unconnected or connected to loadless signal. Found 17-bit adder for signal <n0021> created at line 1634. Summary:

inferred 1 Adder/Subtractor(s).Unit <NiLvFxpAdd> synthesized.

Synthesizing Unit <NiLvCompare>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvCompare.vhd".WARNING:Xst:647 - Input <cTopLevelEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiLvCompare> synthesized.

Synthesizing Unit <NiLvFxpCompare_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCompare.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFxpCompare.vhd" line 240: Output port <cOut> of the instance <NiLvFxpEnableHandlerx> is unconnected or connected to loadless signal. Found 16-bit comparator not equal for signal <GenInOneSigned.cInOneFxpSgn[15]_GenInOneSigned.GenInTwoSigned.cInTwoFxpSgn[15]_equal_5_o> created at line 1555 Summary:

inferred 1 Comparator(s).Unit <NiLvFxpCompare_2> synthesized.

Synthesizing Unit <NiFpgaAG_0000004d_CaseStructure_149>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructure_149.vhd".WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

inferred 3 Multiplexer(s).Unit <NiFpgaAG_0000004d_CaseStructure_149> synthesized.

Synthesizing Unit <NiFpgaAG_0000004d_CaseStructureFrame_0000>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd" line 44: Output port <cEnableOut> of the instance <n_Control> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd" line 61: Output port <enable_out> of the instance <n_Sous_dash_VI_NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Ed_6711> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd" line 74: Output port <cEnableOut> of the instance <n_ET_7777> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd" line 105: Output port <cEnableOut> of the instance <n_SE9lectionner_8211> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_0000004d_CaseStructureFrame_0000> synthesized.

Synthesizing Unit <NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd" line 52: Output port <enable_out> of the instance <n_resholder_r_opt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd" line 98: Output port <cEnableOut> of the instance <n_NotPrimitive> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd" line 120: Output port <cEnableOut> of the instance <n_OpE9rateur_arithmE9tique_117> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd" line 151: Output port <enable_out> of the instance <n_resholder_w_opt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd" line 168: Output port <res_wo> of the instance <n_SubVICtlOrIndOpt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd" line 168: Output port <data> of the instance <n_SubVICtlOrIndOpt> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2.vhd" line 192: Output port <res_ro> of the instance <n_SubVICtlOrIndOpt_2> is unconnected or connected to loadless signal.WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND. Summary:

no macro.Unit <NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge_Detect_vi_co_2> synthesized.

Synthesizing Unit <NiFpgaAG_0000004d_CaseStructureFrame_0001>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <tunnel_EIOSignal> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000003<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

inferred 1 Multiplexer(s).Unit <NiFpgaAG_0000004d_CaseStructureFrame_0001> synthesized.

Synthesizing Unit <NiFpgaAG_00000059_CaseStructureFrame_0000>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000059_CaseStructureFrame_0000.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000059_CaseStructureFrame_0000.vhd" line 32: Output port <enable_out> of the instance <n_NiFpgaAG_0000005a_SequenceFrame_Diagram> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <NiFpgaAG_0000005a_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005a_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005a_SequenceFrame.vhd" line 30: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_8838_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005a_SequenceFrame.vhd" line 30: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_8838_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005a_SequenceFrame.vhd" line 30: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_8838_Diagram> is unconnected or connected to loadless signal.

Summary:no macro.

Unit <NiFpgaAG_0000005a_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_00000059_CaseStructureFrame_0001>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000059_CaseStructureFrame_0001.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <tunnel_Element> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <enable_clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:


Synthesizing Unit <NiFpgaAG_0000004d_CaseStructureFrame_0002>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <tunnel_EIOSignal> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd" line 33: Output port <enable_out> of the instance <n_NiFpgaAG_0000005d_SequenceFrame_Diagram> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <NiFpgaAG_0000005d_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005d_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005d_SequenceFrame.vhd" line 30: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_4191_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005d_SequenceFrame.vhd" line 30: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_4191_Diagram> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005d_SequenceFrame.vhd" line 30: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_4191_Diagram> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_0000005d_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_0000004d_CaseStructureFrame_0003>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0003.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <tunnel_EIOSignal> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0003.vhd" line 33: Output port <enable_out> of the instance <n_NiFpgaAG_0000005f_SequenceFrame_Diagram> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <NiFpgaAG_0000005f_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005f_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005f_SequenceFrame.vhd" line 30: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_4338_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005f_SequenceFrame.vhd" line 30: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_4338_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000005f_SequenceFrame.vhd" line 30: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_4338_Diagram> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_0000005f_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_0000004d_CaseStructureFrame_0004>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0004.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <tunnel_EIOSignal> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0004.vhd" line 33: Output port <enable_out> of the

instance <n_NiFpgaAG_00000061_SequenceFrame_Diagram> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <NiFpgaAG_00000061_SequenceFrame>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000061_SequenceFrame.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000061_SequenceFrame.vhd" line 30: Output port <cErrorOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_4428_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000061_SequenceFrame.vhd" line 30: Output port <cToEnableResource> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_4428_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000061_SequenceFrame.vhd" line 30: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_E_slash_S_FPGA_4428_Diagram> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <NiFpgaAG_0000004d_CaseStructureFrame_0005>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd" line 31: Output port <cEnableOut> of the instance <n_SE9lectionner_3129> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <NiFpgaAG_TimedLoopControllerContainer_180>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_180.vhd".WARNING:Xst:647 - Input <iClkSubdiag_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_180.vhd" line 75: Output port <iEnableOut> of the instance <TimeLoopControllerx> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <TimedLoopController_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimedLoopController.vhd". Found 1-bit register for signal <iLEnableOut>.

Found 1-bit register for signal <iLEnableIn>. Summary:


Unit <TimedLoopController_2> synthesized.

Synthesizing Unit <NiFpgaAG_00000098_TimedLoopDiagram>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd".WARNING:Xst:647 - Input <iteration> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_8000000b<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_8000000d<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" line 85: Output port <cEnableOut> of the instance <n_N9Cud_d_apost_entrE9e_14543_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" line 108: Output port <cEnableOut> of the instance <n_Non_10997> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" line 140: Output port <cEnableOut> of the instance <n_Non_11019> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" line 162: Output port <cEnableOut> of the instance <n_ET_11110> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" line 193: Output port <binenc_muxselect> of the instance <n_NiFpgaAG_0000009c_CaseStructure> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" line 193: Output port <enable_out> of the instance <n_NiFpgaAG_0000009c_CaseStructure> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" line 240: Output port <cErrorOut> of the instance <n_N9Cud_de_sortie_14533_Diagram> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_00000098_TimedLoopDiagram.vhd" line 240: Output port <cEnableOut> of the instance <n_N9Cud_de_sortie_14533_Diagram> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <NiFpgaAG_0000009c_CaseStructureFrame_0000>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0000.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <tunnel_Element> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <tunnel_Element_2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <enable_clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaAG_0000009c_CaseStructureFrame_0000> synthesized.

Synthesizing Unit <NiFpgaAG_0000009c_CaseStructureFrame_0001>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd".WARNING:Xst:647 - Input <casesel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000005<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <res_80000007<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" line 57: Output port <cEnableOut> of the instance <n_Variable_globale_FGPA_Globals_vi_4498> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" line 93: Output port <cEnableOut> of the instance <n_OU_4537> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" line 124: Output port <enable_out> of the instance <n_Sous_dash_VI_niInstr_Basic_Elements_v1_FPGA_lvlib_colon_4329> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd" line 138: Output port <cEnableOut> of the instance <n_Indicator> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaAG_0000009c_CaseStructureFrame_0001> synthesized.

Synthesizing Unit <NiFpgaBoolOp_3>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBoolOp.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBoolOp.vhd" line 233: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <NiFpgaBoolOp_3> synthesized.

Synthesizing Unit <niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 91: Output port <enable_out> of the instance <n_resholder_r_opt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 108: Output port <cEnableOut> of the instance <n_OU_67> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 139: Output port <enable_out> of the instance <n_resholder_r_opt_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 156: Output port <cEnableOut> of the instance <n_NotPrimitive> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 178: Output port <cEnableOut> of the instance <n_OpE9rateur_arithmE9tique_179> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 209: Output port <enable_out> of the instance <n_resholder_w_opt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 226: Output port <res_wo> of the instance <n_SubVICtlOrIndOpt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 226: Output port <data> of the instance <n_SubVICtlOrIndOpt> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 250: Output port <res_wo> of the instance <n_SubVICtlOrIndOpt_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 250: Output port <data> of the instance <n_SubVICtlOrIndOpt_2> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat.vhd" line 274: Output port <res_ro> of the instance <n_SubVICtlOrIndOpt_3> is unconnected or connected to loadless signal.WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND. Summary:

no macro.Unit <niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Synchronous_Lat> synthesized.

Synthesizing Unit <FloatingFeedbackGInit_4>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FloatingFeedbackGInit.vhd".WARNING:Xst:647 - Input <cFromResTopEnablePassThruTopEnables> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <cInitEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cLeftEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:


Synthesizing Unit <NiFpgaAG_TimedLoopControllerContainer_181>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_181.vhd".WARNING:Xst:647 - Input <iClkSubdiag_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaAG_TimedLoopControllerContainer_181.vhd" line 64: Output port <oEnableOut> of the instance <TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz> is unconnected or connected to loadless signal. Summary:


Synthesizing Unit <TimedLoopCore_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimedLoopCore.vhd". Summary:

no macro.Unit <TimedLoopCore_2> synthesized.

Synthesizing Unit <TimedLoopDomainCrosser_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimedLoopDomainCrosser.vhd".WARNING:Xst:647 - Input <iTopEnIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal <oLEnableOut>. Found 1-bit register for signal <iEnableClrDelayed>. Found 3-bit register for signal <iEnableInDelays>. Found 2-bit register for signal <iEoState>. Found finite state machine <FSM_4> for signal <iEoState>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 6 | | Inputs | 2 | | Outputs | 1 | | Clock | IClk (rising_edge) | | Reset | aReset (positive) | | Reset type | asynchronous | | Reset State | waitingforloopenableoutassertion | | Power Up State | waitingforloopenableoutassertion | | Encoding | auto | | Implementation | LUT |

----------------------------------------------------------------------- Summary:


Unit <TimedLoopDomainCrosser_2> synthesized.

Synthesizing Unit <InvisibleResholder>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InvisibleResholder.vhd".WARNING:Xst:647 - Input <FromResbusholddummy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:653 - Signal <ToResbusholddummy> is used but never assigned. This sourceless signal will be automatically connected to value GND. Summary:

no macro.Unit <InvisibleResholder> synthesized.

Synthesizing Unit <NiLvFpgaStockDigitalOutput_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFpgaStockDigitalOutput.vhd". Set property "IOB = TRUE" for signal <cSyncRegister>.WARNING:Xst:647 - Input <cFromResholder<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiLvFpgaStockDigitalOutput_1> synthesized.

Synthesizing Unit <NiLvFpgaStockDigitalOutput_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFpgaStockDigitalOutput.vhd". Set property "IOB = TRUE" for signal <cSyncRegister>.WARNING:Xst:647 - Input <cFromResholder<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

Summary:no macro.

Unit <NiLvFpgaStockDigitalOutput_2> synthesized.

Synthesizing Unit <FGPA_Globals_viBit00>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FGPA_Globals_viBit00.vhd".WARNING:Xst:647 - Input <clkOutPortFromReshold<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkInPortFromReshold<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 16-bit register for signal <clkReg>. Summary:

inferred 16 D-type flip-flop(s).Unit <FGPA_Globals_viBit00> synthesized.

Synthesizing Unit <FGPA_Globals_viIO_Module_bksl_Acq_Reset12>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd".WARNING:Xst:647 - Input <clkOutPortFromReshold<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkInPortFromReshold<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal <clkReg>. Summary:

inferred 1 D-type flip-flop(s).Unit <FGPA_Globals_viIO_Module_bksl_Acq_Reset12> synthesized.

Synthesizing Unit <NiLvFpgaStockDigitalInput_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFpgaStockDigitalInput.vhd". Set property "syn_maxfan = 1000000" for signal <cFirstRegister_ms>. Set property "IOB = TRUE" for signal <cFirstRegister_ms>. Set property "syn_maxfan = 1000000" for signal <cSecondRegister>. Found 16-bit register for signal <cSecondRegister>. Found 16-bit register for signal <cFirstRegister_ms>.INFO:Xst:2774 - HDL ADVISOR - IOB, MAX_FANOUT properties attached to signal cFirstRegister_ms may hinder XST clustering optimizations. Summary:

inferred 32 D-type flip-flop(s).Unit <NiLvFpgaStockDigitalInput_1> synthesized.

Synthesizing Unit <TopEnablePassThru>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TopEnablePassThru.vhd".WARNING:Xst:647 - Input <clkTopEnablesFromReshold> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <TopEnablePassThru> synthesized.

Synthesizing Unit <FPGAwFIFOn0>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn0.vhd".WARNING:Xst:647 - Input <CClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cClearEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cClearEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <iCountEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <iCountEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <oCountEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <oCountEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <iTopEnIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <oTopEnIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn0.vhd" line 423: Output port <cDisableAck> of the instance <PushControl> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn0.vhd" line 472: Output port <cDisableAck> of the instance <PopControl> is unconnected or connected to loadless signal.WARNING:Xst:2935 - Signal 'iCountEmptyCountLoc', unconnected in block 'FPGAwFIFOn0', is tied to its initial value (10000000010).WARNING:Xst:2935 - Signal 'oCountFullCountLoc', unconnected in block 'FPGAwFIFOn0', is tied to its initial value (00000000000).WARNING:Xst:2935 - Signal 'cClearEnableOut', unconnected in block 'FPGAwFIFOn0', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'iCountEnableOut', unconnected in block 'FPGAwFIFOn0', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'oCountEnableOut', unconnected in block 'FPGAwFIFOn0', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'iDisablePushFromClearControl', unconnected in block 'FPGAwFIFOn0', is tied to its initial value (0).

WARNING:Xst:2935 - Signal 'oDisablePopFromClearControl', unconnected in block 'FPGAwFIFOn0', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'oPopFromClearControl', unconnected in block 'FPGAwFIFOn0', is tied to its initial value (0). Summary:

no macro.Unit <FPGAwFIFOn0> synthesized.

Synthesizing Unit <NiFpgaBuiltInFifoResetControl>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBuiltInFifoResetControl.vhd". Set property "syn_keep = true" for signal <BuiltInFifoInputEn.iTopEnInLatch>. Set property "syn_keep = true" for signal <BuiltInFifoInputEn.oTopEnInLatch>.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaBuiltInFifoResetControl.vhd" line 268: Output port <oSig> of the instance <BuiltInFifoInputEn.TopEnInFromOClkSyncToIClk> is unconnected or connected to loadless signal. Found 1-bit register for signal <BuiltInFifoRst.iBuiltInFifoRstReg>. Found 1-bit register for signal <BuiltInFifoInputEn.iTopEnInLatch>. Found 1-bit register for signal <BuiltInFifoInputEn.oTopEnInLatch>. Found 8-bit register for signal <BuiltInFifoInputEn.iTimerCount>. Found 7-bit register for signal <BuiltInFifoInputEn.oTimerCount>. Found 8-bit subtractor for signal <GND_1435_o_GND_1435_o_sub_2_OUT<7:0>> created at line 195. Found 7-bit subtractor for signal <GND_1435_o_GND_1435_o_sub_8_OUT<6:0>> created at line 218. Summary:


Unit <NiFpgaBuiltInFifoResetControl> synthesized.

Synthesizing Unit <NiFpgaFifoPushPopControl_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPushPopControl.vhd".WARNING:Xst:647 - Input <cTimeoutValue> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaFifoPushPopControl_1> synthesized.

Synthesizing Unit <NiFpgaFifoPushPopControl_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPushPopControl.vhd".

WARNING:Xst:647 - Input <cTimeoutValue> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaFifoPushPopControl_2> synthesized.

Synthesizing Unit <FPGAwFIFOn1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn1.vhd".WARNING:Xst:647 - Input <CClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cClearEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cClearEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <iCountEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <iCountEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <oCountEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <oCountEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <iTopEnIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <oTopEnIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn1.vhd" line 423: Output port <cDisableAck> of the instance <PushControl> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FPGAwFIFOn1.vhd" line 472: Output port <cDisableAck> of the instance <PopControl> is unconnected or connected to loadless signal.WARNING:Xst:2935 - Signal 'iCountEmptyCountLoc', unconnected in block 'FPGAwFIFOn1', is tied to its initial value (10000000010).

WARNING:Xst:2935 - Signal 'oCountFullCountLoc', unconnected in block 'FPGAwFIFOn1', is tied to its initial value (00000000000).WARNING:Xst:2935 - Signal 'cClearEnableOut', unconnected in block 'FPGAwFIFOn1', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'iCountEnableOut', unconnected in block 'FPGAwFIFOn1', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'oCountEnableOut', unconnected in block 'FPGAwFIFOn1', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'iDisablePushFromClearControl', unconnected in block 'FPGAwFIFOn1', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'oDisablePopFromClearControl', unconnected in block 'FPGAwFIFOn1', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'oPopFromClearControl', unconnected in block 'FPGAwFIFOn1', is tied to its initial value (0). Summary:

no macro.Unit <FPGAwFIFOn1> synthesized.

Synthesizing Unit <FGPA_Globals_viAcq_Regional_Clock_Loop11>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FGPA_Globals_viAcq_Regional_Clock_Loop11.vhd".WARNING:Xst:647 - Input <clkInPortFromReshold<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkOutPortFromReshold<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal <clkReg>. Summary:

inferred 1 D-type flip-flop(s).Unit <FGPA_Globals_viAcq_Regional_Clock_Loop11> synthesized.

Synthesizing Unit <NiLvFpgaStockDigitalInput_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFpgaStockDigitalInput.vhd". Set property "syn_maxfan = 1000000" for signal <cFirstRegister_ms>. Set property "IOB = TRUE" for signal <cFirstRegister_ms>. Set property "syn_maxfan = 1000000" for signal <cSecondRegister>. Found 1-bit register for signal <cSecondRegister>. Found 1-bit register for signal <cFirstRegister_ms>.INFO:Xst:2774 - HDL ADVISOR - IOB, MAX_FANOUT properties attached to signal cFirstRegister_ms may hinder XST clustering optimizations. Summary:

inferred 2 D-type flip-flop(s).Unit <NiLvFpgaStockDigitalInput_2> synthesized.

Synthesizing Unit <NiLvFpgaStockDigitalOutput_3>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFpgaStockDigitalOutput.vhd". Set property "IOB = TRUE" for signal <cSyncRegister>.WARNING:Xst:647 - Input <cFromResholder<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiLvFpgaStockDigitalOutput_3> synthesized.

Synthesizing Unit <bushold>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd".WARNING:Xst:647 - Input <dummyFromReshold> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResIO_Module_bksl_Xpoint_Switch_Write_ctl_0HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResIO_Module_bksl_Gen_IO_Clock_Source_ctl_1HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResIO_Module_bksl_Xpoint_Switch_Ready_ind_2HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResBit0_ctl_3HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResBit1_ctl_4HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResBit2_ctl_5HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResBit3_ctl_6HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResBit4_ctl_7HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResBit5_ctl_8HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResBit6_ctl_9HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResIO_Module_bksl_Gen_Reset_ctl_10HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <rioClk40FromResSoftware_Trigger_ctl_12HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResFetch_Length_ctl_13HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40Derived5x1C00MHzFromResT2H_DMA_Timeout_ind_14HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResClear_T2H_DMA_Timeout_ctl_15HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResAcq_Regional_Clock_Loop_ind_16HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResIO_Module_bksl_Acq_IO_Clock_Source_ctl_17HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResIO_Module_bksl_Acq_Reset_ctl_18HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rioClk40FromResIO_Module_bksl_Program_Onboard_Clock_ctl_11HostWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" line 521: Output port <iStoredData> of the instance <RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzFromInterface> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" line 537: Output port <iStoredData> of the instance <RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzToInterface> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" line 537: Output port <iReady> of the instance <RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzToInterface> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" line 537: Output port <iOResetStatus> of the instance <RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzToInterface> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" line 673: Output port <iStoredData> of the instance <RioClk40Crossing.RioClk40FromInterface> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" line 689: Output port <iStoredData> of the instance <RioClk40Crossing.RioClk40ToInterface> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" line 689: Output port <iReady> of the instance <RioClk40Crossing.RioClk40ToInterface> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" line 689: Output port <iOResetStatus> of the instance <RioClk40Crossing.RioClk40ToInterface> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" line 1128: Output port <cRegDataOut> of the instance <ChinchClkShifter.ShiftRegister> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\bushold.vhd" line 1128: Output port <cRegWrite> of the instance <ChinchClkShifter.ShiftRegister> is unconnected or connected to loadless signal.WARNING:Xst:653 - Signal <dummyToReshold> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <chinchClkToResViControlHostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <chinchClkToResViControlHostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <chinchClkToResDiagramResetHostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <chinchClkToResDiagramResetHostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <chinchClkToResViSignatureHostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Xpoint_Switch_Write_ctl_0HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Xpoint_Switch_Write_ctl_0HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Gen_IO_Clock_Source_ctl_1HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Gen_IO_Clock_Source_ctl_1HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Xpoint_Switch_Ready_ind_2HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Xpoint_Switch_Ready_ind_2HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit0_ctl_3HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit0_ctl_3HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit1_ctl_4HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit1_ctl_4HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit2_ctl_5HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit2_ctl_5HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.

WARNING:Xst:653 - Signal <rioClk40ToResBit3_ctl_6HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit3_ctl_6HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit4_ctl_7HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit4_ctl_7HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit5_ctl_8HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit5_ctl_8HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit6_ctl_9HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResBit6_ctl_9HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Gen_Reset_ctl_10HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Gen_Reset_ctl_10HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResSoftware_Trigger_ctl_12HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResSoftware_Trigger_ctl_12HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResFetch_Length_ctl_13HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResFetch_Length_ctl_13HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40Derived5x1C00MHzToResT2H_DMA_Timeout_ind_14HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40Derived5x1C00MHzToResT2H_DMA_Timeout_ind_14HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResClear_T2H_DMA_Timeout_ctl_15HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResClear_T2H_DMA_Timeout_ctl_15HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResAcq_Regional_Clock_Loop_ind_16HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResAcq_Regional_Clock_Loop_ind_16HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Acq_IO_Clock_Source_ctl_17HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Acq_IO_Clock_Source_ctl_17HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Acq_Reset_ctl_18HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Acq_Reset_ctl_18HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.

WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Program_Onboard_Clock_ctl_11HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <rioClk40ToResIO_Module_bksl_Program_Onboard_Clock_ctl_11HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <RioClk40Derived5x1C00MHzShifter.RioClk40Derived5x1C00MHzSrDataOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <RioClk40Shifter.RioClk40SrDataOut> is used but never assigned. This sourceless signal will be automatically connected to value GND. Found 17-bit comparator greater for signal <RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzAddrInThisDomain> created at line 495 Found 17-bit comparator greater for signal <iRegPortInRioClk40_Address[16]_GND_1461_o_LessThan_28_o> created at line 647 Summary:

inferred 2 Comparator(s).inferred 48 Multiplexer(s).

Unit <bushold> synthesized.

Synthesizing Unit <HandshakeBaseResetCross_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBaseResetCross.vhd". Set property "syn_keep = true" for signal <iPush>. Set property "syn_keep = true" for signal <iDlyPush>. Set property "syn_keep = true" for signal <iLclReady>. Set property "use_clock_enable = yes" for signal <oPushToggleToReady>. Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>. Set property "syn_keep = true" for signal <BlkOut.oDataAckClkEnable>.WARNING:Xst:37 - Detected unknown constraint/property "syn_direct_enable". This constraint/property is not supported by the current software release and will be ignored. Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>.WARNING:Xst:647 - Input <aResetToDlyPush> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aResetToIResetFast> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aPushToggleDly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBaseResetCross.vhd" line 382: Output port <c1ResetFast> of the instance <BlkOut.SyncOReset> is unconnected or connected to loadless signal. Found 1-bit register for signal <BlkRdy.iRdyPushToggle>. Found 1-bit register for signal <iLclReady>. Found 1-bit register for signal <iDlyPush>. Found 1-bit register for signal <BlkOut.oPushToggle1>. Found 1-bit register for signal <BlkOut.oPushToggle2>. Found 1-bit register for signal <oDataValid>. Summary:

inferred 6 D-type flip-flop(s).

Unit <HandshakeBaseResetCross_1> synthesized.



Synthesizing Unit <ResetSync_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ResetSync.vhd". Set property "equivalent_register_removal = no". Found 1-bit register for signal <c1ResetFromClk2_ms>. Found 1-bit register for signal <c1ResetFromClk2>. Found 1-bit register for signal <c2ResetLcl>. Summary:

inferred 3 D-type flip-flop(s).Unit <ResetSync_1> synthesized.

Synthesizing Unit <DFlopBool_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlopBool.vhd". Set property "syn_preserve = true". Summary:

no macro.Unit <DFlopBool_2> synthesized.

Synthesizing Unit <DFlop_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlop.vhd".WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored.WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored. Set property "use_clock_enable = yes" for signal <cQ>. Summary:

no macro.Unit <DFlop_2> synthesized.

Synthesizing Unit <DFlopBoolFallingEdge>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlopBoolFallingEdge.vhd". Set property "syn_preserve = true". Summary:

no macro.Unit <DFlopBoolFallingEdge> synthesized.

Synthesizing Unit <DFlopFallingEdge>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DFlopFallingEdge.vhd".WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored.WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored. Set property "use_clock_enable = yes" for signal <cQ>. Summary:

no macro.

Unit <DFlopFallingEdge> synthesized.

Synthesizing Unit <ResetSync_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ResetSync.vhd". Set property "equivalent_register_removal = no".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ResetSync.vhd" line 150: Output port <cQ> of the instance <c2ResetFe_msx> is unconnected or connected to loadless signal. Found 1-bit register for signal <c1ResetFromClk2_ms>. Found 1-bit register for signal <c1ResetFromClk2>. Found 1-bit register for signal <c2ResetLcl>. Found 1-bit register for signal <c2ResetRe_ms>. Summary:

inferred 4 D-type flip-flop(s).Unit <ResetSync_2> synthesized.


inferred 6 D-type flip-flop(s).Unit <HandshakeBaseResetCross_2> synthesized.


no macro.

Unit <DFlopSlvResetVal_3> synthesized.

Synthesizing Unit <NiFpgaRegFrameworkShiftReg>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaRegFrameworkShiftReg.vhd". Found 1-bit register for signal <ReadBlk.cRegReadLoc>. Found 1-bit register for signal <WriteBlk.cDelayedWritePulse1>. Found 1-bit register for signal <WriteBlk.cDelayedWritePulse2>. Found 96-bit register for signal <cShiftReg>. Found 3-bit register for signal <cCounter>. Found 1-bit register for signal <cReadShift>. Found 3-bit subtractor for signal <GND_1862_o_GND_1862_o_sub_5_OUT<2:0>> created at line 1308. Summary:


Unit <NiFpgaRegFrameworkShiftReg> synthesized.

Synthesizing Unit <DoubleSyncBoolAsyncIn>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncBoolAsyncIn.vhd". Summary:

no macro.Unit <DoubleSyncBoolAsyncIn> synthesized.

Synthesizing Unit <Interface>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd".WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<105:105>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<211:211>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<317:317>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<423:423>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<529:529>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<635:635>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<741:741>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<847:847>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<953:953>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<1059:1059>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<1165:1165>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<1271:1271>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<1377:1377>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<1483:1483>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<1589:1589>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo<1695:1695>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<0>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<1>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<3>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<4>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<5>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<6>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<7>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<8>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<9>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<10>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<11>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<12>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<13>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<14>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaDataOutArray<15>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<0>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<1>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<2>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<3>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<4>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<5>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<6>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<7>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<8>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<9>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<10>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<11>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<12>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<13>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<14>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtCountArray<15>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaCtEnableOutArray> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateEnableOutArray> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<15>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<14>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<13>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<12>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<11>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<10>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<9>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<8>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<7>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<6>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<5>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<4>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<3>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<2>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<1>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <DmaStreamStateOutArray<0>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateEnableOutArray> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<15>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<14>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<13>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<12>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<11>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<10>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<9>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<8>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<7>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<6>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<5>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<4>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<3>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<2>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<1>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStreamStateOutArray<0>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<15>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<14>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<13>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<12>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<11>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<10>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<9>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<8>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<7>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<6>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<5>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<4>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<3>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<2>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<1>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dCurrentStreamStateArray<0>> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStartRequestEnableOutArray> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStopRequestEnableOutArray> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStopWithFlushRequestEnableOutArray> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 232: Output port <dStopWithFlushRequestTimedOutArray> of the instance <ChinchDmaFifosx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 303: Output port <iIrqAckStatus> of the instance <IrqComponents[0].ChinchLvFpgaIrqx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 303: Output port <iIrqEnableOut> of the instance <IrqComponents[0].ChinchLvFpgaIrqx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Interface.vhd" line 303: Output port <iIrqAckStatusEnableOut> of the instance <IrqComponents[0].ChinchLvFpgaIrqx> is unconnected or connected to loadless signal.WARNING:Xst:653 - Signal <DmaClkArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<4>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<5>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<6>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<7>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.

WARNING:Xst:653 - Signal <DmaRwDataInArray<9>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<11>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<12>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<13>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwDataInArray<15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<4>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<5>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<6>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<7>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<9>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<11>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<12>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<13>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwTimeoutArray<15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwEnableInArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaRwEnableOutClearArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaCtEnableInArray> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaCtEnableOutClearArray> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateEnableInArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateEnableClearArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.

WARNING:Xst:653 - Signal <dStreamStateEnableInArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateEnableClearArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStartRequestEnableInArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStartRequestEnableClearArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopRequestEnableInArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopRequestEnableClearArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestEnableInArray<2:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestEnableClearArray<2:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<4>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<5>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<6>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<7>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<9>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<11>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<12>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<13>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimeoutArray<15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <iIrqOutArray[0]_IrqNum> is used but never assigned. This sourceless signal will be automatically connected to value GND. Summary:

no macro.Unit <Interface> synthesized.

Synthesizing Unit <ChinchDmaFifos>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaFifos.vhd".

WARNING:Xst:647 - Input <DmaClkArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<14>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaDataInArray<15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <DmaTimeoutArray<5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<14>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaTimeoutArray<15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaEnableInArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaEnableClearArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaCtEnableInArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaCtEnableOutClearArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaStreamStateEnableInArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DmaStreamStateEnableClearArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <dStreamStateEnableInArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStreamStateEnableClearArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStartRequestEnableInArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStartRequestEnableClearArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopRequestEnableInArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopRequestEnableClearArray<3:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestEnableInArray<2:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestEnableClearArray<2:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<14>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dStopWithFlushRequestTimeoutArray<15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[15]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[15]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[14]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[14]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[13]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[13]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[12]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[12]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[11]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[11]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[10]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[10]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[9]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[9]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[8]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[8]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[7]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[7]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[6]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[6]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[5]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[5]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[4]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[4]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[3]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[3]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[2]_BytesRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[2]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[15]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[15]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[15]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[15]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[14]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[14]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[14]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[14]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[13]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[13]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[13]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[13]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[12]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[12]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[12]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[12]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[11]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[11]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[11]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[11]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[10]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[10]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[10]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[10]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[9]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[9]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[9]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[9]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[8]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[8]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[8]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[8]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[7]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[7]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[7]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[7]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[6]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[6]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[6]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[6]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[5]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[5]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[5]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[5]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[4]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[4]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[4]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[4]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[3]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[3]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[3]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[3]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[1]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[1]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[1]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[1]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[0]_WriteLengthInBytes> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[0]_FifoData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[0]_NumWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[0]_StreamState> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[15]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[15]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[15]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[14]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[14]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[14]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[13]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[13]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[13]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[12]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[12]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[12]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[11]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[11]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[11]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[10]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[10]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[10]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[9]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[9]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[9]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[8]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[8]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[8]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[7]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[7]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[7]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[6]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[6]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[6]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[5]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[5]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[5]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[4]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[4]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[4]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[3]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[3]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[3]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[2]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[2]_Pop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceToFifo[2]_UpdateByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[15]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[15]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[15]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[15]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[14]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[14]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[14]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[14]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[13]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[13]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[13]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[13]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[12]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[12]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[12]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[12]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[11]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[11]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[11]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[11]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[10]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[10]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[10]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[10]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[9]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[9]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[9]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[9]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[8]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[8]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[8]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[8]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[7]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[7]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[7]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[7]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[6]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[6]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[6]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[6]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[5]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[5]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[5]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[5]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[4]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[4]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[4]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[4]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[3]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[3]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[3]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[3]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[1]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[1]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[1]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[1]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[0]_DmaReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[0]_FifoWrite> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[0]_RsrvWriteSpaces> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo[0]_ReportDisabledToDiagram> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:653 - Signal <DmaDataOutArray<2><63:16>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaCtEnableOutArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateEnableOutArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<13>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<12>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<11>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<9>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<7>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<6>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<5>> is used but never assigned. This sourceless signal will be automatically connected to value GND.

WARNING:Xst:653 - Signal <DmaStreamStateOutArray<4>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <DmaStreamStateOutArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateEnableOutArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<13>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<12>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<11>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<9>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<7>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<6>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<5>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<4>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStreamStateOutArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<14>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<13>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<12>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<11>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<10>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<9>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<7>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<6>> is used but never assigned. This sourceless signal will be automatically connected to value GND.

WARNING:Xst:653 - Signal <dCurrentStreamStateArray<5>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<4>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dCurrentStreamStateArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStartRequestEnableOutArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopRequestEnableOutArray<3:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestEnableOutArray<2:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dStopWithFlushRequestTimedOutArray<2:15>> is used but never assigned. This sourceless signal will be automatically connected to value GND. Summary:

no macro.Unit <ChinchDmaFifos> synthesized.

Synthesizing Unit <ChinchDmaInputFifoInterface>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 319: Output port <pDataOut> of the instance <ChinchDmaComponentEnableChainx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 319: Output port <pDisable> of the instance <ChinchDmaComponentEnableChainx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 562: Output port <bTransitionTimeoutRequestStrobe> of the instance <StreamStateBlock.StartEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 562: Output port <vTransitionRequestStrobe> of the instance <StreamStateBlock.StartEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 562: Output port <vTransitionTimeoutRequestStrobe> of the instance <StreamStateBlock.StartEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 562: Output port <vTimedOut> of the instance <StreamStateBlock.StartEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 591: Output port <bTransitionTimeoutRequestStrobe> of the instance <StreamStateBlock.StopEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 591: Output port <vTransitionTimeoutRequestStrobe> of the instance <StreamStateBlock.StopEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 591: Output port <vTimedOut> of the instance <StreamStateBlock.StopEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 620: Output port <vTransitionTimeoutRequestStrobe> of the instance <StreamStateBlock.StopWithFlushEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 656: Output port <oDataValid> of the instance

<StreamStateBlock.GenDefaultStateCrossing.HandshakeStateToDefaultClkDomain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 714: Output port <iStoredData> of the instance <StreamStateBlock.HandshakeStateToBusClkDomain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 714: Output port <iOResetStatus> of the instance <StreamStateBlock.HandshakeStateToBusClkDomain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 714: Output port <oDataValid> of the instance <StreamStateBlock.HandshakeStateToBusClkDomain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 819: Output port <iStoredData> of the instance <StreamStateBlock.HandshakeOverflowStopRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 819: Output port <oData> of the instance <StreamStateBlock.HandshakeOverflowStopRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 819: Output port <iReady> of the instance <StreamStateBlock.HandshakeOverflowStopRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 819: Output port <iOResetStatus> of the instance <StreamStateBlock.HandshakeOverflowStopRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 890: Output port <iStoredData> of the instance <BlkOverflow.HandshakeOverflow> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 890: Output port <oData> of the instance <BlkOverflow.HandshakeOverflow> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputFifoInterface.vhd" line 890: Output port <iOResetStatus> of the instance <BlkOverflow.HandshakeOverflow> is unconnected or connected to loadless signal. Found 4x2-bit Read Only RAM for signal <StreamStateBlock.dStreamStateFromController> Found 4x2-bit Read Only RAM for signal <vStreamStateFromController> Found 4x2-bit Read Only RAM for signal <StreamStateBlock.dStreamStateValue> Found 4x2-bit Read Only RAM for signal <StreamStateBlock.vStreamStateValue> Found 10-bit comparator greater for signal <vFullFromFifo> created at line 462 Summary:

inferred 4 RAM(s).inferred 1 Comparator(s).

Unit <ChinchDmaInputFifoInterface> synthesized.

Synthesizing Unit <ChinchDmaComponentEnableChain_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentEnableChain.vhd".WARNING:Xst:647 - Input <pTimeout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <pEnableClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentEnableChain.vhd" line 318: Output port <oPopFromClear> of the instance <Input.FifoClearController> is unconnected or connected to loadless signal. Found 1-bit register for signal <bEnableOutDly>. Summary:


Unit <ChinchDmaComponentEnableChain_1> synthesized.

Synthesizing Unit <NiFpgaFifoClearControl_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoClearControl.vhd".WARNING:Xst:647 - Input <iEmpty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal <cDisable>. Found 1-bit register for signal <oPopFromClear>. Found 1-bit register for signal <cEnableOutLoc>. Found 1-bit register for signal <ClearRequestNoSCL.cDelayedEnableIn>. Found 3-bit register for signal <cDisablerState>. Found finite state machine <FSM_5> for signal <cDisablerState>. ----------------------------------------------------------------------- | States | 7 | | Transitions | 18 | | Inputs | 6 | | Outputs | 9 | | Clock | CClk (rising_edge) | | Reset | aReset (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Summary:


Unit <NiFpgaFifoClearControl_1> synthesized.

Synthesizing Unit <DoubleSyncBool>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncBool.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncBool.vhd" line 58: Output port <iSigOut> of the instance <DoubleSyncBasex> is unconnected or connected to loadless signal. Summary:

no macro.Unit <DoubleSyncBool> synthesized.

Synthesizing Unit <DoubleSyncBase>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncBase.vhd". Set property "KEEP_HIERARCHY = TRUE". Set property "syn_keep = true" for signal <iDlySig>. Summary:

no macro.Unit <DoubleSyncBase> synthesized.

Synthesizing Unit <NiFpgaFifoPortReset_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPortReset.vhd". Found 1-bit register for signal <oResetDly>. Found 1-bit register for signal <iResetFromPopDly>. Found 1-bit register for signal <iResetFromPopDlyDly>. Found 1-bit register for signal <oPopDoneState>. Found 1-bit register for signal <cPushClearDoneLocDly>. Found 1-bit register for signal <iResetDly>. Found 1-bit register for signal <iPushDoneState>. Found 1-bit register for signal <oResetFromPushDly>. Found 1-bit register for signal <oResetFromPushDlyDly>. Found 1-bit register for signal <cPopClearDoneLocDly>. Summary:

inferred 10 D-type flip-flop(s).Unit <NiFpgaFifoPortReset_1> synthesized.

Synthesizing Unit <NiFpgaPulseSyncBaseWrapper>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaPulseSyncBaseWrapper.vhd". Found 1-bit register for signal <oRegisteredSigAck>. Summary:

inferred 1 D-type flip-flop(s).Unit <NiFpgaPulseSyncBaseWrapper> synthesized.

Synthesizing Unit <InStrmFifo>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmFifo.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmFifo.vhd" line 146: Output port <iWriteEnables> of the instance <InStrmFifoFlagsx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <InStrmFifo> synthesized.

Synthesizing Unit <InStrmFifoFlags>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmFifoFlags.vhd". Found 1-bit register for signal <iWritesDisabledSampPtrUnsGray>. Found 1-bit register for signal <iWritesDisabledSampPtrUns>. Found 1-bit register for signal <oPush_ms>. Found 1-bit register for signal <oPush>. Found 10-bit register for signal <oReadAddUns>. Found 10-bit register for signal <iWriteSamplePtrUns>. Found 10-bit register for signal <iWriteSamplePtrUnsGray>. Found 3-bit register for signal <oByteLanePtrLoc>. Found 10-bit register for signal <oWriteSamplePtrUns>. Found 1-bit register for signal <oWritesDisabledSamplePtrUnsGray>. Found 1-bit register for signal <oWritesDisabledLoc>. Found 10-bit register for signal <oWriteSamplePtrUnsGray_ms>. Found 10-bit register for signal <oWriteSamplePtrUnsGray>. Found 1-bit register for signal <oWritesDisabledSamplePtrUnsGray_ms>. Found 1-bit register for signal <oWritesDisabledSamplePtrUnsGrayExtraDelay_ms>. Found 3-bit adder for signal <oBytesRead[2]_oByteLanePtrLoc[2]_add_0_OUT> created at line 210.

Found 10-bit adder for signal <oReadAddUns[9]_GND_1941_o_add_4_OUT> created at line 1241. Found 10-bit adder for signal <iWriteSamplePtrUns[9]_GND_1941_o_add_17_OUT> created at line 1241. Found 10-bit subtractor for signal <GND_1941_o_GND_1941_o_sub_15_OUT<9:0>> created at line 322. Found 10-bit subtractor for signal <iEmptyCount> created at line 146. Found 10-bit subtractor for signal <oFullCount> created at line 149. Found 4x2-bit Read Only RAM for signal <_n0225> Found 8x4-bit Read Only RAM for signal <_n0234> Found 10-bit comparator equal for signal <oReadAddUns[9]_oWriteAddUns[9]_equal_34_o> created at line 474 Found 3-bit comparator greater for signal <oWriteByteLanePtrLoc[2]_oByteLanePtrLoc[2]_LessThan_35_o> created at line 482 Summary:

inferred 2 RAM(s).inferred 6 Adder/Subtractor(s).inferred 71 D-type flip-flop(s).inferred 2 Comparator(s).inferred 9 Multiplexer(s).

Unit <InStrmFifoFlags> synthesized.

Synthesizing Unit <FifoPtrClockCrossing_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FifoPtrClockCrossing.vhd". Found 1-bit register for signal <iAckRcvd>. Found 1-bit register for signal <iAckRcvdDlyd>. Found 1-bit register for signal <iTogglePush>. Found 1-bit register for signal <iTxSmState>. Found 1-bit register for signal <oPushRcvd_ms>. Found 1-bit register for signal <oPushRcvd>. Found 1-bit register for signal <oPushRcvdDlyd>. Found 1-bit register for signal <oAck>. Found 1-bit register for signal <iAckRcvd_ms>. Found 12-bit register for signal <iDataToPush>. Summary:

inferred 21 D-type flip-flop(s).Unit <FifoPtrClockCrossing_1> synthesized.



Synthesizing Unit <InStrmRAMArray>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\InStrmRAMArray.vhd". Found 1-bit register for signal <iEnables>. Found 10-bit register for signal <iAddrReg>. Found 64-bit register for signal <oDataOut>. Found 64-bit register for signal <iDataInReg>. Summary:


Unit <InStrmRAMArray> synthesized.

Synthesizing Unit <ADPRAM36K>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ADPRAM36K.vhd".WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <ADPRAM36K> synthesized.

Synthesizing Unit <NiFpgaFifoCountControl_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoCountControl.vhd". Found 1-bit register for signal <GenOthers.cEnableInReg>. Found 10-bit register for signal <cCountInQualReg>. Summary:


Unit <NiFpgaFifoCountControl_1> synthesized.

Synthesizing Unit <ChinchDmaComponentStreamStateEnableChain_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStreamStateEnableChain.vhd".WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <ViClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <vEnableClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <ChinchDmaComponentStreamStateEnableChain_1> synthesized.

Synthesizing Unit <ChinchDmaComponentStreamStateEnableChain_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStreamStateEnableChain.vhd". Found 1-bit register for signal <vEnableOut>. Found 1-bit register for signal <vEnableInDelay>. Found 2-bit register for signal <vStreamStateOut>. Summary:

inferred 4 D-type flip-flop(s).Unit <ChinchDmaComponentStreamStateEnableChain_2> synthesized.

Synthesizing Unit <ChinchDmaComponentStateTransitionEnableChain>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStateTransitionEnableChain.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStateTransitionEnableChain.vhd" line 300: Output port <iStoredData> of the instance <HandshakeTransitionRequest> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStateTransitionEnableChain.vhd" line 300: Output port <oData> of the instance <HandshakeTransitionRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStateTransitionEnableChain.vhd" line 300: Output port <iOResetStatus> of the instance <HandshakeTransitionRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStateTransitionEnableChain.vhd" line 342: Output port <iStoredData> of the instance <HandshakeTransitionTimeoutRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStateTransitionEnableChain.vhd" line 342: Output port <oData> of the instance <HandshakeTransitionTimeoutRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentStateTransitionEnableChain.vhd" line 342: Output port <iOResetStatus> of the instance <HandshakeTransitionTimeoutRequest> is unconnected or connected to loadless signal. Found 1-bit register for signal <vEnableOut>. Found 1-bit register for signal <vTimedOut>. Found 1-bit register for signal <vEnableInDelay>. Found 2-bit register for signal <vEnableChainState>. Found 32-bit register for signal <vLatchedTimeout>. Found finite state machine <FSM_6> for signal <vEnableChainState>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 12 | | Inputs | 5 | | Outputs | 2 | | Clock | ViClk (rising_edge) | | Reset | aReset (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 32-bit subtractor for signal <vLatchedTimeout[31]_GND_2001_o_sub_8_OUT<31:0>> created at line 1320. Found 1-bit 3-to-1 multiplexer for signal <vTransitionRequestStrobeLcl> created at line 148. Found 32-bit comparator greater for signal <vLatchedTimeout[31]_GND_2001_o_LessThan_7_o> created at line 208 Summary:

inferred 1 Adder/Subtractor(s).inferred 35 D-type flip-flop(s).inferred 1 Comparator(s).inferred 9 Multiplexer(s).inferred 1 Finite State Machine(s).

Unit <ChinchDmaComponentStateTransitionEnableChain> synthesized.

Synthesizing Unit <HandshakeBaseResetCross_3>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBaseResetCross.vhd". Set property "syn_keep = true" for signal <iPush>. Set property "syn_keep = true" for signal <iDlyPush>. Set property "syn_keep = true" for signal <iLclReady>.

Set property "use_clock_enable = yes" for signal <oPushToggleToReady>. Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>. Set property "syn_keep = true" for signal <BlkOut.oDataAckClkEnable>.WARNING:Xst:37 - Detected unknown constraint/property "syn_direct_enable". This constraint/property is not supported by the current software release and will be ignored. Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>.WARNING:Xst:647 - Input <aResetToDlyPush> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aResetToIResetFast> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aPushToggleDly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBaseResetCross.vhd" line 382: Output port <c1ResetFast> of the instance <BlkOut.SyncOReset> is unconnected or connected to loadless signal. Found 1-bit register for signal <BlkRdy.iRdyPushToggle>. Found 1-bit register for signal <iLclReady>. Found 1-bit register for signal <iDlyPush>. Found 1-bit register for signal <BlkOut.oPushToggle1>. Found 1-bit register for signal <BlkOut.oPushToggle2>. Found 1-bit register for signal <oDataValid>. Summary:






Synthesizing Unit <HandshakeBase_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBase.vhd". Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>. Set property "syn_maxfan = 1000000" for signal <BlkRdy.iReset_ms>. Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>. Found 1-bit register for signal <BlkRdy.iReset>. Found 1-bit register for signal <BlkRdy.iReset_ms>. Found 1-bit register for signal <iPushToggle>. Found 1-bit register for signal <BlkOut.oPushToggle0_ms>. Found 1-bit register for signal <BlkOut.oPushToggle1>.

Found 1-bit register for signal <BlkOut.oPushToggle2>. Found 1-bit register for signal <oDataValid>. Found 1-bit register for signal <oPushToggleToReady>. Found 1-bit register for signal <BlkRdy.iRdyPushToggle_ms>. Found 1-bit register for signal <BlkRdy.iRdyPushToggle>. Found 1-bit register for signal <iLclReady>. Found 1-bit register for signal <iDlyPush>. Found 2-bit register for signal <iLclStoredData>. Summary:


Synthesizing Unit <ChinchDmaComponentInputStateHolder>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentInputStateHolder.vhd". Found 1-bit register for signal <vFlushingLatch>. Summary:


Unit <ChinchDmaComponentInputStateHolder> synthesized.

Synthesizing Unit <ChinchDmaOutputFifoInterface>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd".WARNING:Xst:647 - Input <bOutputStreamInterfaceToFifo_NumWriteSpaces<31:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 370: Output port <cPopFlag> of the instance <NiFpgaFifoPopBufferx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 429: Output port <iByteLanePtr> of the instance <OutStrmFifox> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 562: Output port <bTransitionTimeoutRequestStrobe> of the instance <StreamStateBlock.StartEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 562: Output port <vTransitionRequestStrobe> of the instance <StreamStateBlock.StartEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 562: Output port <vTransitionTimeoutRequestStrobe> of the instance <StreamStateBlock.StartEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 562: Output port <vTimedOut> of the instance <StreamStateBlock.StartEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 590: Output port <bTransitionTimeoutRequestStrobe> of the instance <StreamStateBlock.StopEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 590: Output port <vTransitionTimeoutRequestStrobe> of the instance <StreamStateBlock.StopEnableChain> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 590: Output port <vTimedOut> of the instance <StreamStateBlock.StopEnableChain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 687: Output port <iStoredData> of the instance <StreamStateBlock.HandshakeStateToBusClkDomain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 687: Output port <iOResetStatus> of the instance <StreamStateBlock.HandshakeStateToBusClkDomain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 687: Output port <oDataValid> of the instance <StreamStateBlock.HandshakeStateToBusClkDomain> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 793: Output port <iStoredData> of the instance <StreamStateBlock.HandshakeUnderflowStopRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 793: Output port <oData> of the instance <StreamStateBlock.HandshakeUnderflowStopRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 793: Output port <iReady> of the instance <StreamStateBlock.HandshakeUnderflowStopRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 793: Output port <iOResetStatus> of the instance <StreamStateBlock.HandshakeUnderflowStopRequest> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 903: Output port <iStoredData> of the instance <BlkUnderflow.HandshakeUnderflow> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 903: Output port <oData> of the instance <BlkUnderflow.HandshakeUnderflow> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 903: Output port <iOResetStatus> of the instance <BlkUnderflow.HandshakeUnderflow> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 947: Output port <iStoredData> of the instance <HandshakeFullCount> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 947: Output port <iOResetStatus> of the instance <HandshakeFullCount> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputFifoInterface.vhd" line 947: Output port <oDataValid> of the instance <HandshakeFullCount> is unconnected or connected to loadless signal. Found 2-bit register for signal <StreamStateBlock.vStreamStateValueDelays<0>>. Found 4x2-bit Read Only RAM for signal <StreamStateBlock.vStreamStateValue> Found 4x2-bit Read Only RAM for signal <bStreamStateValue> Found 4x2-bit Read Only RAM for signal <StreamStateBlock.dStreamState> Summary:

inferred 3 RAM(s).inferred 2 D-type flip-flop(s).inferred 1 Multiplexer(s).

Unit <ChinchDmaOutputFifoInterface> synthesized.

Synthesizing Unit <ChinchDmaComponentEnableChain_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentEnableChain.vhd".WARNING:Xst:647 - Input <pTimeout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <pEnableClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentEnableChain.vhd" line 343: Output port <oPopFromClear> of the instance <Output.FifoClearController> is unconnected or connected to loadless signal. Found 1-bit register for signal <bEnableOutDly>. Summary:


Unit <ChinchDmaComponentEnableChain_2> synthesized.

Synthesizing Unit <NiFpgaFifoClearControl_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoClearControl.vhd".WARNING:Xst:647 - Input <oEmpty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:2935 - Signal 'oPopFromClear', unconnected in block 'NiFpgaFifoClearControl_2', is tied to its initial value (0). Found 1-bit register for signal <cDisable>. Found 1-bit register for signal <cEnableOutLoc>. Found 1-bit register for signal <ClearRequestNoSCL.cDelayedEnableIn>. Found 3-bit register for signal <cDisablerState>. Found finite state machine <FSM_7> for signal <cDisablerState>. ----------------------------------------------------------------------- | States | 7 | | Transitions | 18 | | Inputs | 6 | | Outputs | 9 | | Clock | CClk (rising_edge) | | Reset | aReset (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Summary:


Unit <NiFpgaFifoClearControl_2> synthesized.

Synthesizing Unit <NiFpgaFifoPortReset_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPortReset.vhd". Found 1-bit register for signal <oResetDly>.

Found 1-bit register for signal <iResetFromPopDly>. Found 1-bit register for signal <iResetFromPopDlyDly>. Found 1-bit register for signal <oPopDoneState>. Found 1-bit register for signal <cPushClearDoneLocDly>. Found 1-bit register for signal <iResetDly>. Found 1-bit register for signal <iPushDoneState>. Found 1-bit register for signal <oResetFromPushDly>. Found 1-bit register for signal <oResetFromPushDlyDly>. Found 1-bit register for signal <cPopClearDoneLocDly>. Summary:

inferred 10 D-type flip-flop(s).Unit <NiFpgaFifoPortReset_2> synthesized.

Synthesizing Unit <NiFpgaFifoPopBuffer>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPopBuffer.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPopBuffer.vhd" line 349: Output port <cPushFlag> of the instance <NiFpgaFlipFlopFifox> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoPopBuffer.vhd" line 349: Output port <cPopFlag> of the instance <NiFpgaFlipFlopFifox> is unconnected or connected to loadless signal. Found 1-bit register for signal <FullCountBlk.cExtendedCountAvailable>. Found 1-bit register for signal <DelayBlk.cPushes>. Found 2-bit register for signal <FullCountBlk.cPendingPushes>. Found 3-bit register for signal <FullCountBlk.cBufferFullCountPlusPendingPushes>. Found 2-bit adder for signal <FullCountBlk.cPendingPushes[1]_GND_2571_o_add_3_OUT> created at line 1241. Found 3-bit adder for signal <cBufferFullCount[2]_GND_2571_o_add_12_OUT> created at line 1241. Found 3-bit adder for signal <GND_2571_o_FullCountBlk.cNxBufferFullCount[2]_add_18_OUT> created at line 288. Found 11-bit adder for signal <GND_2571_o_GND_2571_o_add_21_OUT> created at line 301. Found 2-bit subtractor for signal <GND_2571_o_GND_2571_o_sub_2_OUT<1:0>> created at line 1308. Found 3-bit subtractor for signal <GND_2571_o_GND_2571_o_sub_11_OUT<2:0>> created at line 1308. Found 10-bit comparator greater for signal <cFullCountFromFifo[9]_GND_2571_o_LessThan_1_o> created at line 125 Found 3-bit comparator lessequal for signal <n0017> created at line 223 Found 3-bit comparator greater for signal <GND_2571_o_FullCountBlk.cNxBufferFullCount[2]_LessThan_15_o> created at line 245 Found 3-bit comparator greater for signal <GND_2571_o_FullCountBlk.cNxBufferFullCount[2]_LessThan_16_o> created at line 246 Found 2-bit comparator lessequal for signal <n0033> created at line 246 Found 11-bit comparator lessequal for signal <n0048> created at line 377 WARNING:Xst:2404 - FFs/Latches <FullCountBlk.cBufferFullCountPlusPendingPushesAvailable<0:0>> (without init value) have a constant value of 0 in block <NiFpgaFifoPopBuffer>. Summary:

inferred 4 Adder/Subtractor(s).inferred 7 D-type flip-flop(s).inferred 6 Comparator(s).inferred 7 Multiplexer(s).

Unit <NiFpgaFifoPopBuffer> synthesized.

Synthesizing Unit <NiFpgaFlipFlopFifo>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFlipFlopFifo.vhd".WARNING:Xst:2935 - Signal 'cPushFlag', unconnected in block 'NiFpgaFlipFlopFifo', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'cPopFlag', unconnected in block 'NiFpgaFlipFlopFifo', is tied to its initial value (0). Found 16-bit register for signal <cFifo<5>>. Found 16-bit register for signal <cFifo<4>>. Found 16-bit register for signal <cFifo<3>>. Found 16-bit register for signal <cFifo<2>>. Found 16-bit register for signal <cFifo<1>>. Found 16-bit register for signal <cFifo<0>>. Found 3-bit register for signal <cFullCountLoc>. Found 3-bit register for signal <cEmptyCountLoc>. Found 7-bit register for signal <cFlags>. Found 3-bit adder for signal <cFullCountLoc[2]_GND_2572_o_add_24_OUT> created at line 1241. Found 3-bit adder for signal <cEmptyCountLoc[2]_GND_2572_o_add_26_OUT> created at line 1241. Found 3-bit subtractor for signal <GND_2572_o_GND_2572_o_sub_23_OUT<2:0>> created at line 1308. Found 3-bit subtractor for signal <GND_2572_o_GND_2572_o_sub_29_OUT<2:0>> created at line 1308. Summary:


Unit <NiFpgaFlipFlopFifo> synthesized.

Synthesizing Unit <OutStrmFifo>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\OutStrmFifo.vhd". Summary:

no macro.Unit <OutStrmFifo> synthesized.

Synthesizing Unit <OutStrmFifoFlags>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\OutStrmFifoFlags.vhd". Found 1-bit register for signal <iPush_ms>. Found 1-bit register for signal <iPush>. Found 1-bit register for signal <oReadEnableFlag>. Found 8-bit register for signal <oReadAddUns>. Found 10-bit register for signal <oReadSamplePtrUnsGray>. Found 10-bit register for signal <iReqSamplePtrUns>. Found 10-bit register for signal <oFullCount>. Found 11-bit register for signal <iWriteSamplePtrUnsBytes>. Found 3-bit register for signal <oByteLanePtrLoc>. Found 10-bit register for signal <iReadSamplePtrUnsGray_ms>. Found 10-bit register for signal <iReadSamplePtrUnsGray>. Found 10-bit register for signal <iReadSamplePtrUns>. Found 3-bit adder for signal <GND_2575_o_oByteLanePtrLoc[2]_add_0_OUT> created at line 1247. Found 8-bit adder for signal <oReadAddUns[7]_GND_2575_o_add_5_OUT> created at line 1241.

Found 11-bit adder for signal <iWriteSamplePtrUnsBytes[10]_GND_2575_o_add_19_OUT> created at line 345. Found 10-bit adder for signal <iReqSamplePtrUns[9]_iReqWriteSamples[9]_add_24_OUT> created at line 363. Found 5-bit adder for signal <n0196> created at line 457. Found 4-bit adder for signal <n0198> created at line 498. Found 10-bit subtractor for signal <GND_2575_o_GND_2575_o_sub_18_OUT<9:0>> created at line 331. Found 10-bit subtractor for signal <iEmptyCount> created at line 162. Found 10-bit subtractor for signal <oLclFullCountNx> created at line 198. Found 3-bit subtractor for signal <GND_2575_o_GND_2575_o_sub_37_OUT<2:0>> created at line 457. Found 3-bit subtractor for signal <GND_2575_o_GND_2575_o_sub_72_OUT<2:0>> created at line 498. Found 10-bit comparator equal for signal <iRsrvdSpacesFilled> created at line 368 Found 3-bit comparator lessequal for signal <n0058> created at line 457 Found 3-bit comparator lessequal for signal <n0061> created at line 456 Found 3-bit comparator lessequal for signal <n0063> created at line 457 Found 3-bit comparator lessequal for signal <n0067> created at line 456 Found 3-bit comparator lessequal for signal <n0069> created at line 457 Found 3-bit comparator lessequal for signal <n0073> created at line 456 Found 3-bit comparator lessequal for signal <n0075> created at line 457 Found 3-bit comparator lessequal for signal <n0079> created at line 456 Found 3-bit comparator lessequal for signal <n0081> created at line 457 Found 3-bit comparator lessequal for signal <n0085> created at line 456 Found 3-bit comparator lessequal for signal <n0087> created at line 457 Found 3-bit comparator lessequal for signal <n0091> created at line 456 Found 3-bit comparator lessequal for signal <n0093> created at line 457 Found 3-bit comparator lessequal for signal <n0097> created at line 456 Summary:


Unit <OutStrmFifoFlags> synthesized.

Synthesizing Unit <FifoPtrClockCrossing_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FifoPtrClockCrossing.vhd". Found 1-bit register for signal <iAckRcvd>. Found 1-bit register for signal <iAckRcvdDlyd>. Found 1-bit register for signal <iTogglePush>. Found 1-bit register for signal <iTxSmState>. Found 1-bit register for signal <oPushRcvd_ms>. Found 1-bit register for signal <oPushRcvd>. Found 1-bit register for signal <oPushRcvdDlyd>. Found 1-bit register for signal <oAck>. Found 1-bit register for signal <iAckRcvd_ms>. Found 13-bit register for signal <iDataToPush>. Summary:

inferred 22 D-type flip-flop(s).Unit <FifoPtrClockCrossing_2> synthesized.



Synthesizing Unit <OutStrmDPRAM>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\OutStrmDPRAM.vhd". Found 3-bit register for signal <oByteLanePtrDelay>. Found 32-bit adder for signal <oByteLaneInt[28]_GND_2578_o_add_8_OUT> created at line 298. Found 7-bit subtractor for signal <GND_2578_o_GND_2578_o_sub_10_OUT<6:0>> created at line 298. Summary:


Unit <OutStrmDPRAM> synthesized.

Synthesizing Unit <DPRAM64Bits>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DPRAM64Bits.vhd". Summary:

no macro.Unit <DPRAM64Bits> synthesized.

Synthesizing Unit <DPRAM32Bits>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DPRAM32Bits.vhd". Summary:

inferred 4 Multiplexer(s).Unit <DPRAM32Bits> synthesized.



Synthesizing Unit <NiFpgaFifoCountControl_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaFifoCountControl.vhd". Found 1-bit register for signal <GenOthers.cEnableInReg>. Found 11-bit register for signal <cCountInQualReg>. Summary:


Unit <NiFpgaFifoCountControl_2> synthesized.

Synthesizing Unit <ChinchDmaComponentOutputStateHolder>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaComponentOutputStateHolder.vhd". Found 1-bit register for signal <vDisabledLatch>. Summary:


Unit <ChinchDmaComponentOutputStateHolder> synthesized.





Synthesizing Unit <ChinchLvFpgaIrq>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaIrq.vhd".WARNING:Xst:647 - Input <iIrqAckStatusEnableClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaIrq.vhd" line 397: Output port <iStoredData> of the instance <HandshakeIrqNum> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaIrq.vhd" line 397: Output port <iOResetStatus> of the instance <HandshakeIrqNum> is unconnected or connected to loadless signal. Found 1-bit register for signal <iPushIrqNumState>. Found 1-bit register for signal <iIrqEnableOut>.

Found 1-bit register for signal <bDiagramReset>. Found 2-bit register for signal <n0408[1:0]>. Found 2-bit register for signal <n0409[1:0]>. Found 2-bit register for signal <n0410[1:0]>. Found 2-bit register for signal <n0411[1:0]>. Found 2-bit register for signal <n0412[1:0]>. Found 2-bit register for signal <n0413[1:0]>. Found 2-bit register for signal <n0414[1:0]>. Found 2-bit register for signal <n0415[1:0]>. Found 2-bit register for signal <n0416[1:0]>. Found 2-bit register for signal <n0417[1:0]>. Found 2-bit register for signal <n0418[1:0]>. Found 2-bit register for signal <n0419[1:0]>. Found 2-bit register for signal <n0420[1:0]>. Found 2-bit register for signal <n0421[1:0]>. Found 2-bit register for signal <n0422[1:0]>. Found 2-bit register for signal <n0423[1:0]>. Found 2-bit register for signal <n0424[1:0]>. Found 2-bit register for signal <n0425[1:0]>. Found 2-bit register for signal <n0426[1:0]>. Found 2-bit register for signal <n0427[1:0]>. Found 2-bit register for signal <n0428[1:0]>. Found 2-bit register for signal <n0429[1:0]>. Found 2-bit register for signal <n0430[1:0]>. Found 2-bit register for signal <n0431[1:0]>. Found 2-bit register for signal <n0432[1:0]>. Found 2-bit register for signal <n0433[1:0]>. Found 2-bit register for signal <n0434[1:0]>. Found 2-bit register for signal <n0435[1:0]>. Found 2-bit register for signal <n0436[1:0]>. Found 2-bit register for signal <n0437[1:0]>. Found 2-bit register for signal <n0438[1:0]>. Found 2-bit register for signal <n0439[1:0]>. Found 2-bit register for signal <n0440[1:0]>. Found 2-bit register for signal <n0407[1:0]>. Found 2-bit register for signal <n0406>. Found 1-bit register for signal <bIeReg>. Found 32-bit register for signal <bMaskReg>. Found 32-bit register for signal <bStatusReg>. Found 32-bit register for signal <bIrqClear>. Found 32-bit register for signal <bRegPortOutLcl_Data>. Found 1-bit register for signal <bRegPortOutLcl_DataValid>. Found 1-bit register for signal <bPushIrqAckHold>. Found 1-bit register for signal <bRegPortOutLcl_Ready>. Found 32-bit register for signal <bIrqAck>. Found 1-bit register for signal <bDiagramReset_ms>. Found 5 bit to 32 bit decoder compact to one-hot for signal <bIrqNum[4]_Decoder_110_OUT> created at line 268 Summary:

inferred 237 D-type flip-flop(s).inferred 43 Multiplexer(s).inferred 1 Decoder(s).

Unit <ChinchLvFpgaIrq> synthesized.







Synthesizing Unit <HandshakeBase_3>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBase.vhd". Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>.

Set property "syn_maxfan = 1000000" for signal <BlkRdy.iReset_ms>. Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>. Found 1-bit register for signal <BlkRdy.iReset>. Found 1-bit register for signal <BlkRdy.iReset_ms>. Found 1-bit register for signal <iPushToggle>. Found 1-bit register for signal <BlkOut.oPushToggle0_ms>. Found 1-bit register for signal <BlkOut.oPushToggle1>. Found 1-bit register for signal <BlkOut.oPushToggle2>. Found 1-bit register for signal <oDataValid>. Found 1-bit register for signal <oPushToggleToReady>. Found 1-bit register for signal <BlkRdy.iRdyPushToggle_ms>. Found 1-bit register for signal <BlkRdy.iRdyPushToggle>. Found 1-bit register for signal <iLclReady>. Found 1-bit register for signal <iDlyPush>. Found 32-bit register for signal <iLclStoredData>. Summary:


Synthesizing Unit <FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopEnInIClk>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopEnInIClk.vhd".WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopEnInIClk> synthesized.

Synthesizing Unit <ViControl>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ViControl.vhd". Set property "equivalent_register_removal = no". Set property "syn_keep = true" for signal <rDiagramResetAssertionErr>. Set property "syn_keep = true" for signal <rEnableIn>. Set property "syn_keep = true" for signal <rEnableClear>. Set property "syn_keep = true" for signal <EnableInBlk.tEnableIn_ms>. Set property "syn_keep = true" for signal <EnableInBlk.bEnableIn_ms>. Set property "syn_keep = true" for signal <EnableClearBlk.bEnableClear_ms>. Set property "syn_keep = true" for signal <EnableClearBlk.tEnableClear_ms>. Set property "syn_keep = true" for signal <DerivedClkLockBlk.bDerivedClkLostLock_ms>. Set property "syn_keep = true" for signal <GatedClkStartupErrBlk.bGatedClkStartupErr_ms>. Set property "syn_keep = true" for signal <EnableDeassertionErrBlk.bEnableDeassertionErr_ms>. Set property "syn_keep = true" for signal <DiagramResetAssertionErrBlk.bDiagramResetAssertionErr_ms>.WARNING:Xst:647 - Input <bHostReadIn<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bHostWriteIn<2:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bHostWriteIn<33:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal <EnableInBlk.tEnableIn_ms>. Found 1-bit register for signal <EnableInBlk.tEnableInLoc>. Found 1-bit register for signal <rEnableClear>. Found 1-bit register for signal <EnableClearBlk.tEnableClear_ms>. Found 1-bit register for signal <EnableClearBlk.tEnableClearLoc>. Found 1-bit register for signal <EnableOutBlk.tDiagramEnableOutReg>. Found 1-bit register for signal <EnableOutBlk.bEnableOut_ms>. Found 1-bit register for signal <bEnableOut>. Found 1-bit register for signal <EnableInBlk.rFirstRunAfterConfig>. Found 3-bit register for signal <EnableInBlk.rEnableInState>. Found 5-bit register for signal <EnableInBlk.rTimerCount>. Found 1-bit register for signal <rEnableIn>. Found 1-bit register for signal <EnableInBlk.rEnableClksForViRunLoc>. Found 1-bit register for signal <EnableInBlk.bEnableIn_ms>. Found 1-bit register for signal <bEnableIn>. Found 1-bit register for signal <EnableClearBlk.bEnableClear_ms>. Found 1-bit register for signal <bEnableClear>. Found 1-bit register for signal <bTimeout>. Found 1-bit register for signal <DerivedClkLockBlk.rDerivedClkLostLock>. Found 1-bit register for signal <DerivedClkLockBlk.bDerivedClkLostLock_ms>. Found 1-bit register for signal <bDerivedClkLostLock>. Found 1-bit register for signal <GatedClkStartupErrBlk.rGatedClkStartupErr>. Found 1-bit register for signal <GatedClkStartupErrBlk.bGatedClkStartupErr_ms>. Found 1-bit register for signal <bGatedClkStartupErr>. Found 1-bit register for signal <EnableDeassertionErrBlk.rEnableDeassertionErr>. Found 1-bit register for signal <EnableDeassertionErrBlk.bEnableDeassertionErr_ms>. Found 1-bit register for signal <bEnableDeassertionErr>. Found 1-bit register for signal <DiagramResetAssertionErrBlk.bDiagramResetAssertionErr_ms>. Found 1-bit register for signal <bDiagramResetAssertionErr>.INFO:Xst:1799 - State waituntilinternalclocksbecomevalid is never reached in FSM <EnableInBlk.rEnableInState>.INFO:Xst:1799 - State enableindeassertionnotsupportederr is never reached in FSM <EnableInBlk.rEnableInState>. Found finite state machine <FSM_8> for signal <EnableInBlk.rEnableInState>. ----------------------------------------------------------------------- | States | 6 | | Transitions | 8 | | Inputs | 5 | | Outputs | 8 | | Clock | ReliableClk (rising_edge) | | Reset | rDiagramResetStatus (positive) | | Reset type | synchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT |

----------------------------------------------------------------------- Found 5-bit subtractor for signal <GND_3182_o_GND_3182_o_sub_14_OUT<4:0>> created at line 582.INFO:Xst:2774 - HDL ADVISOR - KEEP property attached to signal rEnableIn may hinder XST clustering optimizations. Summary:


Unit <ViControl> synthesized.

Synthesizing Unit <SafeBusCrossing_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SafeBusCrossing.vhd". Set property "equivalent_register_removal = no".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SafeBusCrossing.vhd" line 280: Output port <iStoredData> of the instance <ClockDomainCrossing.BusClkToReliableClkHS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SafeBusCrossing.vhd" line 280: Output port <iOResetStatus> of the instance <ClockDomainCrossing.BusClkToReliableClkHS> is unconnected or connected to loadless signal. Found 1-bit register for signal <bPushEnDly>. Found 1-bit register for signal <bPushDly>. Found 2-bit register for signal <ClockDomainCrossing.bDataDly>. Found 1-bit register for signal <bReadyLoc>. Summary:

inferred 5 D-type flip-flop(s).Unit <SafeBusCrossing_1> synthesized.

Synthesizing Unit <DiagramReset>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DiagramReset.vhd". Set property "equivalent_register_removal = no". Set property "syn_maxfan = 100000000" for signal <rDiagramReset>. Set property "syn_maxfan = 100000000" for signal <aDiagramReset>. Set property "syn_keep = true" for signal <bDiagramResetForHost_ms>. Set property "syn_keep = true" for signal <rDiagramResetForHost>. Set property "KEEP = TRUE" for signal <DiagramResetFSM.rStartFsmOnDld>. Set property "KEEP = TRUE" for signal <DiagramResetFSM.rStartFsmOnDldDly>. Set property "KEEP = TRUE" for signal <DiagramResetFSM.rStartFsmOnDld_ms>. Set property "syn_keep = true" for signal <DiagramResetRegisterBlk.rDiagramResetLoc>. Set property "syn_keep = true" for signal <DiagramResetRegisterBlk.aDiagramResetLoc>.WARNING:Xst:647 - Input <bHostReadIn<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bHostWriteIn<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bHostWriteIn<33:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DiagramReset.vhd" line 374: Output port <rData> of the instance <HostWtAccessBlk.BusClkToReliableClkHS> is unconnected or connected to loadless signal. Found 1-bit register for signal <DiagramResetFSM.rStartFsmOnDld>. Found 1-bit register for signal <DiagramResetFSM.rStartFsmOnDldDly>. Found 4-bit register for signal <DiagramResetFSM.rDiagramResetState>. Found 8-bit register for signal <DiagramResetFSM.rTimerCount>. Found 1-bit register for signal <DiagramResetFSM.rDcmPllSourceClksValidLoc>. Found 1-bit register for signal <DiagramResetFSM.rAssumeExternalClkInvalidLoc>. Found 1-bit register for signal <DiagramResetFSM.rInternalClksValidLoc>. Found 1-bit register for signal <DiagramResetFSM.rDiagramResetAssertionErrLoc>. Found 1-bit register for signal <rDiagramResetForHost>. Found 1-bit register for signal <bDiagramResetForHost_ms>. Found 1-bit register for signal <bDiagramResetForHost>. Found 1-bit register for signal <DiagramResetFSM.rStartFsmOnDld_ms>.INFO:Xst:1799 - State waitforclkenablerequest is never reached in FSM <DiagramResetFSM.rDiagramResetState>.INFO:Xst:1799 - State diagrstassertionnotsupportederr is never reached in FSM <DiagramResetFSM.rDiagramResetState>. Found finite state machine <FSM_9> for signal <DiagramResetFSM.rDiagramResetState>. ----------------------------------------------------------------------- | States | 11 | | Transitions | 17 | | Inputs | 8 | | Outputs | 4 | | Clock | ReliableClk (rising_edge) | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 8-bit subtractor for signal <GND_3282_o_GND_3282_o_sub_25_OUT<7:0>> created at line 728. Summary:


Unit <DiagramReset> synthesized.

Synthesizing Unit <SafeBusCrossing_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SafeBusCrossing.vhd". Set property "equivalent_register_removal = no".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SafeBusCrossing.vhd" line 280: Output port <iStoredData> of the instance <ClockDomainCrossing.BusClkToReliableClkHS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\SafeBusCrossing.vhd" line 280: Output port <iOResetStatus> of the instance <ClockDomainCrossing.BusClkToReliableClkHS> is unconnected or connected to loadless signal. Found 1-bit register for signal <bPushEnDly>. Found 1-bit register for signal <bPushDly>. Found 1-bit register for signal <bReadyLoc>.

WARNING:Xst:2404 - FFs/Latches <ClockDomainCrossing.bDataDly<0><0:0>> (without init value) have a constant value of 0 in block <SafeBusCrossing_2>. Summary:

inferred 3 D-type flip-flop(s).Unit <SafeBusCrossing_2> synthesized.

Synthesizing Unit <HandshakeBaseResetCross_6>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBaseResetCross.vhd". Set property "syn_keep = true" for signal <iPush>. Set property "syn_keep = true" for signal <iDlyPush>. Set property "syn_keep = true" for signal <iLclReady>. Set property "use_clock_enable = yes" for signal <oPushToggleToReady>. Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>. Set property "syn_keep = true" for signal <BlkOut.oDataAckClkEnable>.WARNING:Xst:37 - Detected unknown constraint/property "syn_direct_enable". This constraint/property is not supported by the current software release and will be ignored. Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>.WARNING:Xst:647 - Input <aResetToDlyPush> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aResetToIResetFast> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aPushToggleDly> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeBaseResetCross.vhd" line 382: Output port <c1ResetFast> of the instance <BlkOut.SyncOReset> is unconnected or connected to loadless signal. Found 1-bit register for signal <BlkOut.oPushToggle1>. Found 1-bit register for signal <BlkOut.oPushToggle2>. Found 1-bit register for signal <oDataValid>. Found 1-bit register for signal <BlkRdy.iRdyPushToggle>. Found 1-bit register for signal <iLclReady>. Found 1-bit register for signal <iDlyPush>. Summary:




Synthesizing Unit <ViSignature>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ViSignature.vhd".WARNING:Xst:647 - Input <clkHostReadFromReshold<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <ViSignature> synthesized.

Synthesizing Unit <NiFpgaCtrlIndRegister_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaCtrlIndRegister.vhd".WARNING:Xst:647 - Input <cFpgaReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <NiFpgaCtrlIndRegister_1> synthesized.

Synthesizing Unit <NiFpgaHostAccessibleRegister_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaHostAccessibleRegister.vhd". Found 1-bit register for signal <cQ>. Summary:


Unit <NiFpgaHostAccessibleRegister_1> synthesized.






Synthesizing Unit <NiFpgaCtrlIndRegister_3>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaCtrlIndRegister.vhd".WARNING:Xst:647 - Input <cFpgaWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaCtrlIndRegister.vhd" line 331: Output port <cFpgaDataEnable> of the instance <PlainIndicator.PlainIndicator> is unconnected or connected to loadless signal. Summary:







Synthesizing Unit <NiFpgaCtrlIndRegister_5>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaCtrlIndRegister.vhd".WARNING:Xst:647 - Input <cFpgaReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:





Synthesizing Unit <CustomArbForOutPortPortOnResFGPA_Globals_viBit00>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viBit00.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viBit00.vhd" line 38: Output port <oDataValid> of the instance <HandshakeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv> is unconnected or connected to loadless signal. Summary:

no macro.Unit <CustomArbForOutPortPortOnResFGPA_Globals_viBit00> synthesized.

Synthesizing Unit <HandshakeWithResetValueSLV>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeWithResetValueSLV.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeWithResetValueSLV.vhd" line 56: Output port <iStoredData> of the instance <HBx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <HandshakeWithResetValueSLV> synthesized.

Synthesizing Unit <HandshakeWithResetValueBase>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\HandshakeWithResetValueBase.vhd". Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>. Set property "syn_maxfan = 1000000" for signal <BlkRdy.iReset_ms>. Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>. Found 1-bit register for signal <BlkRdy.iReset>. Found 1-bit register for signal <BlkRdy.iReset_ms>. Found 1-bit register for signal <iPushToggle>. Found 1-bit register for signal <BlkOut.oPushToggle0_ms>.

Found 1-bit register for signal <BlkOut.oPushToggle1>. Found 1-bit register for signal <BlkOut.oPushToggle2>. Found 1-bit register for signal <oDataValid>. Found 1-bit register for signal <oPushToggleToReady>. Found 1-bit register for signal <BlkRdy.iRdyPushToggle_ms>. Found 1-bit register for signal <BlkRdy.iRdyPushToggle>. Found 1-bit register for signal <iLclReady>. Found 1-bit register for signal <iDlyPush>. Found 16-bit register for signal <iLclStoredData>. Summary:

inferred 28 D-type flip-flop(s).Unit <HandshakeWithResetValueBase> synthesized.



Synthesizing Unit <CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Gen_Reset7>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Gen_Reset7.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Gen_Reset7> synthesized.

Synthesizing Unit <DoubleSyncWithResetValueSLV>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncWithResetValueSLV.vhd". Summary:

no macro.Unit <DoubleSyncWithResetValueSLV> synthesized.

Synthesizing Unit <DoubleSyncWithResetValueSL>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncWithResetValueSL.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncWithResetValueSL.vhd" line 58: Output port <iSigOut> of the instance <DoubleSyncBasex> is unconnected or connected to loadless signal. Summary:

no macro.Unit <DoubleSyncWithResetValueSL> synthesized.

Synthesizing Unit <CustomArbForTopEnablesPortOnResTopEnablePassThru>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForTopEnablesPortOnResTopEnablePassThru.vhd".

WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder00000000> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder00000001> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder00000002> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk2FromResholder00000003> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk3FromResholder00000004> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000005> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000006> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000007> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000008> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000009> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder0000000A> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder0000000B> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder0000000C> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder0000000D> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder0000000E> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder0000000F> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForTopEnablesPortOnResTopEnablePassThru> synthesized.

Synthesizing Unit <NiFpgaTopEnInSyncForExternalClk_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaTopEnInSyncForExternalClk.vhd". Set property "syn_keep = true" for signal <eTopEnInLoc>. Found 1-bit register for signal <DelayTopEnInExtClk.eStateMachineTrigger_ms>. Found 1-bit register for signal <DelayTopEnInExtClk.eStateMachineTrigger>. Found 1-bit register for signal <eTopEnInLoc>. Found 1-bit register for signal <eClrRstLoc>. Found 1-bit register for signal <SyncTopEnInToExtClk.tSyncTopEnState>. Found 3-bit register for signal <DelayTopEnInExtClk.eDelayTopEnInState>. Found 8-bit register for signal <DelayTopEnInExtClk.eTimerCount>. Found finite state machine <FSM_10> for signal <DelayTopEnInExtClk.eDelayTopEnInState>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 11 | | Inputs | 3 | | Outputs | 3 | | Clock | ExternalClk (rising_edge) | | Reset | aDiagramRst (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 8-bit subtractor for signal <GND_3446_o_GND_3446_o_sub_17_OUT<7:0>> created at line 414. Found 8-bit 5-to-1 multiplexer for signal <DelayTopEnInExtClk.eTimerSetCount> created at line 350. Summary:


Unit <NiFpgaTopEnInSyncForExternalClk_1> synthesized.

Synthesizing Unit <NiFpgaTopEnInSyncForExternalClk_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaTopEnInSyncForExternalClk.vhd". Set property "syn_keep = true" for signal <eTopEnInLoc>. Found 1-bit register for signal <DelayTopEnInExtClk.eStateMachineTrigger_ms>. Found 1-bit register for signal <DelayTopEnInExtClk.eStateMachineTrigger>. Found 1-bit register for signal <DelayTopEnInExtClk.eTimerCount>. Found 1-bit register for signal <eTopEnInLoc>. Found 1-bit register for signal <eClrRstLoc>. Found 1-bit register for signal <SyncTopEnInToExtClk.tSyncTopEnState>. Found 3-bit register for signal <DelayTopEnInExtClk.eDelayTopEnInState>. Found finite state machine <FSM_11> for signal <DelayTopEnInExtClk.eDelayTopEnInState>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 11 |

| Inputs | 3 | | Outputs | 3 | | Clock | ExternalClk (rising_edge) | | Reset | aDiagramRst (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 2-bit subtractor for signal <n0047> created at line 414. Summary:


Unit <NiFpgaTopEnInSyncForExternalClk_2> synthesized.

Synthesizing Unit <DoubleSyncSLV>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncSLV.vhd". Summary:

no macro.Unit <DoubleSyncSLV> synthesized.

Synthesizing Unit <DoubleSyncSL>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncSL.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\DoubleSyncSL.vhd" line 53: Output port <iSigOut> of the instance <DoubleSyncBasex> is unconnected or connected to loadless signal. Summary:

no macro.Unit <DoubleSyncSL> synthesized.

Synthesizing Unit <CustomArbForOutPortPortOnResFGPA_Globals_viSoftware_Trigger8>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viSoftware_Trigger8.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForOutPortPortOnResFGPA_Globals_viSoftware_Trigger8> synthesized.

Synthesizing Unit <CustomArbForOutPortPortOnResFGPA_Globals_viFetch_Length9>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viFetch_Length9.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <clk1FromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viFetch_Length9.vhd" line 38: Output port <oDataValid> of the instance <HandshakeSLVFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv> is unconnected or connected to loadless signal. Summary:

no macro.Unit <CustomArbForOutPortPortOnResFGPA_Globals_viFetch_Length9> synthesized.

Synthesizing Unit <CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Acq_Reset12>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bksl_Acq_Reset12> synthesized.

Synthesizing Unit <CustomArbForIO_Module_bksl_Program_Onboard_Clock_ctl_11RHFpgaReadPortOnResbushold>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForIO_Module_bksl_Program_Onboard_Clock_ctl_11RHFpgaReadPortOnResbushold.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForIO_Module_bksl_Program_Onboard_Clock_ctl_11RHFpgaReadPortOnResbushold> synthesized.

Synthesizing Unit <NiFpgaArbRW>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiFpgaArbRW.vhd".

WARNING:Xst:647 - Input <cFromResource> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cFromResHolders<4:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <cFromResHolders<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

inferred 3 Multiplexer(s).Unit <NiFpgaArbRW> synthesized.

Synthesizing Unit <CustomArbForIO_Module_bksl_Xpoint_Switch_Write_ctl_0RHFpgaReadPortOnResbushold>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForIO_Module_bksl_Xpoint_Switch_Write_ctl_0RHFpgaReadPortOnResbushold.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForIO_Module_bksl_Xpoint_Switch_Write_ctl_0RHFpgaReadPortOnResbushold> synthesized.

Synthesizing Unit <CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.


no macro.Unit <CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold_1> synthesized.

Synthesizing Unit <CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:




Synthesizing Unit <CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold_4>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold.vhd".

WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:





no macro.

Unit <CustomArbForBit0_ctl_3RHFpgaReadPortOnResbushold_6> synthesized.





Synthesizing Unit <CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RHFpgaReadPortOnResbushold>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RHFpgaReadPortOnResbushold.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.


no macro.Unit <CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RHFpgaReadPortOnResbushold> synthesized.

Synthesizing Unit <CustomArbForSoftware_Trigger_ctl_12RHFpgaReadPortOnResbushold>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForSoftware_Trigger_ctl_12RHFpgaReadPortOnResbushold.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForSoftware_Trigger_ctl_12RHFpgaReadPortOnResbushold> synthesized.



Synthesizing Unit <CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpgaReadPortOnResbushold>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpgaReadPortOnResbushold.vhd".

WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpgaReadPortOnResbushold> synthesized.



Synthesizing Unit <CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RHFpgaReadPortOnResbushold>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RHFpgaReadPortOnResbushold.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RHFpgaReadPortOnResbushold> synthesized.

Synthesizing Unit <CustomArbForOutPortPortOnResFGPA_Globals_viAcq_Regional_Clock_Loop11>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viAcq_Regional_Clock_Loop11.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForOutPortPortOnResFGPA_Globals_viAcq_Regional_Clock_Loop11> synthesized.

Synthesizing Unit <CustomArbForOutPortPortOnResFGPA_Globals_viClear_T2H_DMA_Timeout10>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForOutPortPortOnResFGPA_Globals_viClear_T2H_DMA_Timeout10.vhd".WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <clk1FromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <CustomArbForOutPortPortOnResFGPA_Globals_viClear_T2H_DMA_Timeout10> synthesized.

Synthesizing Unit <CustomArbForMiteIoLikePortOnResInterface>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CustomArbForMiteIoLikePortOnResInterface.vhd".WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

inferred 1 Multiplexer(s).Unit <CustomArbForMiteIoLikePortOnResInterface> synthesized.

Synthesizing Unit <NiLvFpgaClipContainer>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\NiLvFpgaClipContainer.vhd".WARNING:Xst:647 - Input <dDram0RdFifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1RdFifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <dDram0AddrFifoFull> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram0PhyInitDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram0RdDataValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram0WrFifoFull> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Dram0ClkUser> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1AddrFifoFull> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1PhyInitDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1RdDataValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1WrFifoFull> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <Dram1ClkUser> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aClockGate> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:653 - Signal <dDram0AddrFifoAddr> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram0AddrFifoCmd> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram0WrFifoDataIn> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram0WrFifoMaskData> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1AddrFifoAddr> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1AddrFifoCmd> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1WrFifoDataIn> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1WrFifoMaskData> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram0AddrFifoWrEn> is used but never assigned. This sourceless signal will be automatically connected to value GND.

WARNING:Xst:653 - Signal <dDram0WrFifoWrEn> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1AddrFifoWrEn> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1WrFifoWrEn> is used but never assigned. This sourceless signal will be automatically connected to value GND. Summary:

no macro.Unit <NiLvFpgaClipContainer> synthesized.

Synthesizing Unit <Ni6587ConnectorSerdes>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587ConnectorSerdes.vhd".WARNING:Xst:647 - Input <arBitSlipData<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <arIdelayIncData<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenDataSample0<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenDataSample1<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenDataSample2<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenDataSample3<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenDataSample4<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenDataSample5<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenDataSample6<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rAcqClkSelect<7:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rPfiClkSelect<7:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rGenClkSelect<7:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <rIoModClk1Select<7:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <rClkToSocket> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <Ni6587ConnectorSerdes> synthesized.

Synthesizing Unit <Ni6587CoreSerdes>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587CoreSerdes.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587CoreSerdes.vhd" line 120: Output port <aAcqDataFromIBuf_n> of the instance <Ni6587Basex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587CoreSerdes.vhd" line 193: Output port <rI2cReadData> of the instance <I2cReadWritex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587CoreSerdes.vhd" line 220: Output port <rXpointWriteDataDebug> of the instance <CrossSwitchSourceSelectx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <Ni6587CoreSerdes> synthesized.

Synthesizing Unit <Ni6587Base>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <O> of the instance <AcqAndGenDataNotUsed_BUFDS[0].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <OB> of the instance <AcqAndGenDataNotUsed_BUFDS[0].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <O> of the instance <AcqAndGenDataNotUsed_BUFDS[1].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <OB> of the instance <AcqAndGenDataNotUsed_BUFDS[1].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <O> of the instance <AcqAndGenDataNotUsed_BUFDS[2].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <OB> of the instance <AcqAndGenDataNotUsed_BUFDS[2].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <O> of the instance <AcqAndGenDataNotUsed_BUFDS[3].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <OB> of the instance <AcqAndGenDataNotUsed_BUFDS[3].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <O> of the instance <AcqAndGenDataNotUsed_BUFDS[4].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <OB> of the instance <AcqAndGenDataNotUsed_BUFDS[4].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <O> of the instance <AcqAndGenDataNotUsed_BUFDS[5].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <OB> of the instance <AcqAndGenDataNotUsed_BUFDS[5].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <O> of the instance <AcqAndGenDataNotUsed_BUFDS[6].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <OB> of the instance <AcqAndGenDataNotUsed_BUFDS[6].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <O> of the instance <AcqAndGenDataNotUsed_BUFDS[7].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <OB> of the instance <AcqAndGenDataNotUsed_BUFDS[7].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <O> of the instance <AcqAndGenDataNotUsed_BUFDS[8].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <OB> of the instance <AcqAndGenDataNotUsed_BUFDS[8].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <O> of the instance <AcqAndGenDataNotUsed_BUFDS[9].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Ni6587Base.vhd" line 272: Output port <OB> of the instance <AcqAndGenDataNotUsed_BUFDS[9].AcqDataNotUsed_IBufDS> is unconnected or connected to loadless signal. Found 1-bit tristate buffer for signal <aUserGpio<1>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<1>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<2>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio<3>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<3>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<4>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<4>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<5>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<5>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<6>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<6>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<7>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<7>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<8>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<8>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<9>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<9>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<10>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<10>> created at line 35

Found 1-bit tristate buffer for signal <aUserGpio<11>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<11>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<12>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<12>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<13>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<13>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<14>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<14>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<15>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<15>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<33>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<33>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<34>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<34>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio_n<35>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<37>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio_n<37>> created at line 35 Found 1-bit tristate buffer for signal <aUserGpio<42>> created at line 34 Found 1-bit tristate buffer for signal <aUserGpio<44>> created at line 34 Summary:

inferred 38 Tristate(s).Unit <Ni6587Base> synthesized.

Synthesizing Unit <AcquisitionEngine>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\AcquisitionEngine.vhd".WARNING:Xst:647 - Input <prResetSl> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <PfiClkBufR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <PfiClkBufIo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary:

no macro.Unit <AcquisitionEngine> synthesized.

Synthesizing Unit <Deserializer>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q1> of the instance <DataIoDelayGen[0].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q2> of the instance <DataIoDelayGen[0].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT1> of the instance <DataIoDelayGen[0].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT2> of the instance <DataIoDelayGen[0].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q1> of the instance <DataIoDelayGen[1].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q2> of the instance <DataIoDelayGen[1].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT1> of the instance <DataIoDelayGen[1].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT2> of the instance <DataIoDelayGen[1].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q1> of the instance <DataIoDelayGen[2].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q2> of the instance <DataIoDelayGen[2].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT1> of the instance <DataIoDelayGen[2].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT2> of the instance <DataIoDelayGen[2].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q1> of the instance <DataIoDelayGen[3].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q2> of the instance <DataIoDelayGen[3].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT1> of the instance <DataIoDelayGen[3].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT2> of the instance <DataIoDelayGen[3].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q1> of the instance <DataIoDelayGen[4].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q2> of the instance <DataIoDelayGen[4].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT1> of the instance <DataIoDelayGen[4].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT2> of the instance <DataIoDelayGen[4].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q1> of the instance <DataIoDelayGen[5].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q2> of the instance <DataIoDelayGen[5].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT1> of the instance <DataIoDelayGen[5].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT2> of the instance <DataIoDelayGen[5].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q1> of the instance <DataIoDelayGen[6].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q2> of the instance <DataIoDelayGen[6].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT1> of the instance <DataIoDelayGen[6].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT2> of the instance <DataIoDelayGen[6].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q1> of the instance <DataIoDelayGen[7].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q2> of the instance <DataIoDelayGen[7].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT1> of the instance <DataIoDelayGen[7].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT2> of the instance <DataIoDelayGen[7].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q1> of the instance <DataIoDelayGen[8].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q2> of the instance <DataIoDelayGen[8].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT1> of the instance <DataIoDelayGen[8].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT2> of the instance <DataIoDelayGen[8].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q1> of the instance <DataIoDelayGen[9].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <Q2> of the instance <DataIoDelayGen[9].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT1> of the instance <DataIoDelayGen[9].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Deserializer.vhd" line 179: Output port <SHIFTOUT2> of the instance <DataIoDelayGen[9].SlaveIserdesGen.SlaveDataISerdes> is unconnected or connected to loadless signal. Summary:

no macro.Unit <Deserializer> synthesized.

Synthesizing Unit <GenerationEngine>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\GenerationEngine.vhd".WARNING:Xst:647 - Input <prResetSl> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <PfiClkBufR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <PfiClkBufIo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <prLvdsClkOutInvert> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aLvdsClkOutEn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:653 - Signal <aLvdsClkOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <aLvdsClkOutTristate> is used but never assigned. This sourceless signal will be automatically connected to value GND. Summary:

no macro.Unit <GenerationEngine> synthesized.

Synthesizing Unit <Serializer>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd".WARNING:Xst:647 - Input <grGenData<9><9:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenData<8><9:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenData<7><9:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenData<6><9:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenData<5><9:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <grGenData<4><9:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenData<3><9:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenData<2><9:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenData<1><9:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <grGenData<0><9:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT1> of the instance <SerialGen[0].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT2> of the instance <SerialGen[0].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <OQ> of the instance <SerialGen[0].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <TQ> of the instance <SerialGen[0].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT1> of the instance <SerialGen[1].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT2> of the instance <SerialGen[1].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <OQ> of the instance <SerialGen[1].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <TQ> of the instance <SerialGen[1].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT1> of the instance <SerialGen[2].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT2> of the instance <SerialGen[2].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <OQ> of the instance <SerialGen[2].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <TQ> of the instance <SerialGen[2].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT1> of the instance <SerialGen[3].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT2> of the instance <SerialGen[3].MasterOserdes> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <OQ> of the instance <SerialGen[3].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <TQ> of the instance <SerialGen[3].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT1> of the instance <SerialGen[4].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT2> of the instance <SerialGen[4].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <OQ> of the instance <SerialGen[4].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <TQ> of the instance <SerialGen[4].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT1> of the instance <SerialGen[5].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT2> of the instance <SerialGen[5].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <OQ> of the instance <SerialGen[5].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <TQ> of the instance <SerialGen[5].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT1> of the instance <SerialGen[6].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT2> of the instance <SerialGen[6].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <OQ> of the instance <SerialGen[6].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <TQ> of the instance <SerialGen[6].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT1> of the instance <SerialGen[7].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT2> of the instance <SerialGen[7].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <OQ> of the instance <SerialGen[7].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <TQ> of the instance <SerialGen[7].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT1> of the instance <SerialGen[8].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT2> of the instance <SerialGen[8].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <OQ> of the instance <SerialGen[8].SlaveOserdes> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <TQ> of the instance <SerialGen[8].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT1> of the instance <SerialGen[9].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 99: Output port <SHIFTOUT2> of the instance <SerialGen[9].MasterOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <OQ> of the instance <SerialGen[9].SlaveOserdes> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Serializer.vhd" line 134: Output port <TQ> of the instance <SerialGen[9].SlaveOserdes> is unconnected or connected to loadless signal. Summary:

no macro.Unit <Serializer> synthesized.

Synthesizing Unit <I2cReadWrite>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\I2cReadWrite.vhd". Found 1-bit register for signal <rI2cWriteEnHold>. Found 1-bit register for signal <rI2cGoD1>. Found 8-bit register for signal <rI2cSlaveAddrHold>. Found 8-bit register for signal <rI2cByteAddrHold>. Found 8-bit register for signal <rI2cWriteDataHold>. Found 4-bit register for signal <rState>. Found finite state machine <FSM_12> for signal <rState>. ----------------------------------------------------------------------- | States | 12 | | Transitions | 23 | | Inputs | 6 | | Outputs | 15 | | Clock | rClkToSocket (rising_edge) | | Reset | aResetSl (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Summary:


Unit <I2cReadWrite> synthesized.

Synthesizing Unit <I2cIssueCycle>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\I2cIssueCycle.vhd".WARNING:Xst:647 - Input <rLvFpgaI2cAck> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal <rCycleStartD1>. Found 3-bit register for signal <rState>. Found finite state machine <FSM_13> for signal <rState>.

----------------------------------------------------------------------- | States | 6 | | Transitions | 11 | | Inputs | 4 | | Outputs | 4 | | Clock | rClkToSocket (rising_edge) | | Reset | aResetSl (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Summary:


Unit <I2cIssueCycle> synthesized.

Synthesizing Unit <CrossSwitchSourceSelect>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CrossSwitchSourceSelect.vhd". Summary:

inferred 7 Multiplexer(s).Unit <CrossSwitchSourceSelect> synthesized.

Synthesizing Unit <CrossSwitchInterface>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\CrossSwitchInterface.vhd". Found 1-bit register for signal <cXpointAccessPending>. Found 1-bit register for signal <cXpointInterfaceGoD1>. Found 1-bit register for signal <cStateMachineEnable>. Found 1-bit register for signal <aXpointSdata>. Found 1-bit register for signal <aXpointLoad>. Found 1-bit register for signal <cEnableSclk>. Found 1-bit register for signal <cControlWord<11>>. Found 1-bit register for signal <cControlWord<10>>. Found 1-bit register for signal <cControlWord<9>>. Found 1-bit register for signal <cControlWord<8>>. Found 1-bit register for signal <cControlWord<7>>. Found 1-bit register for signal <cControlWord<6>>. Found 1-bit register for signal <cControlWord<5>>. Found 1-bit register for signal <cControlWord<4>>. Found 1-bit register for signal <cControlWord<3>>. Found 1-bit register for signal <cControlWord<2>>. Found 1-bit register for signal <cControlWord<1>>. Found 1-bit register for signal <cControlWord<0>>. Found 1-bit register for signal <cXpointInterfaceBusyLcl>. Found 1-bit register for signal <aXpointSclkLcl>. Found 12-bit register for signal <cXpointWriteDataLcl>. Found 2-bit register for signal <cCounter>. Found 2-bit register for signal <cState>. Found 5-bit register for signal <cCount>. Found 1-bit register for signal <cResetSl>.

Found 1-bit register for signal <cResetSl_ms>. Found finite state machine <FSM_14> for signal <cState>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 11 | | Inputs | 3 | | Outputs | 4 | | Clock | Clk (rising_edge) | | Reset | aResetSl (positive) | | Reset type | asynchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 2-bit adder for signal <cCounter[1]_GND_3798_o_add_4_OUT> created at line 1241. Found 5-bit subtractor for signal <GND_3798_o_GND_3798_o_sub_17_OUT<4:0>> created at line 1308. Summary:


Unit <CrossSwitchInterface> synthesized.

Synthesizing Unit <TimingEngine>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimingEngine.vhd".INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\TimingEngine.vhd" line 78: Output port <RDY> of the instance <idelayctrlx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <TimingEngine> synthesized.

Synthesizing Unit <RegionalClockBuf>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\RegionalClockBuf.vhd". Summary:

no macro.Unit <RegionalClockBuf> synthesized.

Synthesizing Unit <Puma20DramMain>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd".WARNING:Xst:647 - Input <dDram0AddrFifoAddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram0AddrFifoCmd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram0WrFifoDataIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <dDram0WrFifoMaskData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1AddrFifoAddr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1AddrFifoCmd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1WrFifoDataIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1WrFifoMaskData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DramClk200> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DramClk200s90> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <DramClkDiv100> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aDiagramReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <aPll200Locked> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram0WrFifoWrEn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram0AddrFifoWrEn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1WrFifoWrEn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <dDram1AddrFifoWrEn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" line 511: Output port <O> of the instance <GenNoBank0Mig.NoMig0Gen[0].d0DDRDQS0_2Ibuf> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" line 517: Output port <O> of the instance <GenNoBank0Mig.NoMig0Gen[0].d0DDRDQS1_3Ibuf> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" line 511: Output port <O> of the instance <GenNoBank0Mig.NoMig0Gen[1].d0DDRDQS0_2Ibuf> is unconnected or connected to loadless signal.

INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" line 517: Output port <O> of the instance <GenNoBank0Mig.NoMig0Gen[1].d0DDRDQS1_3Ibuf> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" line 667: Output port <O> of the instance <GenNoBank1Mig.NoMig1Gen[0].d1DDRDQS0_2Ibuf> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" line 673: Output port <O> of the instance <GenNoBank1Mig.NoMig1Gen[0].d1DDRDQS1_3Ibuf> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" line 667: Output port <O> of the instance <GenNoBank1Mig.NoMig1Gen[1].d1DDRDQS0_2Ibuf> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\Puma20DramMain.vhd" line 673: Output port <O> of the instance <GenNoBank1Mig.NoMig1Gen[1].d1DDRDQS1_3Ibuf> is unconnected or connected to loadless signal.WARNING:Xst:653 - Signal <dDram0RdFifoDataOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1RdFifoDataOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram0WrFifoFull> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram0AddrFifoFull> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram0RdDataValid> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram0PhyInitDone> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <Dram0ClkUser> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1WrFifoFull> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1AddrFifoFull> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1RdDataValid> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <dDram1PhyInitDone> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <Dram1ClkUser> is used but never assigned. This sourceless signal will be automatically connected to value GND. Found 1-bit tristate buffer for signal <d0DdrWE_n> created at line 486 Found 1-bit tristate buffer for signal <d0DdrODT<1>> created at line 487 Found 1-bit tristate buffer for signal <d0DdrODT<0>> created at line 487 Found 1-bit tristate buffer for signal <d0DdrCKE> created at line 488 Found 1-bit tristate buffer for signal <d0DdrRAS_n> created at line 489 Found 1-bit tristate buffer for signal <d0DdrCAS_n> created at line 490 Found 1-bit tristate buffer for signal <d0DdrAddr<12>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<11>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<10>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<9>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<8>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<7>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<6>> created at line 491

Found 1-bit tristate buffer for signal <d0DdrAddr<5>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<4>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<3>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<2>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<1>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrAddr<0>> created at line 491 Found 1-bit tristate buffer for signal <d0DdrBankAddr<2>> created at line 492 Found 1-bit tristate buffer for signal <d0DdrBankAddr<1>> created at line 492 Found 1-bit tristate buffer for signal <d0DdrBankAddr<0>> created at line 492 Found 1-bit tristate buffer for signal <d0DdrDM<3>> created at line 493 Found 1-bit tristate buffer for signal <d0DdrDM<2>> created at line 493 Found 1-bit tristate buffer for signal <d0DdrDM<1>> created at line 493 Found 1-bit tristate buffer for signal <d0DdrDM<0>> created at line 493 Found 1-bit tristate buffer for signal <d1DdrWE_n> created at line 641 Found 1-bit tristate buffer for signal <d1DdrODT<1>> created at line 642 Found 1-bit tristate buffer for signal <d1DdrODT<0>> created at line 642 Found 1-bit tristate buffer for signal <d1DdrCKE> created at line 643 Found 1-bit tristate buffer for signal <d1DdrRAS_n> created at line 644 Found 1-bit tristate buffer for signal <d1DdrCAS_n> created at line 645 Found 1-bit tristate buffer for signal <d1DdrAddr<12>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<11>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<10>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<9>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<8>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<7>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<6>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<5>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<4>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<3>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<2>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<1>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrAddr<0>> created at line 646 Found 1-bit tristate buffer for signal <d1DdrBankAddr<2>> created at line 647 Found 1-bit tristate buffer for signal <d1DdrBankAddr<1>> created at line 647 Found 1-bit tristate buffer for signal <d1DdrBankAddr<0>> created at line 647 Found 1-bit tristate buffer for signal <d1DdrDM<3>> created at line 648 Found 1-bit tristate buffer for signal <d1DdrDM<2>> created at line 648 Found 1-bit tristate buffer for signal <d1DdrDM<1>> created at line 648 Found 1-bit tristate buffer for signal <d1DdrDM<0>> created at line 648 Summary:

inferred 52 Tristate(s).Unit <Puma20DramMain> synthesized.

Synthesizing Unit <ChinchLvFpgaInterface>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaInterface.vhd".WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[15]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[15]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[15]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[15]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[14]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[14]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[14]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[14]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[13]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[13]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[13]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[13]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[12]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[12]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[12]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[12]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[11]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[11]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[11]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[11]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[10]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[10]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[10]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[10]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[9]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[9]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[9]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[9]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[8]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[8]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[8]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[8]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[7]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[7]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[7]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[7]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[6]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[6]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[6]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[6]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[5]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[5]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[5]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[5]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[4]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[4]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[4]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[4]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[3]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[3]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[3]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[3]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[2]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[2]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[2]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[2]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[15]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[15]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[15]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[14]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[14]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[14]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[13]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[13]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[13]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[12]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[12]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[12]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[11]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[11]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[11]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[10]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[10]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[10]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[9]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[9]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[9]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[8]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[8]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[8]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[7]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[7]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[7]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[6]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[6]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[6]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[5]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[5]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[5]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[4]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[4]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[4]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[3]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[3]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[3]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[1]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[1]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[1]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[0]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[0]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[0]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientInputStreamInterfaceFromFifo[0]_FifoDataOut> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientInputStreamInterfaceFromFifo[0]_FifoFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientInputStreamInterfaceFromFifo[0]_ByteLanePtr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bClientInputStreamInterfaceFromFifo[0]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientOutputStreamInterfaceFromFifo[0]_EmptyCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientOutputStreamInterfaceFromFifo[0]_HostReadableFullCount> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientOutputStreamInterfaceFromFifo[0]_StateInDefaultClkDomain> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[15]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[15]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[15]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[15]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[15]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[15]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[14]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[14]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[14]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[14]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[14]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[14]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[13]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[13]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[13]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[13]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[13]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[13]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[12]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[12]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[12]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[12]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[12]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[12]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[11]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[11]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[11]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[11]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[11]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[11]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[10]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[10]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[10]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[10]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[10]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[10]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[9]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[9]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[9]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[9]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[9]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[9]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[8]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[8]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[8]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[8]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[8]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[8]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[7]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[7]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[7]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[7]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[7]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[7]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[6]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[6]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[6]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[6]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[6]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[6]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[5]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[5]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[5]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[5]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[5]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[5]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[4]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[4]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[4]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[4]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[4]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[4]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[3]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[3]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[3]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[3]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[3]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[3]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[2]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[2]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[2]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[2]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[2]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo[2]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[15]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[15]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[15]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[15]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[15]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[14]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[14]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[14]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[14]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[14]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[13]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[13]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[13]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[13]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[13]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[12]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[12]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[12]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[12]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[12]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[11]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[11]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[11]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[11]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[11]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[10]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[10]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[10]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[10]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[10]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[9]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[9]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[9]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[9]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[9]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[8]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[8]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[8]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[8]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[8]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[7]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[7]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[7]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[7]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[7]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[6]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[6]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[6]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[6]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[6]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[5]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[5]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[5]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[5]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[5]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[4]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[4]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[4]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[4]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[4]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[3]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[3]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[3]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[3]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[3]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[1]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[1]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[1]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[1]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[1]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[0]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[0]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[0]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[0]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo[0]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientInputStreamInterfaceFromFifo[0]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientInputStreamInterfaceFromFifo[0]_FifoOverflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientInputStreamInterfaceFromFifo[0]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientInputStreamInterfaceFromFifo[0]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientInputStreamInterfaceFromFifo[0]_StopStreamWithFlushRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientInputStreamInterfaceFromFifo[0]_WritesDisabled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientOutputStreamInterfaceFromFifo[0]_ResetDone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bClientOutputStreamInterfaceFromFifo[0]_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientOutputStreamInterfaceFromFifo[0]_FifoUnderflow> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientOutputStreamInterfaceFromFifo[0]_StartStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientOutputStreamInterfaceFromFifo[0]_StopStreamRequest> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaInterface.vhd" line 898: Output port <sStatusPushAccGnt> of the instance <ChinchCommIfcArbiterBasex> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchLvFpgaInterface.vhd" line 898: Output port <sMsiAccGnt> of the instance <ChinchCommIfcArbiterBasex> is unconnected or connected to loadless signal.WARNING:Xst:653 - Signal <bClientInputStreamInterfaceToFifo[0]_BytesRead> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <bClientInputStreamInterfaceToFifo[0]_StreamState> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <bClientOutputStreamInterfaceToFifo[0]_WriteLengthInBytes> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <bClientOutputStreamInterfaceToFifo[0]_FifoData> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <bClientOutputStreamInterfaceToFifo[0]_NumWriteSpaces> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:653 - Signal <bClientOutputStreamInterfaceToFifo[0]_StreamState> is used but never assigned. This sourceless signal will be automatically connected to value GND.WARNING:Xst:2935 - Signal 'bClientInputStreamInterfaceToFifo[0]_DmaReset', unconnected in block 'ChinchLvFpgaInterface', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'bClientInputStreamInterfaceToFifo[0]_Pop', unconnected in block 'ChinchLvFpgaInterface', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'bClientInputStreamInterfaceToFifo[0]_UpdateByteLanePtr', unconnected in block 'ChinchLvFpgaInterface', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'bClientOutputStreamInterfaceToFifo[0]_DmaReset', unconnected in block 'ChinchLvFpgaInterface', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'bClientOutputStreamInterfaceToFifo[0]_FifoWrite', unconnected in block 'ChinchLvFpgaInterface', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'bClientOutputStreamInterfaceToFifo[0]_RsrvWriteSpaces', unconnected in block 'ChinchLvFpgaInterface', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'bClientOutputStreamInterfaceToFifo[0]_ReportDisabledToDiagram', unconnected in block 'ChinchLvFpgaInterface', is tied to its initial value (0). Summary:

no macro.Unit <ChinchLvFpgaInterface> synthesized.

Synthesizing Unit <ChinchRegisterAccess>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchRegisterAccess.vhd".

WARNING:Xst:647 - Input <bInputRx_ReadyForRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 2-bit register for signal <bReadCompleterState>. Found 28-bit register for signal <bAddressReg>. Found 8-bit register for signal <bLabelReg>. Found 32-bit register for signal <bReadDataReg>. Found 32-bit register for signal <bWriteDataReg>. Found 1-bit register for signal <bTimeoutOccurred>. Found 1-bit register for signal <bZeroLengthRead>. Found 4-bit register for signal <bResponseEndpoint>. Found 1-bit register for signal <bRegPortIn_Rd>. Found 1-bit register for signal <bRegPortIn_Wt>. Found 32-bit register for signal <bRegPortOutDel_Data>. Found 1-bit register for signal <bRegPortOutDel_DataValid>. Found 64-bit register for signal <bResponseHeader>. Found 32-bit register for signal <bReadCompleterData>. Found 1-bit register for signal <bReadCompleterZeroLength>. Found 11-bit register for signal <bTimeoutCounterReg>. Found 3-bit register for signal <bRegAccessState>. Found 1-bit register for signal <bRegPortOutDel_Ready>. Found finite state machine <FSM_15> for signal <bReadCompleterState>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 9 | | Inputs | 4 | | Outputs | 5 | | Clock | BusClk (rising_edge) | | Reset | bReset (positive) | | Reset type | synchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_16> for signal <bRegAccessState>. ----------------------------------------------------------------------- | States | 8 | | Transitions | 24 | | Inputs | 12 | | Outputs | 7 | | Clock | BusClk (rising_edge) | | Reset | bReset (positive) | | Reset type | synchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 11-bit adder for signal <bTimeoutCounterReg[10]_GND_3951_o_add_76_OUT> created at line 1241. Found 64-bit 3-to-1 multiplexer for signal <bInputTx_Data> created at line 646.

Found 1-bit 3-to-1 multiplexer for signal <bArbiterDoneStrobe> created at line 646. Found 10-bit comparator greater for signal <GND_3951_o_bOutputTx_Data[26]_LessThan_23_o> created at line 467 Summary:


Unit <ChinchRegisterAccess> synthesized.

Synthesizing Unit <ChinchDmaInput_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInput.vhd".WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo_FifoFullCount<31:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInput.vhd" line 332: Output port <bPeerAddress> of the instance <ChinchInterfaceDmaRegistersx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInput.vhd" line 332: Output port <bSatcrUpdatesEnabled> of the instance <ChinchInterfaceDmaRegistersx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInput.vhd" line 380: Output port <bDisable> of the instance <ChinchDmaSourceStreamStateControllerx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <ChinchDmaInput_1> synthesized.

Synthesizing Unit <ChinchDmaInputController_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputController.vhd".WARNING:Xst:647 - Input <bMaxPktSize<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputRx_ReadyForRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 8-bit register for signal <bDataWordCounter>. Found 1-bit register for signal <bHeaderWord>. Found 1-bit register for signal <bLastWord>. Found 1-bit register for signal <bReady>. Found 1-bit register for signal <bSatcrWriteStrobe>. Found 1-bit register for signal <bStateEntry>. Found 64-bit register for signal <bDataOut>. Found 1-bit register for signal <bLastPop>. Found 1-bit register for signal <bResetFifo>. Found 3-bit register for signal <bLastBytesRead>. Found 3-bit register for signal <bHeaderByteLane>. Found 10-bit register for signal <bPacketLength>. Found 1-bit register for signal <bArbiterNormalReq>. Found 1-bit register for signal <bArbiterEmergencyReq>. Found 10-bit register for signal <HandleArbiterRequests.bFifoFullCountDelay>.

Found 10-bit register for signal <HandleArbiterRequests.bFifoFullCountDelay2>. Found 1-bit register for signal <HandleArbiterRequests.bPopDelay>. Found 1-bit register for signal <HandleArbiterRequests.bPopDelay2>. Found 8-bit register for signal <HandleArbiterRequests.bEvictionCounter>. Found 2-bit register for signal <FifoController.bFifoState>. Found 1-bit register for signal <FifoController.bPopDelay>. Found 64-bit register for signal <FifoController.bDff0>. Found 64-bit register for signal <FifoController.bDff1>. Found 4-bit register for signal <bDmaInputState>. Found finite state machine <FSM_17> for signal <FifoController.bFifoState>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 9 | | Inputs | 2 | | Outputs | 2 | | Clock | BusClk (rising_edge) | | Reset | bReset (positive) | | Reset type | synchronous | | Reset State | directfifo | | Power Up State | directfifo | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_18> for signal <bDmaInputState>. ----------------------------------------------------------------------- | States | 9 | | Transitions | 25 | | Inputs | 9 | | Outputs | 16 | | Clock | BusClk (rising_edge) | | Reset | bReset (positive) | | Reset type | synchronous | | Reset State | disabled | | Power Up State | disablerequest | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 4-bit adder for signal <GND_3954_o_GND_3954_o_add_21_OUT> created at line 691. Found 3-bit adder for signal <GND_3954_o_GND_3954_o_sub_27_OUT<2:0>> created at line 710. Found 10-bit adder for signal <n0310> created at line 727. Found 10-bit adder for signal <n0237> created at line 1241. Found 8-bit adder for signal <HandleArbiterRequests.bEvictionCounter[7]_GND_3954_o_add_88_OUT> created at line 1241. Found 8-bit subtractor for signal <GND_3954_o_GND_3954_o_sub_40_OUT<7:0>> created at line 1308. Found 3-bit subtractor for signal <GND_3954_o_GND_3954_o_sub_25_OUT<2:0>> created at line 695. Found 1-bit 3-to-1 multiplexer for signal <FifoController.bDff0Load> created at line 1229. Found 1-bit 3-to-1 multiplexer for signal <FifoController.bDff0SelFifo> created at line 1229. Found 4-bit comparator greater for signal <GND_3954_o_GND_3954_o_LessThan_23_o> created at line 691

Found 8-bit comparator greater for signal <GND_3954_o_bDataWordCounter[7]_LessThan_33_o> created at line 755 Found 8-bit comparator greater for signal <GND_3954_o_bDataWordCounter[7]_LessThan_38_o> created at line 798 Found 10-bit comparator greater for signal <HandleArbiterRequests.bFifoFullCountDelay2[9]_HandleArbiterRequests.bFifoFullCountDelay[9]_LessThan_83_o> created at line 1051 Found 10-bit comparator equal for signal <HandleArbiterRequests.bFifoFullCountDelay[9]_HandleArbiterRequests.bFifoFullCountDelay2[9]_equal_84_o> created at line 1052 Found 10-bit comparator lessequal for signal <n0153> created at line 1062 Found 8-bit comparator greater for signal <HandleArbiterRequests.bEvictionTimeoutFlag_INV_1016_o> created at line 1068 Summary:


Unit <ChinchDmaInputController_1> synthesized.

Synthesizing Unit <ChinchInterfaceDmaRegisters_1>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchInterfaceDmaRegisters.vhd". Found 1-bit register for signal <InterruptRegister.bUnderflowStatus>. Found 1-bit register for signal <InterruptRegister.bStartStreamStatus>. Found 1-bit register for signal <InterruptRegister.bStopStreamStatus>. Found 1-bit register for signal <InterruptRegister.bFlushingStatus>. Found 1-bit register for signal <InterruptRegister.bStreamErrorStatus>. Found 1-bit register for signal <InterruptRegister.bOverflowMask>. Found 1-bit register for signal <InterruptRegister.bUnderflowMask>. Found 1-bit register for signal <InterruptRegister.bStartStreamMask>. Found 1-bit register for signal <InterruptRegister.bStopStreamMask>. Found 1-bit register for signal <InterruptRegister.bFlushingMask>. Found 1-bit register for signal <InterruptRegister.bStreamErrorMask>. Found 2-bit register for signal <n0304>. Found 1-bit register for signal <bDmaResetReg>. Found 1-bit register for signal <ControlStatusRegister.bLinkedReg>. Found 1-bit register for signal <ControlStatusRegister.bHostEnableReg>. Found 1-bit register for signal <ControlStatusRegister.bHostDisableReg>. Found 1-bit register for signal <ControlStatusRegister.bHostFlushReg>. Found 1-bit register for signal <bOverflowStatusReg>. Found 1-bit register for signal <bUnderflowStatusReg>. Found 1-bit register for signal <bFlushingStatus>. Found 1-bit register for signal <bFlushingFailedStatus>. Found 1-bit register for signal <bStreamErrorStatusReg>. Found 1-bit register for signal <bEnableAlignment>. Found 16-bit register for signal <bNextBoundary>. Found 16-bit register for signal <bMaxPayloadSize>. Found 1-bit register for signal <SatcrRegister.bSatcrRegWrite>. Found 32-bit register for signal <bSatcr>. Found 32-bit register for signal <SatcrRegister.bSatcrAddAmt>. Found 10-bit register for signal <bMaxPktSize>.

Found 10-bit register for signal <SatcrRegister.bBytesToAlignment>. Found 1-bit register for signal <SatcrRegister.bDisabledLast>. Found 1-bit register for signal <bRegPortOut_DataValid>. Found 32-bit register for signal <bRegPortOut_Data>. Found 1-bit register for signal <InterruptRegister.bOverflowStatus>. Found 32-bit adder for signal <bSatcr[31]_SatcrRegister.bSatcrAddAmt[31]_add_16_OUT> created at line 1113. Found 32-bit subtractor for signal <GND_3957_o_GND_3957_o_sub_19_OUT<31:0>> created at line 1112. Found 10-bit subtractor for signal <GND_3957_o_GND_3957_o_sub_24_OUT<9:0>> created at line 1148. Found 32-bit comparator greater for signal <GND_3957_o_SatcrRegister.bSatcrNx[31]_LessThan_22_o> created at line 1120 Summary:


Unit <ChinchInterfaceDmaRegisters_1> synthesized.

Synthesizing Unit <ChinchDmaSourceStreamStateController>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaSourceStreamStateController.vhd". Found 1-bit register for signal <bDisableController>. Found 1-bit register for signal <bEnableReg>. Found 1-bit register for signal <bEnableRequestReg>. Found 1-bit register for signal <bFlushReg>. Found 1-bit register for signal <bFlushIrqStrobe>. Found 1-bit register for signal <bSatcrWriteReceived>. Found 1-bit register for signal <bOutstandingEnableIrq>. Found 2-bit register for signal <bState>. Found 2-bit register for signal <bStreamState>. Found finite state machine <FSM_19> for signal <bStreamState>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 18 | | Inputs | 7 | | Outputs | 4 | | Clock | BusClk (rising_edge) | | Reset | aReset (positive) | | Reset type | asynchronous | | Reset State | unlinked | | Power Up State | unlinked | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 2-bit 4-to-1 multiplexer for signal <bStreamStateNx> created at line 269. Found 1-bit 4-to-1 multiplexer for signal <bSetEnableIrq> created at line 269. Found 1-bit 3-to-1 multiplexer for signal <bResetFirstSatcrWriteTracker> created at line 269. Summary:


inferred 1 Finite State Machine(s).Unit <ChinchDmaSourceStreamStateController> synthesized.

Synthesizing Unit <ChinchDmaInput_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInput.vhd".WARNING:Xst:647 - Input <bInputStreamInterfaceFromFifo_FifoFullCount<31:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInput.vhd" line 332: Output port <bPeerAddress> of the instance <ChinchInterfaceDmaRegistersx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInput.vhd" line 332: Output port <bSatcrUpdatesEnabled> of the instance <ChinchInterfaceDmaRegistersx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInput.vhd" line 380: Output port <bDisable> of the instance <ChinchDmaSourceStreamStateControllerx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <ChinchDmaInput_2> synthesized.

Synthesizing Unit <ChinchDmaInputController_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaInputController.vhd".WARNING:Xst:647 - Input <bMaxPktSize<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputRx_ReadyForRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 8-bit register for signal <bDataWordCounter>. Found 1-bit register for signal <bHeaderWord>. Found 1-bit register for signal <bLastWord>. Found 1-bit register for signal <bReady>. Found 1-bit register for signal <bSatcrWriteStrobe>. Found 1-bit register for signal <bStateEntry>. Found 64-bit register for signal <bDataOut>. Found 1-bit register for signal <bLastPop>. Found 1-bit register for signal <bResetFifo>. Found 3-bit register for signal <bLastBytesRead>. Found 3-bit register for signal <bHeaderByteLane>. Found 10-bit register for signal <bPacketLength>. Found 1-bit register for signal <bArbiterNormalReq>. Found 1-bit register for signal <bArbiterEmergencyReq>. Found 10-bit register for signal <HandleArbiterRequests.bFifoFullCountDelay>. Found 10-bit register for signal <HandleArbiterRequests.bFifoFullCountDelay2>. Found 1-bit register for signal <HandleArbiterRequests.bPopDelay>. Found 1-bit register for signal <HandleArbiterRequests.bPopDelay2>. Found 8-bit register for signal <HandleArbiterRequests.bEvictionCounter>. Found 2-bit register for signal <FifoController.bFifoState>. Found 1-bit register for signal <FifoController.bPopDelay>. Found 64-bit register for signal <FifoController.bDff0>. Found 64-bit register for signal <FifoController.bDff1>.

Found 4-bit register for signal <bDmaInputState>. Found finite state machine <FSM_20> for signal <FifoController.bFifoState>. ----------------------------------------------------------------------- | States | 3 | | Transitions | 9 | | Inputs | 2 | | Outputs | 2 | | Clock | BusClk (rising_edge) | | Reset | bReset (positive) | | Reset type | synchronous | | Reset State | directfifo | | Power Up State | directfifo | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine <FSM_21> for signal <bDmaInputState>. ----------------------------------------------------------------------- | States | 9 | | Transitions | 25 | | Inputs | 9 | | Outputs | 17 | | Clock | BusClk (rising_edge) | | Reset | bReset (positive) | | Reset type | synchronous | | Reset State | disabled | | Power Up State | disablerequest | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 4-bit adder for signal <GND_3966_o_GND_3966_o_add_21_OUT> created at line 691. Found 3-bit adder for signal <GND_3966_o_GND_3966_o_sub_27_OUT<2:0>> created at line 710. Found 10-bit adder for signal <n0310> created at line 727. Found 10-bit adder for signal <n0237> created at line 1241. Found 8-bit adder for signal <HandleArbiterRequests.bEvictionCounter[7]_GND_3966_o_add_88_OUT> created at line 1241. Found 8-bit subtractor for signal <GND_3966_o_GND_3966_o_sub_40_OUT<7:0>> created at line 1308. Found 3-bit subtractor for signal <GND_3966_o_GND_3966_o_sub_25_OUT<2:0>> created at line 695. Found 1-bit 3-to-1 multiplexer for signal <FifoController.bDff0Load> created at line 1229. Found 1-bit 3-to-1 multiplexer for signal <FifoController.bDff0SelFifo> created at line 1229. Found 4-bit comparator greater for signal <GND_3966_o_GND_3966_o_LessThan_23_o> created at line 691 Found 8-bit comparator greater for signal <GND_3966_o_bDataWordCounter[7]_LessThan_33_o> created at line 755 Found 8-bit comparator greater for signal <GND_3966_o_bDataWordCounter[7]_LessThan_38_o> created at line 798 Found 10-bit comparator greater for signal <HandleArbiterRequests.bFifoFullCountDelay2[9]_HandleArbiterRequests.bFifoFullCountDelay[9]_LessThan_83_o> created at line 1051

Found 10-bit comparator equal for signal <HandleArbiterRequests.bFifoFullCountDelay[9]_HandleArbiterRequests.bFifoFullCountDelay2[9]_equal_84_o> created at line 1052 Found 10-bit comparator lessequal for signal <n0153> created at line 1062 Found 8-bit comparator greater for signal <HandleArbiterRequests.bEvictionTimeoutFlag_INV_1088_o> created at line 1068 Summary:


Unit <ChinchDmaInputController_2> synthesized.

Synthesizing Unit <ChinchInterfaceDmaRegisters_2>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchInterfaceDmaRegisters.vhd". Found 1-bit register for signal <InterruptRegister.bUnderflowStatus>. Found 1-bit register for signal <InterruptRegister.bStartStreamStatus>. Found 1-bit register for signal <InterruptRegister.bStopStreamStatus>. Found 1-bit register for signal <InterruptRegister.bFlushingStatus>. Found 1-bit register for signal <InterruptRegister.bStreamErrorStatus>. Found 1-bit register for signal <InterruptRegister.bOverflowMask>. Found 1-bit register for signal <InterruptRegister.bUnderflowMask>. Found 1-bit register for signal <InterruptRegister.bStartStreamMask>. Found 1-bit register for signal <InterruptRegister.bStopStreamMask>. Found 1-bit register for signal <InterruptRegister.bFlushingMask>. Found 1-bit register for signal <InterruptRegister.bStreamErrorMask>. Found 2-bit register for signal <n0304>. Found 1-bit register for signal <bDmaResetReg>. Found 1-bit register for signal <ControlStatusRegister.bLinkedReg>. Found 1-bit register for signal <ControlStatusRegister.bHostEnableReg>. Found 1-bit register for signal <ControlStatusRegister.bHostDisableReg>. Found 1-bit register for signal <ControlStatusRegister.bHostFlushReg>. Found 1-bit register for signal <bOverflowStatusReg>. Found 1-bit register for signal <bUnderflowStatusReg>. Found 1-bit register for signal <bFlushingStatus>. Found 1-bit register for signal <bFlushingFailedStatus>. Found 1-bit register for signal <bStreamErrorStatusReg>. Found 1-bit register for signal <bEnableAlignment>. Found 16-bit register for signal <bNextBoundary>. Found 16-bit register for signal <bMaxPayloadSize>. Found 1-bit register for signal <SatcrRegister.bSatcrRegWrite>. Found 32-bit register for signal <bSatcr>. Found 32-bit register for signal <SatcrRegister.bSatcrAddAmt>. Found 10-bit register for signal <bMaxPktSize>. Found 10-bit register for signal <SatcrRegister.bBytesToAlignment>. Found 1-bit register for signal <SatcrRegister.bDisabledLast>. Found 1-bit register for signal <bRegPortOut_DataValid>. Found 32-bit register for signal <bRegPortOut_Data>. Found 1-bit register for signal <InterruptRegister.bOverflowStatus>. Found 32-bit adder for signal <bSatcr[31]_SatcrRegister.bSatcrAddAmt[31]_add_16_OUT> created at line 1113.

Found 32-bit subtractor for signal <GND_3968_o_GND_3968_o_sub_19_OUT<31:0>> created at line 1112. Found 10-bit subtractor for signal <GND_3968_o_GND_3968_o_sub_24_OUT<9:0>> created at line 1148. Found 32-bit comparator greater for signal <GND_3968_o_SatcrRegister.bSatcrNx[31]_LessThan_22_o> created at line 1120 Summary:


Unit <ChinchInterfaceDmaRegisters_2> synthesized.

Synthesizing Unit <ChinchDmaOutput>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutput.vhd".WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo_EmptyCount<31:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bOutputStreamInterfaceFromFifo_RsrvdSpacesFilled> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutput.vhd" line 345: Output port <bPeerAddress> of the instance <ChinchInterfaceDmaRegistersx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutput.vhd" line 345: Output port <bPeerEndpoint> of the instance <ChinchInterfaceDmaRegistersx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutput.vhd" line 345: Output port <bHostFlush> of the instance <ChinchInterfaceDmaRegistersx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutput.vhd" line 345: Output port <bSatcrWriteEvent> of the instance <ChinchInterfaceDmaRegistersx> is unconnected or connected to loadless signal.INFO:Xst:3210 - "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutput.vhd" line 345: Output port <bSatcrUpdatesEnabled> of the instance <ChinchInterfaceDmaRegistersx> is unconnected or connected to loadless signal. Summary:

no macro.Unit <ChinchDmaOutput> synthesized.

Synthesizing Unit <ChinchDmaOutputController>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaOutputController.vhd". Found 3-bit register for signal <bDmaOutputRequestState>. Found 64-bit register for signal <bPacketData>. Found 1-bit register for signal <bSatcrWriteStrobe>. Found 10-bit register for signal <bReqWriteSpacesLoc>. Found 1-bit register for signal <bLastWord>. Found 1-bit register for signal <bReady>. Found 1-bit register for signal <bReadRequested>. Found 1-bit register for signal <bArbiterNormalReq>. Found 1-bit register for signal <bArbiterEmergencyReq>. Found 10-bit register for signal <OutstandingReadCounter.bReadCount>.

Found 3-bit register for signal <bByteLane>. Found finite state machine <FSM_22> for signal <bDmaOutputRequestState>. ----------------------------------------------------------------------- | States | 5 | | Transitions | 17 | | Inputs | 7 | | Outputs | 4 | | Clock | BusClk (rising_edge) | | Reset | bReset (positive) | | Reset type | synchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 10-bit adder for signal <n0103> created at line 414. Found 10-bit adder for signal <OutstandingReadCounter.bReadCount[9]_GND_3975_o_add_44_OUT> created at line 1241. Found 10-bit subtractor for signal <GND_3975_o_GND_3975_o_sub_46_OUT<9:0>> created at line 1308. Found 1-bit 4-to-1 multiplexer for signal <bArbiterDone> created at line 343. Found 1-bit 4-to-1 multiplexer for signal <bLastWordNx> created at line 343. Found 10-bit comparator lessequal for signal <n0067> created at line 606 Summary:


Unit <ChinchDmaOutputController> synthesized.

Synthesizing Unit <OutStrmOutputHandler>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\OutStrmOutputHandler.vhd". Found 64-bit register for signal <bFifoData>. Found 1-bit register for signal <bFifoWrite>. Found 4-bit register for signal <bNextWriteLength>. Found 4-bit register for signal <bWriteLengthInBytesLoc>. Found 1-bit register for signal <bFirstData>. Found 1-bit register for signal <bReadResponseReceived>. Found 1-bit register for signal <bStreamError>. Found 3-bit register for signal <bStartingByteLane>. Found 1-bit register for signal <bDmaOutputDataState>. Found 10-bit adder for signal <n0091> created at line 315. Found 10-bit subtractor for signal <GND_3976_o_GND_3976_o_sub_15_OUT<9:0>> created at line 1314. Found 4-bit subtractor for signal <GND_3976_o_GND_3976_o_sub_17_OUT<3:0>> created at line 308. Found 10-bit comparator greater for signal <bOutputTx_Data[26]_GND_3976_o_LessThan_16_o> created at line 300 Summary:

inferred 3 Adder/Subtractor(s).inferred 80 D-type flip-flop(s).

inferred 1 Comparator(s).inferred 17 Multiplexer(s).

Unit <OutStrmOutputHandler> synthesized.

Synthesizing Unit <ChinchInterfaceDmaRegisters_3>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchInterfaceDmaRegisters.vhd". Found 1-bit register for signal <InterruptRegister.bUnderflowStatus>. Found 1-bit register for signal <InterruptRegister.bStartStreamStatus>. Found 1-bit register for signal <InterruptRegister.bStopStreamStatus>. Found 1-bit register for signal <InterruptRegister.bFlushingStatus>. Found 1-bit register for signal <InterruptRegister.bStreamErrorStatus>. Found 1-bit register for signal <InterruptRegister.bOverflowMask>. Found 1-bit register for signal <InterruptRegister.bUnderflowMask>. Found 1-bit register for signal <InterruptRegister.bStartStreamMask>. Found 1-bit register for signal <InterruptRegister.bStopStreamMask>. Found 1-bit register for signal <InterruptRegister.bFlushingMask>. Found 1-bit register for signal <InterruptRegister.bStreamErrorMask>. Found 2-bit register for signal <n0304>. Found 1-bit register for signal <bDmaResetReg>. Found 1-bit register for signal <ControlStatusRegister.bLinkedReg>. Found 1-bit register for signal <ControlStatusRegister.bHostEnableReg>. Found 1-bit register for signal <ControlStatusRegister.bHostDisableReg>. Found 1-bit register for signal <ControlStatusRegister.bHostFlushReg>. Found 1-bit register for signal <bOverflowStatusReg>. Found 1-bit register for signal <bUnderflowStatusReg>. Found 1-bit register for signal <bFlushingStatus>. Found 1-bit register for signal <bFlushingFailedStatus>. Found 1-bit register for signal <bStreamErrorStatusReg>. Found 1-bit register for signal <bEnableAlignment>. Found 16-bit register for signal <bNextBoundary>. Found 16-bit register for signal <bMaxPayloadSize>. Found 1-bit register for signal <SatcrRegister.bSatcrRegWrite>. Found 32-bit register for signal <bSatcr>. Found 32-bit register for signal <SatcrRegister.bSatcrAddAmt>. Found 10-bit register for signal <bMaxPktSize>. Found 10-bit register for signal <SatcrRegister.bBytesToAlignment>. Found 1-bit register for signal <SatcrRegister.bDisabledLast>. Found 1-bit register for signal <bRegPortOut_DataValid>. Found 32-bit register for signal <bRegPortOut_Data>. Found 1-bit register for signal <InterruptRegister.bOverflowStatus>. Found 32-bit adder for signal <bSatcr[31]_SatcrRegister.bSatcrAddAmt[31]_add_16_OUT> created at line 1113. Found 32-bit subtractor for signal <GND_3977_o_GND_3977_o_sub_19_OUT<31:0>> created at line 1112. Found 10-bit subtractor for signal <GND_3977_o_GND_3977_o_sub_24_OUT<9:0>> created at line 1148. Found 32-bit comparator greater for signal <GND_3977_o_SatcrRegister.bSatcrNx[31]_LessThan_22_o> created at line 1120 Summary:

inferred 2 Adder/Subtractor(s).inferred 171 D-type flip-flop(s).inferred 1 Comparator(s).

inferred 36 Multiplexer(s).Unit <ChinchInterfaceDmaRegisters_3> synthesized.

Synthesizing Unit <ChinchDmaSinkStreamStateController>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchDmaSinkStreamStateController.vhd". Found 1-bit register for signal <bEnableReg>. Found 1-bit register for signal <bStateEnableReg>. Found 1-bit register for signal <bWaitOnFifoReset>. Found 1-bit register for signal <bOutstandingEnableIrq>. Found 2-bit register for signal <bStreamState>. Found 1-bit register for signal <bDisableLoc>.INFO:Xst:1799 - State flushing is never reached in FSM <bStreamState>. Found finite state machine <FSM_23> for signal <bStreamState>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 11 | | Inputs | 5 | | Outputs | 5 | | Clock | BusClk (rising_edge) | | Reset | bReset (positive) | | Reset type | synchronous | | Reset State | unlinked | | Power Up State | unlinked | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit 3-to-1 multiplexer for signal <bSetEnableIrq> created at line 214. Summary:


Unit <ChinchDmaSinkStreamStateController> synthesized.

Synthesizing Unit <ChinchIrqInterface>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchIrqInterface.vhd".WARNING:Xst:647 - Input <bLvFpgaIrq[0][32]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][31]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][30]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][29]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][28]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bLvFpgaIrq[0][27]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][26]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][25]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][24]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][23]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][22]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][21]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][20]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][19]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][18]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][17]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][16]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][15]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][14]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][13]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][12]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][11]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bLvFpgaIrq[0][10]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][9]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][8]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][7]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][6]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][5]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][4]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][3]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][2]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][1]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bLvFpgaIrq[0][0]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[15]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[14]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[13]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[12]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[11]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[10]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

WARNING:Xst:647 - Input <bDmaIrq[9]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[8]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[7]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[6]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[5]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[4]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[3]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[2]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[1]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bDmaIrq[0]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bClientIrq[0]_Clear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal <bIrq>. Summary:


Unit <ChinchIrqInterface> synthesized.

Synthesizing Unit <IoPort2LvFpga>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\IoPort2LvFpga.vhd".WARNING:Xst:647 - Input <bIoPort2OutputTx_RFR_Delay> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:647 - Input <bInputTx_HeaderWord> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal <bLastWord>. Summary:

inferred 1 D-type flip-flop(s).Unit <IoPort2LvFpga> synthesized.

Synthesizing Unit <PacketSink>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\PacketSink.vhd".WARNING:Xst:647 - Input <bOutputTx_Data<63:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Found 1-bit register for signal <bOutputRx_Accept>. Summary:

inferred 1 D-type flip-flop(s).Unit <PacketSink> synthesized.

Synthesizing Unit <CHInChCommIfcArbiterBase>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ChinchCommIfcArbiterBase.vhd".WARNING:Xst:2935 - Signal 'sOutStrmsArbHighDone', unconnected in block 'CHInChCommIfcArbiterBase', is tied to its initial value (0).WARNING:Xst:2935 - Signal 'sOutStrmsArbNormDone', unconnected in block 'CHInChCommIfcArbiterBase', is tied to its initial value (0). Found 1-bit register for signal <SmLogicAndFFs.sStatusPushAccGntLoc>. Found 1-bit register for signal <SmLogicAndFFs.sMsiAccGntLoc>. Found 3-bit register for signal <SmLogicAndFFs.sMainArbSt>. Found 1-bit register for signal <SmLogicAndFFs.sLastAccessOutput>. Found 1-bit register for signal <SmLogicAndFFs.sMemReplyAccGntLoc>. Found finite state machine <FSM_24> for signal <SmLogicAndFFs.sMainArbSt>. ----------------------------------------------------------------------- | States | 8 | | Transitions | 101 | | Inputs | 16 | | Outputs | 8 | | Clock | SysClk (rising_edge) | | Reset | sReset (positive) | | Reset type | synchronous | | Reset State | idle | | Power Up State | idle | | Encoding | auto | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit 7-to-1 multiplexer for signal <SmLogicAndFFs.sNextMemReplyAccGntLoc> created at line 383. Found 1-bit 7-to-1 multiplexer for signal <SmLogicAndFFs.sNextStatusPushAccGntLoc> created at line 383. Found 1-bit 7-to-1 multiplexer for signal <SmLogicAndFFs.sNextMsiAccGntLoc> created at line 383. Summary:


Unit <CHInChCommIfcArbiterBase> synthesized.

Synthesizing Unit <StrmArbiter>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\StrmArbiter.vhd". Found 1-bit register for signal <sAccGntLocVal>. Found 1-bit register for signal <sScanningOrder<0>>. Found 1-bit register for signal <sGrantValid>. Found 1-bit register for signal <sScanningOrder<1>>.

Found 1-bit register for signal <sStrmArbiterState>. Found 2-bit register for signal <sAccGntLoc>. Found 3-bit subtractor for signal <n0048> created at line 112. Found 3-bit subtractor for signal <n0050> created at line 112. Found 2-bit adder for signal <n0054> created at line 114. Found 1 bit to 2 bit decoder compact to one-hot for signal <sSubArbiterSelector[0][0]_Decoder_3_OUT> created at line 375 Found 2-bit comparator lessequal for signal <n0029> created at line 111 Found 2-bit comparator lessequal for signal <n0034> created at line 111 Summary:

inferred 3 Adder/Subtractor(s).inferred 7 D-type flip-flop(s).inferred 2 Comparator(s).inferred 15 Multiplexer(s).inferred 1 Decoder(s).

Unit <StrmArbiter> synthesized.

Synthesizing Unit <ClockGenXilinxV5>. Related source file is "C:\NIFPGA\jobs\vcnPe3C_D7RFefX\ClockGenXilinxV5.vhd".WARNING:Xst:647 - Input <bClockGenOut_UpdateConfiguration> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.WARNING:Xst:2935 - Signal 'bLclClockGenDebug<1>', unconnected in block 'ClockGenXilinxV5', is tied to its initial value (00000000).WARNING:Xst:2935 - Signal 'bLclClockGenDebug<0>', unconnected in block 'ClockGenXilinxV5', is tied to its initial value (00000000). Found 1-bit register for signal <bTxPllReset>. Found 1-bit register for signal <TxDcm.bTxClockMayBeLocked_ms>. Found 1-bit register for signal <bTxClockMayBeLocked>. Found 1-bit register for signal <bTxClockLocked>. Found 14-bit register for signal <TxDcm.bTxLockedFilterCount>. Found 26-bit register for signal <RxDcm.bRxUnResetClockCounter>. Found 1-bit register for signal <bRxPllReset>. Found 1-bit register for signal <bDlyCtrlRdy_ms>. Found 1-bit register for signal <bDlyCtrlRdy>. Found 1-bit register for signal <RxDcm.bRxClockMayBeLocked_ms>. Found 1-bit register for signal <bRxClockMayBeLocked>. Found 1-bit register for signal <bRxClockLocked>. Found 13-bit register for signal <RxDcm.bRxLockedFilterCount>. Found 25-bit register for signal <TxDcm.bTxUnResetClockCounter>. Found 25-bit adder for signal <TxDcm.bTxUnResetClockCounter[24]_GND_4034_o_add_3_OUT> created at line 152. Found 14-bit adder for signal <TxDcm.bTxLockedFilterCount[13]_GND_4034_o_add_8_OUT> created at line 235. Found 26-bit adder for signal <RxDcm.bRxUnResetClockCounter[25]_GND_4034_o_add_13_OUT> created at line 282. Found 13-bit adder for signal <RxDcm.bRxLockedFilterCount[12]_GND_4034_o_add_18_OUT> created at line 384. Summary:

inferred 4 Adder/Subtractor(s).inferred 88 D-type flip-flop(s).

Unit <ClockGenXilinxV5> synthesized.

=========================================================================HDL Synthesis Report

Macro Statistics# RAMs : 15 4x2-bit single-port Read Only RAM : 13 8x4-bit single-port Read Only RAM : 2# Adders/Subtractors : 95 10-bit adder : 11 10-bit addsub : 1 10-bit subtractor : 13 11-bit adder : 3 13-bit adder : 1 14-bit adder : 1 14-bit subtractor : 1 17-bit adder : 4 18-bit subtractor : 1 2-bit adder : 3 2-bit addsub : 1 2-bit subtractor : 2 25-bit adder : 1 26-bit adder : 1 3-bit adder : 7 3-bit addsub : 3 3-bit subtractor : 9 32-bit adder : 1 32-bit addsub : 3 32-bit subtractor : 8 4-bit adder : 3 4-bit subtractor : 1 5-bit adder : 1 5-bit subtractor : 2 6-bit subtractor : 1 7-bit subtractor : 3 8-bit adder : 3 8-bit subtractor : 6# Registers : 1338 1-bit register : 1094 10-bit register : 36 11-bit register : 3 12-bit register : 3 13-bit register : 2 14-bit register : 2 16-bit register : 52 2-bit register : 53 25-bit register : 1 26-bit register : 1 28-bit register : 1 3-bit register : 18 32-bit register : 28 33-bit register : 6

4-bit register : 3 5-bit register : 2 6-bit register : 1 64-bit register : 13 7-bit register : 3 8-bit register : 15 96-bit register : 1# Comparators : 63 10-bit comparator equal : 5 10-bit comparator greater : 7 10-bit comparator lessequal : 3 11-bit comparator lessequal : 1 16-bit comparator not equal : 2 17-bit comparator greater : 2 2-bit comparator lessequal : 5 3-bit comparator greater : 4 3-bit comparator lessequal : 15 32-bit comparator greater : 11 4-bit comparator greater : 2 8-bit comparator greater : 6# Multiplexers : 1059 1-bit 2-to-1 multiplexer : 747 1-bit 3-to-1 multiplexer : 18 1-bit 4-to-1 multiplexer : 4 1-bit 5-to-1 multiplexer : 2 1-bit 7-to-1 multiplexer : 3 10-bit 2-to-1 multiplexer : 38 11-bit 2-to-1 multiplexer : 4 12-bit 2-to-1 multiplexer : 1 14-bit 2-to-1 multiplexer : 1 16-bit 2-to-1 multiplexer : 32 16-bit 6-to-1 multiplexer : 1 2-bit 2-to-1 multiplexer : 33 2-bit 4-to-1 multiplexer : 2 3-bit 2-to-1 multiplexer : 40 32-bit 2-to-1 multiplexer : 57 4-bit 2-to-1 multiplexer : 6 5-bit 2-to-1 multiplexer : 4 6-bit 2-to-1 multiplexer : 4 64-bit 2-to-1 multiplexer : 16 64-bit 3-to-1 multiplexer : 1 7-bit 2-to-1 multiplexer : 5 8-bit 2-to-1 multiplexer : 38 8-bit 5-to-1 multiplexer : 1 96-bit 2-to-1 multiplexer : 1# Decoders : 3 1-of-2 decoder : 2 1-of-32 decoder : 1# Tristates : 103 1-bit tristate buffer : 103# FSMs : 36# Xors : 158

1-bit xor2 : 158

=========================================================================INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================* Advanced HDL Synthesis *=========================================================================

Reading core <IoPort2Wrapper.ngc>.Reading core <PumaFixedLogic.ngc>.Reading core <Puma20IoPort2Glue.ngc>.Reading core <BuiltinFIFOCoreFPGAwFIFOn0.ngc>.Reading core <BuiltinFIFOCoreFPGAwFIFOn1.ngc>.Loading core <IoPort2Wrapper> for timing and area information for instance <IoPort2Wrapperx>.Loading core <PumaFixedLogic> for timing and area information for instance <PumaFixedLogicx>.Loading core <Puma20IoPort2Glue> for timing and area information for instance <Puma20IoPort2Gluex>.Loading core <BuiltinFIFOCoreFPGAwFIFOn0> for timing and area information for instance <BuiltinFifoIP>.Loading core <BuiltinFIFOCoreFPGAwFIFOn1> for timing and area information for instance <BuiltinFifoIP>.WARNING:Xst:1290 - Hierarchical block <NiFpgaFifoCountControlx> is unconnected in block <DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <StreamStateBlock.ViClkStreamStateEnableChain> is unconnected in block <DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <StreamStateBlock.DefaultClkStreamStateEnableChain> is unconnected in block <DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <StreamStateBlock.StateHolderForViClkDomain> is unconnected in block <DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <NiFpgaFifoCountControlx> is unconnected in block <DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <StreamStateBlock.ViClkStreamStateEnableChain> is unconnected in block <DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <StreamStateBlock.DefaultClkStreamStateEnableChain> is unconnected in block <DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <StreamStateBlock.StateHolderForViClkDomain> is unconnected in block <DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <NiFpgaFifoCountControlx> is unconnected in block <DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex>. It will be removed from the design.

WARNING:Xst:1290 - Hierarchical block <StreamStateBlock.ViClkStreamStateEnableChain> is unconnected in block <DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <StreamStateBlock.DefaultClkStreamStateEnableChain> is unconnected in block <DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <StreamStateBlock.ViClkStateHolder> is unconnected in block <DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <n_NiFpgaAG_00000029_CaseStructureFrame_0001_Diagram> is unconnected in block <n_Boucle_cadencE9e_8065_Diagram>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <n_N9Cud_d_apost_entrE9e_4562_Diagram> is unconnected in block <n_Boucle_cadencE9e_4094_Diagram>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <n_NiFpgaAG_0000009c_CaseStructureFrame_0000_Diagram> is unconnected in block <n_Boucle_cadencE9e_14482_Diagram>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <n_InvisibleResholder> is unconnected in block <theVI>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <n_N9Cud_de_sortie_78_Diagram> is unconnected in block <theVI>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <n_N9Cud_de_sortie_8098_Diagram> is unconnected in block <theVI>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <n_N9Cud_de_sortie_4534_Diagram> is unconnected in block <theVI>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <n_N9Cud_de_sortie_14515_Diagram> is unconnected in block <theVI>. It will be removed from the design.WARNING:Xst:1426 - The value init of the FF/Latch bSafeStart_ms hinder the constant cleaning in the block PXIe100ClkDetect. You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch bPushEnDly hinder the constant cleaning in the block HostWtAccessBlk.BusClkToReliableClkHS. You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch bPushEnDly hinder the constant cleaning in the block HostWtAccessBlk.BusClkToReliableClkHS. You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch bClkDetectDoneLcl hinder the constant cleaning in the block PXIe100ClkDetect. You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch bPllRstReg_31 hinder the constant cleaning in the block Puma20TimingEnginex. You should achieve better results by setting this init to 0.WARNING:Xst:1290 - Hierarchical block <n_N9Cud_d_apost_entrE9e_106_Diagram> is unconnected in block <n_Boucle_cadencE9e_43_Diagram>. It will be removed from the design.

WARNING:Xst:1290 - Hierarchical block <n_N9Cud_d_apost_entrE9e_8126_Diagram> is unconnected in block <n_Boucle_cadencE9e_8065_Diagram>. It will be removed from the design.WARNING:Xst:1290 - Hierarchical block <n_N9Cud_d_apost_entrE9e_14543_Diagram> is unconnected in block <n_Boucle_cadencE9e_14482_Diagram>. It will be removed from the design.

Synthesizing (advanced) Unit <ChinchDmaComponentStateTransitionEnableChain>.The following registers are absorbed into counter <vLatchedTimeout>: 1 register on signal <vLatchedTimeout>.Unit <ChinchDmaComponentStateTransitionEnableChain> synthesized (advanced).

Synthesizing (advanced) Unit <ChinchDmaInputController_1>.The following registers are absorbed into counter <HandleArbiterRequests.bEvictionCounter>: 1 register on signal <HandleArbiterRequests.bEvictionCounter>.The following registers are absorbed into counter <bDataWordCounter>: 1 register on signal <bDataWordCounter>.Unit <ChinchDmaInputController_1> synthesized (advanced).

Synthesizing (advanced) Unit <ChinchDmaInputController_2>.The following registers are absorbed into counter <HandleArbiterRequests.bEvictionCounter>: 1 register on signal <HandleArbiterRequests.bEvictionCounter>.The following registers are absorbed into counter <bDataWordCounter>: 1 register on signal <bDataWordCounter>.Unit <ChinchDmaInputController_2> synthesized (advanced).

Synthesizing (advanced) Unit <ChinchDmaInputFifoInterface>.INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_vStreamStateFromController> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 2-bit | | | weA | connected to signal <GND> | high | | addrA | connected to signal <vStreamStateValueFromController> | | | diA | connected to signal <GND> | | | doA | connected to signal <vStreamStateFromController> | | -----------------------------------------------------------------------INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_StreamStateBlock.dStreamStateFromController> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 2-bit | |

| weA | connected to signal <GND> | high | | addrA | connected to signal <StreamStateBlock.dStreamStateValueFromController> | | | diA | connected to signal <GND> | | | doA | connected to signal <StreamStateBlock.dStreamStateFromController> | | -----------------------------------------------------------------------INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_StreamStateBlock.dStreamStateValue> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 2-bit | | | weA | connected to signal <GND> | high | | addrA | connected to signal <StreamStateBlock.dStreamState> | | | diA | connected to signal <GND> | | | doA | connected to signal <StreamStateBlock.dStreamStateValue> | | -----------------------------------------------------------------------INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_StreamStateBlock.vStreamStateValue> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 2-bit | | | weA | connected to signal <GND> | high | | addrA | connected to signal <vStreamState> | | | diA | connected to signal <GND> | | | doA | connected to signal <StreamStateBlock.vStreamStateValue> | | -----------------------------------------------------------------------Unit <ChinchDmaInputFifoInterface> synthesized (advanced).

Synthesizing (advanced) Unit <ChinchDmaOutputController>.The following registers are absorbed into accumulator <bByteLane>: 1 register on signal <bByteLane>.The following registers are absorbed into counter <OutstandingReadCounter.bReadCount>: 1 register on signal <OutstandingReadCounter.bReadCount>.Unit <ChinchDmaOutputController> synthesized (advanced).

Synthesizing (advanced) Unit <ChinchDmaOutputFifoInterface>.INFO:Xst:3217 - HDL ADVISOR - Register <iDataToPush> currently described with an asynchronous reset, could be combined with distributed RAM <Mram_bStreamStateValue> for implementation on block RAM resources if you made this reset synchronous instead. ----------------------------------------------------------------------- | ram_type | Distributed | | -----------------------------------------------------------------------

| Port A | | aspect ratio | 4-word x 2-bit | | | weA | connected to signal <GND> | high | | addrA | connected to signal <bStreamState> | | | diA | connected to signal <GND> | | | doA | connected to signal <bStreamStateValue> | | -----------------------------------------------------------------------INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_StreamStateBlock.vStreamStateValue> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 2-bit | | | weA | connected to signal <GND> | high | | addrA | connected to signal <StreamStateBlock.vStreamState> | | | diA | connected to signal <GND> | | | doA | connected to signal <StreamStateBlock.vStreamStateValue> | | -----------------------------------------------------------------------INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_StreamStateBlock.dStreamState> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 2-bit | | | weA | connected to signal <GND> | high | | addrA | connected to signal <StreamStateBlock.vStreamStateValueDelays<0>> | | | diA | connected to signal <GND> | | | doA | connected to signal <StreamStateBlock.dStreamState> | | -----------------------------------------------------------------------Unit <ChinchDmaOutputFifoInterface> synthesized (advanced).

Synthesizing (advanced) Unit <ChinchInterfaceDmaRegisters_1>.The following registers are absorbed into accumulator <bSatcr>: 1 register on signal <bSatcr>.Unit <ChinchInterfaceDmaRegisters_1> synthesized (advanced).



Synthesizing (advanced) Unit <ChinchRegisterAccess>.

The following registers are absorbed into counter <bTimeoutCounterReg>: 1 register on signal <bTimeoutCounterReg>.Unit <ChinchRegisterAccess> synthesized (advanced).

Synthesizing (advanced) Unit <ClockGenXilinxV5>.The following registers are absorbed into counter <RxDcm.bRxUnResetClockCounter>: 1 register on signal <RxDcm.bRxUnResetClockCounter>.The following registers are absorbed into counter <TxDcm.bTxLockedFilterCount>: 1 register on signal <TxDcm.bTxLockedFilterCount>.The following registers are absorbed into counter <RxDcm.bRxLockedFilterCount>: 1 register on signal <RxDcm.bRxLockedFilterCount>.The following registers are absorbed into counter <TxDcm.bTxUnResetClockCounter>: 1 register on signal <TxDcm.bTxUnResetClockCounter>.Unit <ClockGenXilinxV5> synthesized (advanced).

Synthesizing (advanced) Unit <CrossSwitchInterface>.The following registers are absorbed into counter <cCounter>: 1 register on signal <cCounter>.Unit <CrossSwitchInterface> synthesized (advanced).

Synthesizing (advanced) Unit <DiagramReset>.The following registers are absorbed into counter <DiagramResetFSM.rTimerCount>: 1 register on signal <DiagramResetFSM.rTimerCount>.Unit <DiagramReset> synthesized (advanced).

Synthesizing (advanced) Unit <InStrmFifoFlags>.The following registers are absorbed into accumulator <oByteLanePtrLoc>: 1 register on signal <oByteLanePtrLoc>.The following registers are absorbed into counter <iWriteSamplePtrUns>: 1 register on signal <iWriteSamplePtrUns>.INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n0225> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 4-word x 2-bit | | | weA | connected to signal <GND> | high | | addrA | connected to signal <oByteLanePtrLoc<2:1>> | | | diA | connected to signal <GND> | | | doA | connected to internal node | | -----------------------------------------------------------------------INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n0234> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. ----------------------------------------------------------------------- | ram_type | Distributed | | -----------------------------------------------------------------------

| Port A | | aspect ratio | 8-word x 4-bit | | | weA | connected to signal <GND> | high | | addrA | connected to signal <oByteLanePtrLoc> | | | diA | connected to signal <GND> | | | doA | connected to internal node | | -----------------------------------------------------------------------Unit <InStrmFifoFlags> synthesized (advanced).

Synthesizing (advanced) Unit <NiFpgaClockManagerControl>.The following registers are absorbed into counter <rTimerCount>: 1 register on signal <rTimerCount>.Unit <NiFpgaClockManagerControl> synthesized (advanced).

Synthesizing (advanced) Unit <NiFpgaFlipFlopFifo>.The following registers are absorbed into counter <cFullCountLoc>: 1 register on signal <cFullCountLoc>.Unit <NiFpgaFlipFlopFifo> synthesized (advanced).

Synthesizing (advanced) Unit <NiFpgaRegFrameworkShiftReg>.The following registers are absorbed into counter <cCounter>: 1 register on signal <cCounter>.Unit <NiFpgaRegFrameworkShiftReg> synthesized (advanced).

Synthesizing (advanced) Unit <NiFpgaTopEnInSyncForExternalClk_1>.The following registers are absorbed into counter <DelayTopEnInExtClk.eTimerCount>: 1 register on signal <DelayTopEnInExtClk.eTimerCount>.Unit <NiFpgaTopEnInSyncForExternalClk_1> synthesized (advanced).

Synthesizing (advanced) Unit <NiFpgaTopEnInSyncForExternalClk_2>.The following registers are absorbed into counter <DelayTopEnInExtClk.eTimerCount_0>: 1 register on signal <DelayTopEnInExtClk.eTimerCount_0>.Unit <NiFpgaTopEnInSyncForExternalClk_2> synthesized (advanced).

Synthesizing (advanced) Unit <OutStrmFifoFlags>.The following registers are absorbed into accumulator <iReqSamplePtrUns>: 1 register on signal <iReqSamplePtrUns>.The following registers are absorbed into accumulator <iWriteSamplePtrUnsBytes>: 1 register on signal <iWriteSamplePtrUnsBytes>.Unit <OutStrmFifoFlags> synthesized (advanced).

Synthesizing (advanced) Unit <OutStrmOutputHandler>.The following registers are absorbed into accumulator <bStartingByteLane>: 1 register on signal <bStartingByteLane>.Unit <OutStrmOutputHandler> synthesized (advanced).

Synthesizing (advanced) Unit <Puma20TimingEngine>.The following registers are absorbed into counter <rLockedFilterCount>: 1 register on signal <rLockedFilterCount>.The following registers are absorbed into counter <bSlowClkCnt_0>: 1 register on signal <bSlowClkCnt_0>.Unit <Puma20TimingEngine> synthesized (advanced).

Synthesizing (advanced) Unit <ViControl>.The following registers are absorbed into counter <EnableInBlk.rTimerCount>: 1 register on signal <EnableInBlk.rTimerCount>.Unit <ViControl> synthesized (advanced).

=========================================================================Advanced HDL Synthesis Report

Macro Statistics# RAMs : 15 4x2-bit single-port distributed Read Only RAM : 13 8x4-bit single-port distributed Read Only RAM : 2# Adders/Subtractors : 56 1-bit subtractor : 4 10-bit adder : 6 10-bit subtractor : 7 10-bit subtractor borrow in : 3 11-bit adder : 1 17-bit adder : 4 17-bit subtractor : 1 2-bit adder : 2 2-bit addsub : 1 3-bit adder : 7 3-bit addsub : 2 3-bit subtractor : 4 32-bit addsub : 3 4-bit adder : 2 4-bit subtractor : 1 5-bit subtractor : 1 7-bit adder : 1 7-bit subtractor : 3 8-bit adder : 1 8-bit subtractor : 2# Counters : 30 1-bit down counter : 2 10-bit up counter : 2 10-bit updown counter : 1 11-bit up counter : 1 13-bit up counter : 1 14-bit down counter : 1 14-bit up counter : 1 2-bit up counter : 1 25-bit up counter : 1 26-bit up counter : 1 3-bit down counter : 1 3-bit updown counter : 1 32-bit down counter : 8 5-bit down counter : 1 6-bit down counter : 1 8-bit down counter : 4 8-bit up counter : 2# Accumulators : 9

10-bit up loadable accumulator : 1 11-bit up loadable accumulator : 1 3-bit up accumulator : 2 3-bit up loadable accumulator : 2 32-bit updown loadable accumulator : 3# Registers : 5559 Flip-Flops : 5559# Comparators : 63 10-bit comparator equal : 5 10-bit comparator greater : 7 10-bit comparator lessequal : 3 11-bit comparator lessequal : 1 16-bit comparator not equal : 2 17-bit comparator greater : 2 2-bit comparator lessequal : 5 3-bit comparator greater : 4 3-bit comparator lessequal : 15 32-bit comparator greater : 11 4-bit comparator greater : 2 8-bit comparator greater : 6# Multiplexers : 1224 1-bit 2-to-1 multiplexer : 962 1-bit 3-to-1 multiplexer : 18 1-bit 4-to-1 multiplexer : 4 1-bit 5-to-1 multiplexer : 2 1-bit 7-to-1 multiplexer : 3 10-bit 2-to-1 multiplexer : 26 11-bit 2-to-1 multiplexer : 3 12-bit 2-to-1 multiplexer : 1 16-bit 2-to-1 multiplexer : 32 16-bit 6-to-1 multiplexer : 1 2-bit 2-to-1 multiplexer : 23 2-bit 4-to-1 multiplexer : 2 3-bit 2-to-1 multiplexer : 36 32-bit 2-to-1 multiplexer : 47 4-bit 2-to-1 multiplexer : 4 5-bit 2-to-1 multiplexer : 3 6-bit 2-to-1 multiplexer : 3 64-bit 2-to-1 multiplexer : 16 64-bit 3-to-1 multiplexer : 1 7-bit 2-to-1 multiplexer : 5 8-bit 2-to-1 multiplexer : 31 8-bit 5-to-1 multiplexer : 1# Decoders : 3 1-of-2 decoder : 2 1-of-32 decoder : 1# FSMs : 36# Xors : 158 1-bit xor2 : 158

=========================================================================

=========================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1989 - Unit <NiFpgaAG_FPGA_Generate_and_Acquire>: instances <n_N9Cud_d_apost_entrE9e_68_Diagram>, <n_N9Cud_d_apost_entrE9e_8088_Diagram> of unit <XDataNode> are equivalent, second instance is removedWARNING:Xst:1989 - Unit <NiFpgaAG_FPGA_Generate_and_Acquire>: instances <n_N9Cud_d_apost_entrE9e_68_Diagram>, <n_N9Cud_d_apost_entrE9e_4524_Diagram> of unit <XDataNode> are equivalent, second instance is removedWARNING:Xst:1989 - Unit <NiFpgaAG_FPGA_Generate_and_Acquire>: instances <n_N9Cud_d_apost_entrE9e_68_Diagram>, <n_N9Cud_d_apost_entrE9e_14505_Diagram> of unit <XDataNode> are equivalent, second instance is removedWARNING:Xst:1426 - The value init of the FF/Latch bPushEnDly hinder the constant cleaning in the block SafeBusCrossing_1. You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch bPushEnDly hinder the constant cleaning in the block SafeBusCrossing_2. You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch bPllRstReg_31 hinder the constant cleaning in the block Puma20TimingEngine. You should achieve better results by setting this init to 0.WARNING:Xst:1426 - The value init of the FF/Latch bSafeStart_ms hinder the constant cleaning in the block Puma20ClkDetect. You should achieve better results by setting this init to 1.WARNING:Xst:1426 - The value init of the FF/Latch bClkDetectDoneLcl hinder the constant cleaning in the block Puma20ClkDetect. You should achieve better results by setting this init to 1.WARNING:Xst:638 - in unit bushold Conflict on KEEP property on signal RioClk40Crossing.RioClk40FromInterface/BlkOut.oDataAckClkEnable and RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzFromInterface/BlkOut.oDataAckClkEnable RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzFromInterface/BlkOut.oDataAckClkEnable signal will be lost.Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/I2cReadWritex/FSM_13> on signal <rState[1:3]> with user encoding.------------------------- State | Encoding------------------------- idle | 000 runcycle | 001 checkbusy | 010 stopcycle | 011 checkstop | 100 acknowledge | 101-------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/I2cReadWritex/FSM_12> on signal <rState[1:4]> with user encoding.-------------------------------- State | Encoding--------------------------------

idle | 0000 checkack | 0001 slaveaddress | 0010 slaveaddressstart | 0011 byteaddress | 0100 byteaddressstart | 0101 readcommand | 0110 readcommandstart | 0111 writedatabyte | 1000 writedatabytestart | 1001 readdatabyte | 1010 readdatabytestart | 1011--------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/CrossSwitchSourceSelectx/CrossSwitchInterfacex/FSM_14> on signal <cState[1:2]> with user encoding.------------------------------ State | Encoding------------------------------ idle | 00 startserialize | 01 waitmorecycles | 10 loadswitchconfig | 11------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/FSM_5> on signal <cDisablerState[1:3]> with user encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/FSM_5> on signal <cDisablerState[1:3]> with user encoding.-------------------------------- State | Encoding-------------------------------- idle | 000 wait4disabledone | 001 wait4resetdone | 010 wait4pushresetdone | 011 wait4popresetdone | 100 wait4reenable | 101 wait4empty | 110--------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/FSM_6> on signal <vEnableChainState[1:2]> with gray encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.Chinc

hDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/FSM_6> on signal <vEnableChainState[1:2]> with gray encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/FSM_6> on signal <vEnableChainState[1:2]> with gray encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/FSM_6> on signal <vEnableChainState[1:2]> with gray encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/FSM_6> on signal <vEnableChainState[1:2]> with gray encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/FSM_6> on signal <vEnableChainState[1:2]> with gray encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/FSM_6> on signal <vEnableChainState[1:2]> with gray encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/FSM_6> on signal <vEnableChainState[1:2]> with gray encoding.--------------------------------------- State | Encoding--------------------------------------- idle | 00 waitforstrobedeassertion | 11 waitfortransitioncomplete | 01---------------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.FifoClearController/FSM_7> on signal <cDisablerState[1:3]> with user encoding.-------------------------------- State | Encoding-------------------------------- idle | 000 wait4disabledone | 001 wait4resetdone | 010 wait4pushresetdone | 011 wait4popresetdone | 100 wait4reenable | 101 wait4empty | 110--------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_ModuleA_AGen

ClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/FSM_3> on signal <iEoState[1:2]> with user encoding.Optimizing FSM <Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/FSM_3> on signal <iEoState[1:2]> with user encoding.------------------------------------------------ State | Encoding------------------------------------------------ waitingforloopenableoutassertion | 00 pushenableouttooutsidedomain | 01 waitingforloopenableoutdeassertion | 10------------------------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/FSM_2> on signal <EnableInAndClr.IClkIsExternal.iEnableInState[1:3]> with user encoding.Optimizing FSM <Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/FSM_2> on signal <EnableInAndClr.IClkIsExternal.iEnableInState[1:3]> with user encoding.-------------------------------------- State | Encoding-------------------------------------- idle | 000 waitfortopenintoassert | 001 subdiagenabled | 010 waitfortopenintodeassert | 011 waitforenableclrpulse | 100--------------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/FSM_4> on signal <iEoState[1:2]> with user encoding.------------------------------------------------ State | Encoding------------------------------------------------ waitingforloopenableoutassertion | 00 pushenableouttooutsidedomain | 01 waitingforloopenableoutdeassertion | 10------------------------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theVI/ViControlx/FSM_8> on signal <EnableInBlk.rEnableInState[1:2]> with gray encoding.------------------------------------------------ State | Encoding------------------------------------------------ idle | 00 enableindeasserted | 01 waituntilinternalclocksbecomevalid | unreached

waituntilcomponentsinit | 11 enableinasserted | 10 enableindeassertionnotsupportederr | unreached------------------------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/FSM_10> on signal <DelayTopEnInExtClk.eDelayTopEnInState[1:3]> with gray encoding.------------------------------------------------ State | Encoding------------------------------------------------ idle | 000 waitforasyncresetassertionduration | 001 waitforasyncrstdeasrtpropdly | 011 waitforsyncresetassertionduration | 010 topeninassertedtoextclk | 110------------------------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/FSM_11> on signal <DelayTopEnInExtClk.eDelayTopEnInState[1:3]> with gray encoding.------------------------------------------------ State | Encoding------------------------------------------------ idle | 000 waitforasyncresetassertionduration | 001 waitforasyncrstdeasrtpropdly | 011 waitforsyncresetassertionduration | 010 topeninassertedtoextclk | 110------------------------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <Puma20Window/theVI/DiagramResetx/FSM_9> on signal <DiagramResetFSM.rDiagramResetState[1:4]> with user encoding.-------------------------------------------------- State | Encoding-------------------------------------------------- idle | 0000 waitforexternalcircuittoinit | 0001 waitforbaseclkstobecomevalid | 0010 waitforclkenablerequest | unreached waitforgatedbaseclkstobecomevalid | 0100 waitfordervclkstobecomevalid | 0101 waitforresetassertionduration | 0110 waitfordiagrstdeasrtpropdly | 0111 waitforhosttoassertdiagrst | 1000 waituntilderivedfromexternalshutdown | 1001 diagrstassertionnotsupportederr | unreached--------------------------------------------------Analyzing FSM <MFsm> for best encoding.

Optimizing FSM <Puma20Window/NiFpgaStockDcmInst0/NiFpgaClockManagerControlx/FSM_1> on signal <rCmState[1:2]> with gray encoding.---------------------------------------------- State | Encoding---------------------------------------------- waitforclkintobecomevalid | 00 waitforcmtoinitialize | 01 waitforcmtolock | 11 waitforbufgenassertionduration | unreached cmrunning | 10 waitforbufgendeassertionduration | unreached----------------------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <ChinchLvFpgaInterfacex/FSM_19> on signal <bStreamState[1:2]> with gray encoding.Optimizing FSM <ChinchLvFpgaInterfacex/FSM_19> on signal <bStreamState[1:2]> with gray encoding.---------------------- State | Encoding---------------------- unlinked | 00 disabled | 01 enabled | 11 flushing | 10----------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputx/ChinchDmaInputControllerx/FSM_20> on signal <FifoController.bFifoState[1:2]> with gray encoding.------------------------ State | Encoding------------------------ directfifo | 00 backup0 | 01 backup1 | 11------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputx/ChinchDmaInputControllerx/FSM_21> on signal <bDmaInputState[1:4]> with user encoding.---------------------------- State | Encoding---------------------------- disablerequest | 0000 senddoneheader | 0001 disabled | 0010 idle | 0011 fifoclear | 0100 waitforarbiter | 0101 packetsetup | 0110 sendheader | 0111 transmitdata | 1000

----------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputx/ChinchDmaInputControllerx/FSM_17> on signal <FifoController.bFifoState[1:2]> with gray encoding.------------------------ State | Encoding------------------------ directfifo | 00 backup0 | 01 backup1 | 11------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputx/ChinchDmaInputControllerx/FSM_18> on signal <bDmaInputState[1:4]> with user encoding.---------------------------- State | Encoding---------------------------- disablerequest | 0000 senddoneheader | 0001 disabled | 0010 idle | 0011 fifoclear | 0100 waitforarbiter | 0101 packetsetup | 0110 sendheader | 0111 transmitdata | 1000----------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[2].HostOutputStream.ChinchDMAOutputx/ChinchDmaSinkStreamStateControllerx/FSM_23> on signal <bStreamState[1:2]> with gray encoding.---------------------- State | Encoding---------------------- unlinked | 00 disabled | 01 enabled | 11 flushing | unreached----------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <ChinchLvFpgaInterfacex/DmaBlk.DmaComponents[2].HostOutputStream.ChinchDMAOutputx/ChinchDmaOutputControllerx/FSM_22> on signal <bDmaOutputRequestState[1:3]> with user encoding.----------------------- State | Encoding----------------------- idle | 000 enabled | 001 header | 010

hold | 011 disabling | 100-----------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <ChinchLvFpgaInterfacex/ChinchRegisterAccessx/FSM_15> on signal <bReadCompleterState[1:2]> with gray encoding.------------------------------------ State | Encoding------------------------------------ idle | 00 requestarbiteraccess | 01 transmitresponseheader | 11 transmitresponsedata | 10------------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <ChinchLvFpgaInterfacex/ChinchRegisterAccessx/FSM_16> on signal <bRegAccessState[1:3]> with user encoding.--------------------------------- State | Encoding--------------------------------- idle | 000 getwritedata | 001 writereadywait | 010 strobewrite | 011 strobereadwait | 100 stroberead | 101 getreadresponse | 110 triggerreadresponse | 111---------------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <ChinchLvFpgaInterfacex/ChinchCommIfcArbiterBasex/FSM_24> on signal <SmLogicAndFFs.sMainArbSt[1:3]> with user encoding.----------------------------- State | Encoding----------------------------- idle | 000 memspcacc | 001 statuspushacc | 010 msiacc | 011 instrmshighacc | 100 instrmsnormacc | 101 outstrmshighacc | 110 outstrmsnormacc | 111-----------------------------Analyzing FSM <MFsm> for best encoding.Optimizing FSM <PXIe100ClkDetect/FSM_0> on signal <bDetectState[1:4]> with user encoding.--------------------------------- State | Encoding--------------------------------- idle | 0000 writeone | 0001 waitforone | 0010

readone | 0011 writezero | 0100 waitforzero | 0101 readzero | 0110 waitonbaseclksvalid | 0111 monitorplllock | 1000 done | 1001---------------------------------INFO:Xst:1901 - Instance theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/TimingEnginex/LvdsBufG in unit TheWindow of type BUFGCE has been replaced by BUFGCTRLINFO:Xst:1901 - Instance theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/TimingEnginex/SeBufG in unit TheWindow of type BUFGCE has been replaced by BUFGCTRLINFO:Xst:1901 - Instance NiFpgaStockDcmInst0/DCMx in unit TheWindow of type DCM has been replaced by DCM_ADVINFO:Xst:1901 - Instance GenRows[0].GenMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst in unit InStrmRAMArray of type RAMB36 has been replaced by RAMB36_EXPINFO:Xst:1901 - Instance GenRows[0].GenMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst in unit InStrmRAMArray of type RAMB36 has been replaced by RAMB36_EXPINFO:Xst:1901 - Instance ADPRAM36Kx/BRamIs36.RAMB36_inst in unit DPRAM32Bits of type RAMB36 has been replaced by RAMB36_EXP

Optimizing unit <NiLvFpgaStockDigitalInput_1> ...

Optimizing unit <DFlopSlvResetVal_4> ...

Optimizing unit <DFlop_1> ...

Optimizing unit <DoubleSyncBase> ...

Optimizing unit <DoubleSyncAsyncInBase> ...






Optimizing unit <FGPA_Globals_viBit00> ...



Optimizing unit <Puma20Top> ...

Optimizing unit <I2cReadWrite> ...

Optimizing unit <Deserializer> ...

Optimizing unit <Serializer> ...

Optimizing unit <CrossSwitchSourceSelect> ...

Optimizing unit <CrossSwitchInterface> ...

Optimizing unit <NiFpgaAG_FPGA_Generate_and_Acquire> ...

Optimizing unit <Interface> ...

Optimizing unit <ChinchDmaInputFifoInterface> ...

Optimizing unit <InStrmRAMArray> ...

Optimizing unit <InStrmFifoFlags> ...

Optimizing unit <FifoPtrClockCrossing_1> ...

Optimizing unit <HandshakeBase_2> ...

Optimizing unit <NiFpgaFifoClearControl_1> ...

Optimizing unit <NiFpgaFifoPortReset_1> ...

Optimizing unit <ChinchDmaComponentStateTransitionEnableChain> ...

Optimizing unit <HandshakeBaseResetCross_3> ...

Optimizing unit <NiFpgaFifoCountControl_1> ...

Optimizing unit <ChinchDmaOutputFifoInterface> ...

Optimizing unit <OutStrmFifoFlags> ...

Optimizing unit <FifoPtrClockCrossing_2> ...

Optimizing unit <OutStrmDPRAM> ...

Optimizing unit <DPRAM32Bits> ...

Optimizing unit <NiFpgaFifoClearControl_2> ...

Optimizing unit <NiFpgaFifoPortReset_2> ...

Optimizing unit <NiFpgaFifoPopBuffer> ...

Optimizing unit <NiFpgaFlipFlopFifo> ...


Optimizing unit <ChinchLvFpgaIrq> ...



Optimizing unit <TimedLoopDomainCrosser_1> ...


Optimizing unit <NiFpgaAG_00000018_TimedLoopDiagram> ...

Optimizing unit <NiFpgaRegisterCoreBase_1> ...

Optimizing unit <NiFpgaAG_00000043_TimedLoopDiagram> ...

Optimizing unit <NiFpgaShiftReg_1> ...

Optimizing unit <TimedLoopDomainCrosser_2> ...

Optimizing unit <bushold> ...


Optimizing unit <NiFpgaRegFrameworkShiftReg> ...

Optimizing unit <ViControl> ...

Optimizing unit <NiFpgaHostAccessibleRegister_2> ...



Optimizing unit <HandshakeWithResetValueBase> ...

Optimizing unit <NiFpgaTopEnInSyncForExternalClk_1> ...

Optimizing unit <NiFpgaTopEnInSyncForExternalClk_2> ...

Optimizing unit <DiagramReset> ...


Optimizing unit <NiFpgaClockManagerControl> ...

Optimizing unit <ClockGenXilinxV5> ...

Optimizing unit <ChinchLvFpgaInterface> ...

Optimizing unit <ChinchInterfaceDmaRegisters_2> ...

Optimizing unit <ChinchDmaInputController_2> ...


Optimizing unit <ChinchDmaInputController_1> ...

Optimizing unit <OutStrmOutputHandler> ...


Optimizing unit <ChinchDmaSinkStreamStateController> ...

Optimizing unit <ChinchDmaOutputController> ...

Optimizing unit <ChinchRegisterAccess> ...

Optimizing unit <CHInChCommIfcArbiterBase> ...

Optimizing unit <StrmArbiter> ...

Optimizing unit <Puma20TimingEngine> ...

Optimizing unit <Puma20ClkDetect> ...WARNING:Xst:1303 - From in and out of unit Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain, both signals iLclReady and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/iPush have a KEEP attribute, signal iLclReady will be lost.WARNING:Xst:1303 - From in and out of unit Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest, both signals iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/iPush have a KEEP attribute, signal iPush will be lost.WARNING:Xst:1303 - From in and out of unit Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain, both signals iLclReady and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/iPush have a KEEP attribute, signal iLclReady will be lost.WARNING:Xst:1303 - From in and out of unit StreamStateBlock.HandshakeStateToBusClkDomain, both signals iLclReady and StreamStateBlock.HandshakeStateToBusClkDomain/iPush have a KEEP attribute, signal iLclReady will be lost.WARNING:Xst:1303 - From in and out of unit Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/HandshakeFullCount, both signals iLclReady and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/HandshakeFullCount/iPush have a KEEP attribute, signal iLclReady will be lost.

WARNING:Xst:1303 - From in and out of unit Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandshakeIrqNum, both signals iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/iPush have a KEEP attribute, signal iPush will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/

HandshakeTransitionRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal aTbClockSrcSel_inv and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable signal will be lost.

WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.Chinch

DmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.Chinch

DmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.Chin

chDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/BlkOut.oDataAckClkEnable

Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable and Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzToInterface/BlkOut.oDataAckClkEnable Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzToInterface/BlkOut.oDataAckClkEnable signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/

HandshakeTransitionTimeoutRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush signal will be lost.WARNING:Xst:638 - in unit Puma20Top Conflict on KEEP property on signal Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iPush and Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush signal will be lost.WARNING:Xst - Edge d0DdrDQ<31> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<30> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<29> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<28> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<27> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<26> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<25> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<24> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<23> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<22> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<21> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<20> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<19> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<18> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<17> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<16> has no source ports and will not be translated to

ABC.WARNING:Xst - Edge d0DdrDQ<15> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<14> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<13> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<12> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<11> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<10> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<9> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<8> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<7> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<6> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<5> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<4> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<3> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<2> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<1> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d0DdrDQ<0> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<31> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<30> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<29> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<28> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<27> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<26> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<25> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<24> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<23> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<22> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<21> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<20> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<19> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<18> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<17> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<16> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<15> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<14> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<13> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<12> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<11> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<10> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<9> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<8> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<7> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<6> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<5> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<4> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<3> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<2> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<1> has no source ports and will not be translated to ABC.WARNING:Xst - Edge d1DdrDQ<0> has no source ports and will not be translated to ABC.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block Puma20Top, actual ratio is 31.

WARNING:Xst:387 - The KEEP property attached to the net <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/iPush> may hinder timing optimization. You may achieve better results by removing this propertyWARNING:Xst:387 - The KEEP property attached to the net <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/iPush> may hinder timing optimization. You may achieve better results by removing this property

Final Macro Processing ...

Processing Unit <Puma20Top> :Found 2-bit shift register for signal <bBusReset>.Found 2-bit shift register for signal

<Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/CrossSwitchSourceSelectx/CrossSwitchInterfacex/cResetSl>.

Found 2-bit shift register for signal <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmFifoFlagsx/oWritesDisabledSamplePtrUnsGrayExtraDelay_ms>.

Found 2-bit shift register for signal <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmFifoFlagsx/oWriteSamplePtrUnsGray_9>.










Found 2-bit shift register for signal <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.Chinc

hDmaInputFifoInterfacex/InStrmFifox/InStrmFifoFlagsx/oWritesDisabledSamplePtrUnsGrayExtraDelay_ms>.











Found 2-bit shift register for signal <Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmFifoFlagsx/iReadSamplePtrUnsGray_9>.










Found 2-bit shift register for signal <Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/bDiagramReset>.

Found 2-bit shift register for signal <Puma20Window/theVI/ViControlx/bEnableOut>.Found 2-bit shift register for signal <ClockGenXilinxV5x/bRxClockMayBeLocked>.Found 2-bit shift register for signal <ClockGenXilinxV5x/bTxClockMayBeLocked>.Found 2-bit shift register for signal <ClockGenXilinxV5x/bDlyCtrlRdy>.Found 2-bit shift register for signal <Puma20TimingEnginex/rPllLockedNoRst>.Found 2-bit shift register for signal <Puma20TimingEnginex/bLockPllToOsc100>.Found 32-bit shift register for signal <Puma20TimingEnginex/bPllRstReg_0>.Found 2-bit shift register for signal <PXIe100ClkDetect/pSampleValue>.Found 2-bit shift register for signal <PXIe100ClkDetect/bPll200Locked>.Found 2-bit shift register for signal <PXIe100ClkDetect/bSafeStart>.Found 2-bit shift register for signal <PXIe100ClkDetect/bReadBackValue>.

Unit <Puma20Top> processed.

=========================================================================Final Register Report

Macro Statistics# Registers : 5169 Flip-Flops : 5169# Shift Registers : 46 2-bit shift register : 45 32-bit shift register : 1

=========================================================================INFO:Xst:2146 - In block <Puma20Top>, Shifter <Puma20TimingEnginex/Mshreg_rPllLockedNoRst_ms> <PXIe100ClkDetect/Mshreg_bPll200Locked_ms> are equivalent, XST will keep only <Puma20TimingEnginex/Mshreg_rPllLockedNoRst_ms>.

=========================================================================* Partition Report *=========================================================================

Partition Implementation Status-------------------------------

No Partitions were found in this design.

INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:----------------------------------------FindSrcOfAsyncThruGates : 100 (1)-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+Control Signal | Buffer(FF name) | Load |-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iPush(XST_GND:G) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/TimingEnginex/GenClockBuffers/ClkIdelay) | 2623 |Puma20Window/theVI/DiagramResetx/DiagramResetRegisterBlk.aDiagramResetLoc(Puma20Window/theVI/DiagramResetx/DiagramResetRegisterBlk.AsyncDiagramRst/FDCPEx:Q) | NONE(Puma20Window/theVI/Bit4_ctl_7/PlainControl.PlainControl/cQ_10) | 2561 |Puma20Window/theVI/DiagramResetx/DiagramResetRegisterBlk.rDiagramResetLoc(Puma20Window/theVI/DiagramResetx/DiagramResetRegisterBlk.SyncDiagramRst/FDCPEx:Q) | NONE(PumaFixedLogicx/FixedRegsClkXingx/SwReqTbDisableCross/oSig_msx/cLclQ) | 654 |PumaFixedLogicx/aMiteReset_n_inv(PumaFixedLogicx/aMiteReset_n_inv1_INV_0:O) | NONE(PumaFixedLogicx/mIoPortIn_Addr_10) | 624 |IoPort2Wrapperx/IoPort2x/IoPort2Basex/bLclIoReset(IoPort2Wrapperx/IoPort2x/IoPort2Basex/bLclIoReset:Q) | NONE(IoPort2Wrapperx/IoPort2x/IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.PacketFullyReceived/oInputCountGray_msx/cLclQ_1) | 612 |IoPort2Wrapperx/bRegWrite(IoPort2Wrapperx/XST_GND:G) | NONE(IoPort2Wrapperx/IoPort2x/IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFifo.InputFifo.DualPortRAMx/InferredRamx/Mram_iRAM) | 136 |

aIoReset_n_inv(aIoReset_n_inv1_INV_0:O) | NONE(fRefClkPrsnt_ms) | 128 |PumaFixedLogicx/mFixedRegsReadyOE(PumaFixedLogicx/XST_GND:G) | NONE(PumaFixedLogicx/FixedRegsClkXingx/mFlatDataToRegHS/BlkIn.iStoredDatax/cLclQ_57) | 91 |Puma20IoPort2Gluex/sIoAddr<0>(Puma20IoPort2Gluex/XST_GND:G) | NONE(Puma20IoPort2Gluex/FixedRegisterDataCross/BlkIn.iStoredDatax/cLclQ_30) | 68 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataAckClkEnable(XST_VCC:P) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/TimingEnginex/GenClockBuffers/ClkIdelay) | 13 |Puma20Window/theVI/FPGAwFIFOn0/BuiltinFifoIP/N1(Puma20Window/theVI/FPGAwFIFOn0/BuiltinFifoIP/XST_VCC:P) | NONE(Puma20Window/theVI/FPGAwFIFOn0/BuiltinFifoIP/U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gfn72.sngfifo36) | 8 |Puma20Window/theVI/FPGAwFIFOn1/BuiltinFifoIP/N1(Puma20Window/theVI/FPGAwFIFOn1/BuiltinFifoIP/XST_VCC:P) | NONE(Puma20Window/theVI/FPGAwFIFOn1/BuiltinFifoIP/U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[2].inst_extd/gonep.inst_prim/gfn72.sngfifo36) | 8 |Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viAcq_Regional/DoubleSyncSLVFromIO_ModuleA_AAcqClkBufRToLvToRioClk40/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viAcq_Regional/DoubleSyncSLVFromIO_ModuleA_AAcqClkBufRToLvToRioClk40/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viAcq_Regional/DoubleSyncSLVFromIO_ModuleA_AAcqClkBufRToLvToRioClk40/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/FDCPEx) | 3 |Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viClear_T2H_DMA/DoubleSyncSLVFromRioClk40ToRioClk40Derived5x1C00MHz/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viClear_T2H_DMA/DoubleSyncSLVFromRioClk40ToRioClk40Derived5x1C00MHz/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viClear_T2H_DMA/DoubleSyncSLVFromRioClk40ToRioClk40Derived5x1C00MHz/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bks/DoubleSyncSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bks/DoubleSyncSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bks/DoubleSyncSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |

Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bks_2/DoubleSyncSLVFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bks_2/DoubleSyncSLVFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viIO_Module_bks_2/DoubleSyncSLVFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viSoftware_Trigger8/DoubleSyncSLVFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viSoftware_Trigger8/DoubleSyncSLVFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viSoftware_Trigger8/DoubleSyncSLVFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/DoubleSyncSLVFromRioClk40ToRioClk40Derived5x1C00MHz/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/DoubleSyncSLVFromRioClk40ToRioClk40Derived5x1C00MHz/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/DoubleSyncSLVFromRioClk40ToRioClk40Derived5x1C00MHz/EachLineInst[0].DoubleSyncSLx/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/DoubleSyncSLVFromRioClk40ToRioClk40Derived5x1C00MHz/EachLineInst[1].DoubleSyncSLx/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/DoubleSyncSLVFromRioClk40ToRioClk40Derived5x1C00MHz/EachLineInst[1].DoubleSyncSLx/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/DoubleSyncSLVFromRioClk40ToRioClk40Derived5x1C00MHz/EachLineInst[1].DoubleSyncSLx/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/SyncTopEnInToExtClk.DblSyncToExtClk/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/SyncTopEnInToExtClk.DblSyncToExtClk/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/SyncTopEnInToExtClk.DblSyncToExtClk/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/SyncTopEnOut.DblSyncTopEnOut/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/SyncTopEnOut.DblSyncTopEnOut/DoubleSyncBasex/XST_GND:G) |

NONE(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/SyncTopEnOut.DblSyncTopEnOut/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/SyncTopEnInToExtClk.DblSyncToExtClk/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/SyncTopEnInToExtClk.DblSyncToExtClk/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/SyncTopEnInToExtClk.DblSyncToExtClk/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/SyncTopEnOut.DblSyncTopEnOut/DoubleSyncBasex/N0(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/SyncTopEnOut.DblSyncTopEnOut/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_CustomArbForTopEnablesPortOnResTopEnablePassThru/SyncTopEnInFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/SyncTopEnOut.DblSyncTopEnOut/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/N0(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/N0(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSig_msx/FDCPEx)| 3 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/N0(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.

ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/N0(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/FDCPEx) | 3 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.FifoClearController/PopSynchNeeded.FromPopDblSync/DoubleSyncBasex/N0(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.FifoClearController/PopSynchNeeded.FromPopDblSync/DoubleSyncBasex/XST_GND:G)| NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.FifoClearController/PopSynchNeeded.FromPopDblSync/DoubleSyncBasex/iDlySigx/FDCPEx) | 3 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.FifoClearController/PopSynchNeeded.ToPopDblSync/DoubleSyncBasex/N0(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.FifoClearController/PopSynchNeeded.ToPopDblSync/DoubleSyncBasex/XST_GND:G) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.FifoClearController/PopSynchNeeded.ToPopDblSync/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/FDCPEx) | 3 |Puma20Window/theVI/FPGAwFIFOn0/GenResetControl.ResetControl/BuiltInFifoRst.iBuiltInFifoRstReg(Puma20Window/theVI/FPGAwFIFOn0/GenResetControl.ResetControl/BuiltInFifoRst.iBuiltInFifoRstReg:Q) | NONE(Puma20Window/theVI/FPGAwFIFOn0/BuiltinFifoIP/U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg) | 2 |Puma20Window/theVI/FPGAwFIFOn1/GenResetControl.ResetControl/BuiltInFifoRst.iBuiltInFifoRstReg(Puma20Window/theVI/FPGAwFIFOn1/GenResetControl.ResetControl/BuiltInFifoRst.iBuiltInFifoRstReg:Q) | NONE(Puma20Window/theVI/FPGAwFIFOn1/BuiltinFifoIP/U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg) | 2 |Puma20IoPort2Gluex/FixedRegisterDataCross/BlkOut.SyncIReset/c1ResetFastLclx/cQ(Puma20IoPort2Gluex/FixedRegisterDataCross/BlkOut.SyncIReset/c1ResetFastLclx/cLclQ:Q) | NONE(Puma20IoPort2Gluex/FixedRegisterDataCross/BlkIn.iPushTogglex/cLclQ) | 1 |

Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift1<0>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[0].SlaveOserdes:SHIFTOUT1) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[0].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift1<1>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[1].SlaveOserdes:SHIFTOUT1) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[1].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift1<2>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[2].SlaveOserdes:SHIFTOUT1) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[2].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift1<3>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[3].SlaveOserdes:SHIFTOUT1) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[3].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift1<4>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[4].SlaveOserdes:SHIFTOUT1) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[4].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift1<5>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[5].SlaveOserdes:SHIFTOUT1) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[5].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift1<6>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[6].SlaveOserdes:SHIFTOUT1) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[6].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift1<7>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[7].SlaveOserdes:SHIFTOUT1) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[7].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift1<8>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[8].SlaveOserdes:SHIFTOUT1) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/

DataSer/SerialGen[8].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift1<9>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[9].SlaveOserdes:SHIFTOUT1) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[9].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift2<0>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[0].SlaveOserdes:SHIFTOUT2) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[0].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift2<1>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[1].SlaveOserdes:SHIFTOUT2) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[1].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift2<2>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[2].SlaveOserdes:SHIFTOUT2) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[2].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift2<3>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[3].SlaveOserdes:SHIFTOUT2) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[3].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift2<4>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[4].SlaveOserdes:SHIFTOUT2) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[4].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift2<5>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[5].SlaveOserdes:SHIFTOUT2) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[5].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift2<6>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[6].SlaveOserdes:SHIFTOUT2) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[6].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift2<7>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/

GenerationEnginex/DataSer/SerialGen[7].SlaveOserdes:SHIFTOUT2) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[7].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift2<8>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[8].SlaveOserdes:SHIFTOUT2) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[8].MasterOserdes) | 1 |Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/grGenShift2<9>(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[9].SlaveOserdes:SHIFTOUT2) | NONE(Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/DataSer/SerialGen[9].MasterOserdes) | 1 |Puma20Window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/iIResetFast(Puma20Window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/iIResetFast(Puma20Window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/iIResetFast(Puma20Window/theVI/

n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/

iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/

c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/

BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInput.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/HandshakeTransitionTimeoutRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/HandshakeFullCount/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/HandshakeFullCount/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/HandshakeFullCount/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomain/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |

Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeTransitionTimeoutRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/iIResetFast(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOutput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTransitionTimeoutRequest/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandshakeIrqNum/iIResetFast(Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandshakeIrqNum/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandshakeIrqNum/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iIResetFast(Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/iIResetFast(Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q) | NONE(Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/BlkIn.iPushTogglex/DFlopx/FDCPEx) | 1 |Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derived5x1C00MHzFromInterface/

aUserGpio<56> | IBUFDS | 1 |aUserGpio<57> | IBufDS_Diff_Out | 1 |aUserGpio<58> | IBufDS_Diff_Out | 1 |aUserGpio<59> | IBufDS_Diff_Out | 1 |INFO:TclTasksC:1850 - process run : Synthesize - XST is done.-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+

Timing Summary:---------------Speed Grade: -1

Minimum period: 27.395ns (Maximum Frequency: 36.503MHz) Minimum input arrival time before clock: 2.235ns Maximum output required time after clock: 4.438ns Maximum combinational path delay: 2.100ns

=========================================================================WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution for the specified device family. You are free to use it in order to take advantage of its enhanced HDL parsing/elaboration capabilities. However, please be aware that you may be impacted by language support differences. This version may also result in circuit performance and device utilization differences for your particular design. You can always revert back to the default XST solution by setting the "use_new_parser" option to value "no" on the XST command line or in the XST process properties panel.

Process "Synthesize - XST" completed successfullyINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ADPRAM36K.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/AcquisitionEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchCommIfcArbiterBase.vhd" into library

workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentInputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentOutputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStateTransitionEnableChain. vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStreamStateEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSinkStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSourceStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchInterfaceDmaRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchIrqInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaIrq.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchRegisterAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchSinkStream.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ClockGenXilinxV5.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchSourceSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForBit0_ctl_3RHFpgaReadPortOnResbush old.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpg aReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Program_Onboard_Cl ock_ctl_11RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Xpoint_Switch_Writ e_ctl_0RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForMiteIoLikePortOnResInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viAc q_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viBi t00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viCl ear_T2H_DMA_Timeout10.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viFe tch_Length9.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Acq_Reset12.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Gen_Reset7.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viSo ftware_Trigger8.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForSoftware_Trigger_ctl_12RHFpgaRead

PortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForTopEnablesPortOnResTopEnablePassT hru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlop.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBoolFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopSlvResetVal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM32Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM64Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Deserializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DiagramReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncAsyncInBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBoolAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSlAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viBit00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn0.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FeedbackNonSctlCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopE nInIClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoPtrClockCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FloatingFeedbackGInit.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpDynamicShift.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpNormalize.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpShiftCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/GenerationEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBaseResetCross.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV_Ack.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cIssueCycle.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cReadWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmRAMArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Interface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InvisibleResholder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/IoPort2LvFpga.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge

_Detect_vi_co.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co_2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587Base.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587ConnectorSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587CoreSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000001_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000003_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000005_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000018_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000001a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructure_62.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000002c_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000043_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000045_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000049_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004b_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd " into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0003.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0004.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructure_149.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005d_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005f_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000061_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000098_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_FPGA_Generate_and_Acquire.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_178.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_179.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_180.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_181.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbDelayer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbPowerOf2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbRW.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbSerializeAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOpNot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltInFifoResetControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltinFifoCounter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaClockManagerControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaCtrlIndRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDiRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDoWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoClearControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoCountControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPopBuffer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPortReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPushPopControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFlipFlopFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderRead.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaHostAccessibleRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLvJoinNumbers.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPipelinedOrGateTreeSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPulseSyncBaseWrapper.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegFrameworkShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCoreBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaStockDcm.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaTopEnInSyncForExternalClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFixedToFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAddCore.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtractCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixed.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixedCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaClipContainer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandlerSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFixedPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFloatingPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToInteger.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Add.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Equal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Greater.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32GreaterOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Less.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32LessOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32NotEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Subtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmDPRAM.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmOutputHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PacketSink.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgADPRAM36KUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgByteArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchConfig.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommIntConfiguration.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDataPackingFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaRegs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFpgaDeviceSpecs.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxpArithmetic.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgGray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgInStrmFifoUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgIoPort2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgLvFpgaConst.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNi6587.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaIrqRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaViControlRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiLvPrims.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgOneHot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgPuma20.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgStreamStates.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgSwitchedChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20ClkDetect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20DramMain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/RegionalClockBuf.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ResetSync.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SafeBusCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Serializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamDataReceiver.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamTcrUpdateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/StrmArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SubVICtlOrIndOpt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TheWindow.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopDomainCrosser.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimeoutManager.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TopEnablePassThru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViSignature.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNode.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNodeOut.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/bushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_idelay_ctrl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_infrastructure.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Sy nchronous_Lat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_r_opt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_w_opt.vhd" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.WARNING:ProjectMgmt - Circular Reference: work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtlWARNING:ProjectMgmt - Circular Reference: work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl

Started : "Translate".Running ngdbuild...Command Line: ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -u -uc Puma20Top.ucf -p xc5vsx50t-ff1136-1 Puma20Top.ngc Puma20Top.ngd

Command Line: C:\NIFPGA\programs\Xilinx14_4\ISE\bin\nt\unwrapped\ngdbuild.exe-intstyle ise -dd _ngo -aul -nt timestamp -u -uc Puma20Top.ucf -pxc5vsx50t-ff1136-1 Puma20Top.ngc Puma20Top.ngd

Reading NGO file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.ngc" ...Loading design module "C:\NIFPGA\jobs\vcnPe3C_D7RFefX/IoPort2Wrapper.ngc"...Loading design module "C:\NIFPGA\jobs\vcnPe3C_D7RFefX/PumaFixedLogic.ngc"...Loading design module "C:\NIFPGA\jobs\vcnPe3C_D7RFefX/Puma20IoPort2Glue.ngc"...Loading design module"C:\NIFPGA\jobs\vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn0.ngc"...Loading design module"C:\NIFPGA\jobs\vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn1.ngc"...Gathering constraint information from source properties...Done.

Annotating constraints to design from ucf file "Puma20Top.ucf" ...Resolving constraint associations...Checking Constraint Associations...ERROR:ConstraintSystem:58 - Constraint <INST "*n_bushold/*ShiftRegister/SyncBusReset/*oSigReturn*" TNM = TNM_Custom75;> [Puma20Top.ucf(1104)]: INST "*n_bushold/*ShiftRegister/SyncBusReset/*oSigReturn*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*PulseSyncBoolx/*oSigR eturn*" TNM = TNM_Custom213;> [Puma20Top.ucf(1157)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*PulseSyncBoolx/*oSigR eturn*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*iLclSt oredData*" TNM = TNM_Custom217;> [Puma20Top.ucf(1160)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*iLclSt oredData*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*iPushT oggle*" TNM = TNM_Custom219;> [Puma20Top.ucf(1162)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*iPushT

oggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*oPushT oggle0_ms*" TNM = TNM_Custom220;> [Puma20Top.ucf(1163)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*oPushT oggle0_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*oPushT oggleToReady*" TNM = TNM_Custom221;> [Puma20Top.ucf(1164)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*oPushT oggleToReady*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*iRdyPu shToggle_ms*" TNM = TNM_Custom222;> [Puma20Top.ucf(1165)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*iRdyPu shToggle_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*oPushT oggle1*" TNM = TNM_Custom224;> [Puma20Top.ucf(1166)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*oPushT oggle1*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*iReset *" TNM = TNM_Custom226;> [Puma20Top.ucf(1167)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*iReset *" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*iRdyPu shToggle*" TNM = TNM_Custom228;> [Puma20Top.ucf(1168)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/*HandshakeSLVx/*iRdyPu shToggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*PulseSyncBoolx/*oSigR eturn*" TNM = TNM_Custom243;> [Puma20Top.ucf(1180)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*PulseSyncBoolx/*oSigR eturn*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*iLclSt oredData*" TNM = TNM_Custom247;> [Puma20Top.ucf(1183)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*iLclSt oredData*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*iPushT

oggle*" TNM = TNM_Custom249;> [Puma20Top.ucf(1185)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*iPushT oggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*oPushT oggle0_ms*" TNM = TNM_Custom250;> [Puma20Top.ucf(1186)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*oPushT oggle0_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*oPushT oggleToReady*" TNM = TNM_Custom251;> [Puma20Top.ucf(1187)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*oPushT oggleToReady*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*iRdyPu shToggle_ms*" TNM = TNM_Custom252;> [Puma20Top.ucf(1188)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*iRdyPu shToggle_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*oPushT oggle1*" TNM = TNM_Custom254;> [Puma20Top.ucf(1189)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*oPushT oggle1*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*iReset *" TNM = TNM_Custom256;> [Puma20Top.ucf(1190)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*iReset *" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*iRdyPu shToggle*" TNM = TNM_Custom258;> [Puma20Top.ucf(1191)]: INST "*TimeLoopCoreFromRioClk40ToIO_ModuleA_AAcqClkBufRToLv/*HandshakeSLVx/*iRdyPu shToggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*PulseSyncBoolx/*oSigRet urn*" TNM = TNM_Custom273;> [Puma20Top.ucf(1203)]: INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*PulseSyncBoolx/*oSigRet urn*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*iLclStor edData*" TNM = TNM_Custom277;> [Puma20Top.ucf(1206)]: INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*iLclStor edData*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*iPushTog gle*" TNM = TNM_Custom279;> [Puma20Top.ucf(1208)]: INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*iPushTog gle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*oPushTog gle0_ms*" TNM = TNM_Custom280;> [Puma20Top.ucf(1209)]: INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*oPushTog gle0_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*oPushTog gleToReady*" TNM = TNM_Custom281;> [Puma20Top.ucf(1210)]: INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*oPushTog gleToReady*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*iRdyPush Toggle_ms*" TNM = TNM_Custom282;> [Puma20Top.ucf(1211)]: INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*iRdyPush Toggle_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*oPushTog gle1*" TNM = TNM_Custom284;> [Puma20Top.ucf(1212)]: INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*oPushTog gle1*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*iReset*" TNM = TNM_Custom286;> [Puma20Top.ucf(1213)]: INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*iReset*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*iRdyPush Toggle*" TNM = TNM_Custom288;> [Puma20Top.ucf(1214)]: INST "*TimeLoopCoreFromRioClk40ToRioClk40Derived5x1C00MHz/*HandshakeSLVx/*iRdyPush Toggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*iHoldSigInx/FDCPEx" TNM = TNM_Custom289;> [Puma20Top.ucf(1215)]: INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*iHoldSigInx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oHoldSigIn_msx/FDCPEx" TNM = TNM_Custom290;> [Puma20Top.ucf(1216)]: INST

"*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oHoldSigIn_msx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oSigReturn*" TNM = TNM_Custom291;> [Puma20Top.ucf(1217)]: INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oSigReturn*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*iSigOut_msx/FDCPEx" TNM = TNM_Custom292;> [Puma20Top.ucf(1218)]: INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*iSigOut_msx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oLocalSigOutCEx/FDCPEx" TNM = TNM_Custom293;> [Puma20Top.ucf(1219)]: INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oLocalSigOutCEx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*iHoldSigInx/FDCPEx" TNM = TNM_Custom295;> [Puma20Top.ucf(1220)]: INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*iHoldSigInx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oHoldSigIn_msx/FDCPEx" TNM = TNM_Custom296;> [Puma20Top.ucf(1221)]: INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oHoldSigIn_msx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oSigReturn*" TNM = TNM_Custom297;> [Puma20Top.ucf(1222)]: INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oSigReturn*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*iSigOut_msx/FDCPEx" TNM = TNM_Custom298;> [Puma20Top.ucf(1223)]: INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*iSigOut_msx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oLocalSigOutCEx/FDCPEx" TNM = TNM_Custom299;> [Puma20Top.ucf(1224)]: INST "*FPGAwFIFOn0*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB

asex/*oLocalSigOutCEx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl*DoubleSyncBasex*iDlySigx/FDCPEx" TNM = TNM_Custom301;> [Puma20Top.ucf(1225)]: INST "*FPGAwFIFOn0*ClearControl*DoubleSyncBasex*iDlySigx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*ClearControl*DoubleSyncBasex*DoubleSyncAsyncInBasex/oSig_msx/FD CPEx" TNM = TNM_Custom302;> [Puma20Top.ucf(1226)]: INST "*FPGAwFIFOn0*ClearControl*DoubleSyncBasex*DoubleSyncAsyncInBasex/oSig_msx/FD CPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*FIFOCounter*iDlySigx/FDCPEx" TNM = TNM_Custom303;> [Puma20Top.ucf(1227)]: INST "*FPGAwFIFOn0*FIFOCounter*iDlySigx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn0*FIFOCounter*DoubleSyncAsyncInBasex/oSig_msx/FDCPEx" TNM = TNM_Custom304;> [Puma20Top.ucf(1228)]: INST "*FPGAwFIFOn0*FIFOCounter*DoubleSyncAsyncInBasex/oSig_msx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*iHoldSigInx/FDCPEx" TNM = TNM_Custom309;> [Puma20Top.ucf(1233)]: INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*iHoldSigInx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oHoldSigIn_msx/FDCPEx" TNM = TNM_Custom310;> [Puma20Top.ucf(1234)]: INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oHoldSigIn_msx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oSigReturn*" TNM = TNM_Custom311;> [Puma20Top.ucf(1235)]: INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oSigReturn*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*iSigOut_msx/FDCPEx" TNM = TNM_Custom312;> [Puma20Top.ucf(1236)]: INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*iSigOut_msx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB

asex/*oLocalSigOutCEx/FDCPEx" TNM = TNM_Custom313;> [Puma20Top.ucf(1237)]: INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PushToPop*PulseSyncB asex/*oLocalSigOutCEx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*iHoldSigInx/FDCPEx" TNM = TNM_Custom315;> [Puma20Top.ucf(1238)]: INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*iHoldSigInx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oHoldSigIn_msx/FDCPEx" TNM = TNM_Custom316;> [Puma20Top.ucf(1239)]: INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oHoldSigIn_msx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oSigReturn*" TNM = TNM_Custom317;> [Puma20Top.ucf(1240)]: INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oSigReturn*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*iSigOut_msx/FDCPEx" TNM = TNM_Custom318;> [Puma20Top.ucf(1241)]: INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*iSigOut_msx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oLocalSigOutCEx/FDCPEx" TNM = TNM_Custom319;> [Puma20Top.ucf(1242)]: INST "*FPGAwFIFOn1*ClearControl/NiFpgaFifoPortResetx/Crossing.PopToPush*PulseSyncB asex/*oLocalSigOutCEx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl*DoubleSyncBasex*iDlySigx/FDCPEx" TNM = TNM_Custom321;> [Puma20Top.ucf(1243)]: INST "*FPGAwFIFOn1*ClearControl*DoubleSyncBasex*iDlySigx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*ClearControl*DoubleSyncBasex*DoubleSyncAsyncInBasex/oSig_msx/FD CPEx" TNM = TNM_Custom322;> [Puma20Top.ucf(1244)]: INST "*FPGAwFIFOn1*ClearControl*DoubleSyncBasex*DoubleSyncAsyncInBasex/oSig_msx/FD CPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*FIFOCounter*iDlySigx/FDCPEx" TNM = TNM_Custom323;> [Puma20Top.ucf(1245)]: INST "*FPGAwFIFOn1*FIFOCounter*iDlySigx/FDCPEx" does

not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*FPGAwFIFOn1*FIFOCounter*DoubleSyncAsyncInBasex/oSig_msx/FDCPEx" TNM = TNM_Custom324;> [Puma20Top.ucf(1246)]: INST "*FPGAwFIFOn1*FIFOCounter*DoubleSyncAsyncInBasex/oSig_msx/FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*iLclSt oredData*" TNM = TNM_Custom491;> [Puma20Top.ucf(1413)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*iLclSt oredData*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*ODataF lop*FDCPEx" TNM = TNM_Custom492;> [Puma20Top.ucf(1414)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*ODataF lop*FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*iPushT oggle*" TNM = TNM_Custom493;> [Puma20Top.ucf(1415)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*iPushT oggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*oPushT oggle0_ms*" TNM = TNM_Custom494;> [Puma20Top.ucf(1416)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*oPushT oggle0_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*oPushT oggleToReady*" TNM = TNM_Custom495;> [Puma20Top.ucf(1417)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*oPushT oggleToReady*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*iRdyPu shToggle_ms*" TNM = TNM_Custom496;> [Puma20Top.ucf(1418)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*iRdyPu shToggle_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*oPushT oggle1*" TNM = TNM_Custom498;> [Puma20Top.ucf(1419)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*oPushT oggle1*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*iReset

*" TNM = TNM_Custom500;> [Puma20Top.ucf(1420)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*iReset *" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*iRdyPu shToggle*" TNM = TNM_Custom502;> [Puma20Top.ucf(1421)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[0]*HandshakeStateToViClkDomain/*iRdyPu shToggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*iLclSt oredData*" TNM = TNM_Custom681;> [Puma20Top.ucf(1597)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*iLclSt oredData*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*ODataF lop*FDCPEx" TNM = TNM_Custom682;> [Puma20Top.ucf(1598)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*ODataF lop*FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*iPushT oggle*" TNM = TNM_Custom683;> [Puma20Top.ucf(1599)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*iPushT oggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*oPushT oggle0_ms*" TNM = TNM_Custom684;> [Puma20Top.ucf(1600)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*oPushT oggle0_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*oPushT oggleToReady*" TNM = TNM_Custom685;> [Puma20Top.ucf(1601)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*oPushT oggleToReady*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*iRdyPu shToggle_ms*" TNM = TNM_Custom686;> [Puma20Top.ucf(1602)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*iRdyPu shToggle_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*oPushT oggle1*" TNM = TNM_Custom688;> [Puma20Top.ucf(1603)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*oPushT oggle1*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*iReset *" TNM = TNM_Custom690;> [Puma20Top.ucf(1604)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*iReset *" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*iRdyPu shToggle*" TNM = TNM_Custom692;> [Puma20Top.ucf(1605)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[1]*HandshakeStateToViClkDomain/*iRdyPu shToggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*i LclStoredData*" TNM = TNM_Custom853;> [Puma20Top.ucf(1763)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*i LclStoredData*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*O DataFlop*FDCPEx" TNM = TNM_Custom854;> [Puma20Top.ucf(1764)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*O DataFlop*FDCPEx" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*i PushToggle*" TNM = TNM_Custom855;> [Puma20Top.ucf(1765)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*i PushToggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*o PushToggle0_ms*" TNM = TNM_Custom856;> [Puma20Top.ucf(1766)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*o PushToggle0_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*o PushToggleToReady*" TNM = TNM_Custom857;> [Puma20Top.ucf(1767)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*o PushToggleToReady*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*i RdyPushToggle_ms*" TNM = TNM_Custom858;> [Puma20Top.ucf(1768)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*i RdyPushToggle_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*o PushToggle1*" TNM = TNM_Custom860;> [Puma20Top.ucf(1769)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*o

PushToggle1*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*i Reset*" TNM = TNM_Custom862;> [Puma20Top.ucf(1770)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*i Reset*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*i RdyPushToggle*" TNM = TNM_Custom864;> [Puma20Top.ucf(1771)]: INST "*ChinchDmaFifosx/DmaBlk.DmaComponents[2]*HandshakeStateToDefaultClkDomain/*i RdyPushToggle*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*SyncStopRequestStrobeToViClk*PulseSyncBasex/*oSigReturn*" TNM = TNM_Custom871;> [Puma20Top.ucf(1778)]: INST "*SyncStopRequestStrobeToViClk*PulseSyncBasex/*oSigReturn*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM = TNM_Custom883;> [Puma20Top.ucf(1789)]: INST "*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM = TNM_Custom884;> [Puma20Top.ucf(1790)]: INST "*ChinchLvFpgaIrq*bIpIrq*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ViControlx*rGatedClkStartupErr*" TNM = TNM_Custom913;> [Puma20Top.ucf(1817)]: INST "*ViControlx*rGatedClkStartupErr*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ViControlx*rEnableDeassertionErr*" TNM = TNM_Custom915;> [Puma20Top.ucf(1819)]: INST "*ViControlx*rEnableDeassertionErr*" does not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST "*ViControlx*rDiagramResetAssertionErr*" TNM = TNM_Custom917;> [Puma20Top.ucf(1821)]: INST "*ViControlx*rDiagramResetAssertionErr*" does not match any design objects.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo37"= FROM "TNM_Custom75" TO "TNM_Custom76" 23.2476002400 ns DATAPATHONLY;> [Puma20Top.ucf(1882)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named 'TNM_Custom75'.












WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo84"= FROM "TNM_Custom243" TO "TNM_Custom244" 74.2425007499 ns DATAPATHONLY;>

[Puma20Top.ucf(1929)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named 'TNM_Custom243'.





















WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo106"= FROM

"TNM_Custom282" TO "TNM_Custom288" 2.4747500250 ns DATAPATHONLY;> [Puma20Top.ucf(1951)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named 'TNM_Custom288'.










WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo111"= FROM "TNM_Custom297" TO "TNM_Custom298" 14.8485001500 ns DATAPATHONLY;> [Puma20Top.ucf(1956)]: Unable to find an active 'TimeGrp' or 'TNM' or

'TPSync' constraint named 'TNM_Custom298'.











WARNING:ConstraintSystem:193 - The TNM 'TNM_Custom75', does not directly or indirectly drive any flip-flops, latches and/or RAMs and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo37'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the referencing constraint is not a PERIOD constraint. This TNM is used in the following user group or specification: <TIMESPEC "TS_CustomFromTo37"= FROM "TNM_Custom75" TO "TNM_Custom76" 23.2476002400 ns DATAPATHONLY;> [Puma20Top.ucf(1882)]

WARNING:ConstraintSystem:197 - The following specification is invalid because the referenced TNM constraint was removed: <TIMESPEC "TS_CustomFromTo37"= FROM "TNM_Custom75" TO "TNM_Custom76" 23.2476002400 ns DATAPATHONLY;> [Puma20Top.ucf(1882)]







WARNING:ConstraintSystem:192 - The TNM 'TNM_Custom220', does not directly or indirectly drive any flip-flops, latches and/or RAMS and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo72'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the none of the referencing constraints are a PERIOD constraint. This TNM is used in the following user groups and/or specifications: <TIMESPEC "TS_CustomFromTo72"= FROM "TNM_Custom219" TO "TNM_Custom220" 74.2425007499 ns DATAPATHONLY;> [Puma20Top.ucf(1917)] <TIMESPEC "TS_CustomFromTo74"= FROM "TNM_Custom220" TO "TNM_Custom224" 12.3737501250 ns DATAPATHONLY;> [Puma20Top.ucf(1919)]












WARNING:ConstraintSystem:192 - The TNM 'TNM_Custom250', does not directly or indirectly drive any flip-flops, latches and/or RAMS and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo87'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the none of the referencing constraints are a PERIOD constraint. This TNM is used in the following user groups and/or specifications: <TIMESPEC "TS_CustomFromTo87"= FROM "TNM_Custom249" TO "TNM_Custom250" 74.2425007499 ns DATAPATHONLY;> [Puma20Top.ucf(1932)]

<TIMESPEC "TS_CustomFromTo89"= FROM "TNM_Custom250" TO "TNM_Custom254" 12.3737501250 ns DATAPATHONLY;> [Puma20Top.ucf(1934)]








WARNING:ConstraintSystem:193 - The TNM 'TNM_Custom254', does not directly or indirectly drive any flip-flops, latches and/or RAMs and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo89'. If clock

manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the referencing constraint is not a PERIOD constraint. This TNM is used in the following user group or specification: <TIMESPEC "TS_CustomFromTo89"= FROM "TNM_Custom250" TO "TNM_Custom254" 12.3737501250 ns DATAPATHONLY;> [Puma20Top.ucf(1934)]















WARNING:ConstraintSystem:193 - The TNM 'TNM_Custom281', does not directly or

indirectly drive any flip-flops, latches and/or RAMs and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo103'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the referencing constraint is not a PERIOD constraint. This TNM is used in the following user group or specification: <TIMESPEC "TS_CustomFromTo103"= FROM "TNM_Custom281" TO "TNM_Custom282" 14.8485001500 ns DATAPATHONLY;> [Puma20Top.ucf(1948)]







WARNING:ConstraintSystem:193 - The TNM 'TNM_Custom286', does not directly or indirectly drive any flip-flops, latches and/or RAMs and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo105'. If clock

manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the referencing constraint is not a PERIOD constraint. This TNM is used in the following user group or specification: <TIMESPEC "TS_CustomFromTo105"= FROM "TNM_Custom87" TO "TNM_Custom286" 2.4747500250 ns DATAPATHONLY;> [Puma20Top.ucf(1950)]















WARNING:ConstraintSystem:193 - The TNM 'TNM_Custom295', does not directly or

indirectly drive any flip-flops, latches and/or RAMs and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo110'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the referencing constraint is not a PERIOD constraint. This TNM is used in the following user group or specification: <TIMESPEC "TS_CustomFromTo110"= FROM "TNM_Custom295" TO "TNM_Custom296" 10.5632143928 ns DATAPATHONLY;> [Puma20Top.ucf(1955)]














WARNING:ConstraintSystem:197 - The following specification is invalid because the referenced TNM constraint was removed:

<TIMESPEC "TS_CustomFromTo119"= FROM "TNM_Custom313" TO "TNM_Custom312" 10.5632143928 ns DATAPATHONLY;> [Puma20Top.ucf(1964)]







WARNING:ConstraintSystem:192 - The TNM 'TNM_Custom318', does not directly or indirectly drive any flip-flops, latches and/or RAMS and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo121'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the none of the referencing constraints are a PERIOD constraint. This TNM is used in the following user groups and/or specifications:

<TIMESPEC "TS_CustomFromTo121"= FROM "TNM_Custom317" TO "TNM_Custom318" 14.8485001500 ns DATAPATHONLY;> [Puma20Top.ucf(1966)] <TIMESPEC "TS_CustomFromTo122"= FROM "TNM_Custom319" TO "TNM_Custom318" 14.8485001500 ns DATAPATHONLY;> [Puma20Top.ucf(1967)]















WARNING:ConstraintSystem:193 - The TNM 'TNM_Custom492', does not directly or indirectly drive any flip-flops, latches and/or RAMs and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo208'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the referencing constraint is not a PERIOD constraint.

This TNM is used in the following user group or specification: <TIMESPEC "TS_CustomFromTo208"= FROM "TNM_Custom491" TO "TNM_Custom492" 8.8990001000 ns DATAPATHONLY;> [Puma20Top.ucf(2053)]







WARNING:ConstraintSystem:193 - The TNM 'TNM_Custom495', does not directly or indirectly drive any flip-flops, latches and/or RAMs and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo210'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the referencing constraint is not a PERIOD constraint. This TNM is used in the following user group or specification: <TIMESPEC "TS_CustomFromTo210"= FROM "TNM_Custom495" TO "TNM_Custom496"

23.2476002400 ns DATAPATHONLY;> [Puma20Top.ucf(2055)]















WARNING:ConstraintSystem:192 - The TNM 'TNM_Custom686', does not directly or indirectly drive any flip-flops, latches and/or RAMS and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo305'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the none of the referencing constraints are a PERIOD constraint. This TNM is used in the following user groups and/or specifications:

<TIMESPEC "TS_CustomFromTo305"= FROM "TNM_Custom685" TO "TNM_Custom686" 23.2476002400 ns DATAPATHONLY;> [Puma20Top.ucf(2150)] <TIMESPEC "TS_CustomFromTo308"= FROM "TNM_Custom686" TO "TNM_Custom692" 3.8746000400 ns DATAPATHONLY;> [Puma20Top.ucf(2153)]















WARNING:ConstraintSystem:192 - The TNM 'TNM_Custom856', does not directly or indirectly drive any flip-flops, latches and/or RAMS and cannot be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo390'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the none of the referencing constraints are a PERIOD

constraint. This TNM is used in the following user groups and/or specifications: <TIMESPEC "TS_CustomFromTo390"= FROM "TNM_Custom855" TO "TNM_Custom856" 74.2425007499 ns DATAPATHONLY;> [Puma20Top.ucf(2235)] <TIMESPEC "TS_CustomFromTo392"= FROM "TNM_Custom856" TO "TNM_Custom860" 12.3737501250 ns DATAPATHONLY;> [Puma20Top.ucf(2237)]












Done...

Checking expanded design ...WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/FPGAwFIFOn1/GenResetControl.ResetControl/BuiltInFifoInput En.TopEnInFromOClkSyncToIClk/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSig x/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/FPGAwFIFOn0/GenResetControl.ResetControl/BuiltInFifoInput En.TopEnInFromOClkSyncToIClk/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSig x/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoCle arController/NiFpgaFifoPortResetx/Crossing.PopToPush/PulseSyncBasex/oLocalSig Outx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoCle arController/NiFpgaFifoPortResetx/Crossing.PushToPop/PulseSyncBasex/oLocalSig Outx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoCle arController/NiFpgaFifoPortResetx/Crossing.PopToPush/PulseSyncBasex/oLocalSig Outx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoCle

arController/NiFpgaFifoPortResetx/Crossing.PushToPop/PulseSyncBasex/oLocalSig Outx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingE dgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FD CPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDC PE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCP E_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn

put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingE dgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FD CPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDC PE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has

unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCP E_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataFl opx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataFl opx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.SyncORe set/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomai n/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataFl opx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataFl opx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.SyncORe set/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomai n/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDom ain/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopReq uest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopReq uest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopReq uest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.Syn cOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.oDa taFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.oDa taFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FD CPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x ' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/F DCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.SyncStopRequestStrobeToVi Clk/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmFifoFlagsx/IClkToOClkC rossing.SyncToOClk/DataReg/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.Fifo ClearController/NiFpgaFifoPortResetx/Crossing.PopToPush/PulseSyncBasex/oLocal SigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.Fifo ClearController/NiFpgaFifoPortResetx/Crossing.PushToPop/PulseSyncBasex/oLocal SigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/HandshakeFullCount/BlkOut.SyncOReset/c2Res etFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandshakeIr qNum/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Pu lseSyncBoolx/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Puls eSyncBoolx/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu

leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has

unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha

keSLVx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module

A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has

unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand

shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module

A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output

pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak

eSLVx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk

40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has

unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Pul seSyncBoolx/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDC PE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.S yncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[9].DFlopx/FDCPEx' has

unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[22].DFlopx/FDCPEx' has

unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[36].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[37].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[33].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[34].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[35].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[36].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[37].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/BlkOut.Syn cOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzToInterface/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE _1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/ChinchClkShifter.ShiftRegister/SyncBusReset/Pul seSyncBasex/oLocalSigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDom ainCrossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallin gEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit11/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit11/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit11/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit11/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit11/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit11/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit22/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit22/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit22/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit22/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit22/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit22/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit33/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit33/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit33/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit55/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit55/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/Clock DomainCrossing.BusClkToReliableClkHS/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDC PEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/Clock DomainCrossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFal lingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:452 - logical net 'aRsvdCtrl_OBUF' has no driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<31>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<30>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<29>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<28>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<27>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<26>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<25>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<24>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<23>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<22>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<21>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<20>' has no legal driver

WARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<19>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<18>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<17>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<16>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<15>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<14>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<13>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<12>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<11>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<10>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<9>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<8>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<7>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<6>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<5>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<4>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<3>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<2>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<1>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<0>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<31>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<30>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<29>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<28>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<27>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<26>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<25>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<24>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<23>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<22>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<21>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<20>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<19>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<18>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<17>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<16>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<15>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<14>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<13>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<12>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<11>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<10>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<9>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<8>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<7>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<6>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<5>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<4>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<3>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<2>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<1>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<0>' has no legal driver

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/pDisable" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/pDisable" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.SyncORe set/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomai n/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.SyncORe set/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn

put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomai n/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDom ain/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopReq uest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.Syn cOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/HandshakeFullCount/BlkOut.SyncOReset/c1Res etFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandshakeIr qNum/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<37>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<36>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<35>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<34>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<33>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<32>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<31>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<30>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<29>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<28>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<27>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<26>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<25>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<24>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<23>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<22>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<21>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<20>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<19>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<18>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<17>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<16>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<15>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<14>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<13>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<37>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<36>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<35>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<34>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<33>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<32>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<31>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<30>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<29>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<28>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<27>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<26>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<25>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<11>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<10>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<9>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<8>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<7>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<6>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<5>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<4>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<3>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<2>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<1>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<0>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/BlkOut.Syn cOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzToInterface/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDom ainCrossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/Clock DomainCrossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "PumaFixedLogicx/FixedRegsClkXingx/mFlatDataToRegHS/BlkOut.SyncOReset/c1Reset FastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "PumaFixedLogicx/FixedRegsClkXingx/I2cCrosser/BlkOut.SyncOReset/c1ResetFastLc l" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20IoPort2Gluex/FixedRegisterDataCross/BlkOut.SyncOReset/c1ResetFastLcl"INFO:TclTasksC:1850 - process run : Translate is done. is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:470 - bidirect pad net 'aUserGpio<35>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'aUserGpio_n<44>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'aUserGpio_n<42>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'aUserGpio_n<2>' has no legal driver



-------------------------------

NGDBUILD Design Results Summary: Number of errors: 89 Number of warnings: 891

Total REAL time to NGDBUILD completion: 3 min 58 secTotal CPU time to NGDBUILD completion: 1 min 47 sec

One or more errors were found during NGDBUILD. No NGD file will be written.

Writing NGDBUILD log file "Puma20Top.bld"...

Process "Translate" failed

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ADPRAM36K.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/AcquisitionEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchCommIfcArbiterBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentInputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentOutputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStateTransitionEnableChain. vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStreamStateEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSinkStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSourceStreamStateController.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchInterfaceDmaRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchIrqInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaIrq.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchRegisterAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchSinkStream.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ClockGenXilinxV5.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchSourceSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForBit0_ctl_3RHFpgaReadPortOnResbush old.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpg aReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Program_Onboard_Cl ock_ctl_11RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Xpoint_Switch_Writ e_ctl_0RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForMiteIoLikePortOnResInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viAc q_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viBi t00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viCl ear_T2H_DMA_Timeout10.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viFe

tch_Length9.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Acq_Reset12.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Gen_Reset7.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viSo ftware_Trigger8.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForSoftware_Trigger_ctl_12RHFpgaRead PortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForTopEnablesPortOnResTopEnablePassT hru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlop.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBoolFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopSlvResetVal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM32Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM64Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Deserializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DiagramReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncAsyncInBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBoolAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSlAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viBit00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FeedbackNonSctlCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopE nInIClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoPtrClockCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FloatingFeedbackGInit.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpDynamicShift.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpNormalize.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpShiftCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/GenerationEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBaseResetCross.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV_Ack.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cIssueCycle.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cReadWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifo.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmRAMArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Interface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InvisibleResholder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/IoPort2LvFpga.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co_2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587Base.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587ConnectorSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587CoreSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000001_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000003_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000005_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000018_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000001a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructure_62.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000002c_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000043_TimedLoopDiagram.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000045_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000049_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004b_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0003.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0004.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructure_149.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005d_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005f_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000061_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000098_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_FPGA_Generate_and_Acquire.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_178.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_179.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_180.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_181.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbDelayer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbPowerOf2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbRW.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbSerializeAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOpNot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltInFifoResetControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltinFifoCounter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaClockManagerControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaCtrlIndRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDiRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDoWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoClearControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoCountControl.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPopBuffer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPortReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPushPopControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFlipFlopFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaHostAccessibleRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLvJoinNumbers.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPipelinedOrGateTreeSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPulseSyncBaseWrapper.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegFrameworkShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCoreBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaStockDcm.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaTopEnInSyncForExternalClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCoerce.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFixedToFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAddCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtractCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixed.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixedCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaClipContainer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandlerSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFixedPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFloatingPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToInteger.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Add.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Equal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Greater.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32GreaterOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Less.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32LessOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32NotEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Subtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmDPRAM.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmOutputHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PacketSink.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgADPRAM36KUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgByteArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchConfig.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommIntConfiguration.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDataPackingFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaRegs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFpgaDeviceSpecs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxpArithmetic.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgGray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgInStrmFifoUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgIoPort2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgLvFpgaConst.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNi6587.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaIrqRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaViControlRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiLvPrims.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgOneHot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgPuma20.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgStreamStates.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgSwitchedChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20ClkDetect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20DramMain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/RegionalClockBuf.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ResetSync.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SafeBusCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Serializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamDataReceiver.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamTcrUpdateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/StrmArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SubVICtlOrIndOpt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TheWindow.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopDomainCrosser.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimeoutManager.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TopEnablePassThru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViSignature.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNode.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNodeOut.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/bushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_idelay_ctrl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_infrastructure.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Sy nchronous_Lat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_r_opt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_w_opt.vhd" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.WARNING:ProjectMgmt - Circular Reference: work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtlWARNING:ProjectMgmt - Circular Reference: work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtlINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ADPRAM36K.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/AcquisitionEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchCommIfcArbiterBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentInputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentOutputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStateTransitionEnableChain. vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStreamStateEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputController.vhd" into library

workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSinkStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSourceStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchInterfaceDmaRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchIrqInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaIrq.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchRegisterAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchSinkStream.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ClockGenXilinxV5.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchSourceSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForBit0_ctl_3RHFpgaReadPortOnResbush old.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpg aReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Program_Onboard_Cl

ock_ctl_11RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Xpoint_Switch_Writ e_ctl_0RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForMiteIoLikePortOnResInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viAc q_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viBi t00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viCl ear_T2H_DMA_Timeout10.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viFe tch_Length9.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Acq_Reset12.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Gen_Reset7.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viSo ftware_Trigger8.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForSoftware_Trigger_ctl_12RHFpgaRead PortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForTopEnablesPortOnResTopEnablePassT hru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlop.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBoolFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopSlvResetVal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM32Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM64Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Deserializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DiagramReset.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncAsyncInBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBoolAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSlAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viBit00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FeedbackNonSctlCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopE nInIClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoPtrClockCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FloatingFeedbackGInit.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpDynamicShift.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpNormalize.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpShiftCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/GenerationEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBaseResetCross.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV_Ack.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cIssueCycle.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cReadWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmRAMArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Interface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InvisibleResholder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/IoPort2LvFpga.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co_2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587Base.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587ConnectorSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587CoreSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000001_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000003_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000005_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000018_TimedLoopDiagram.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000001a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructure_62.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000002c_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000043_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000045_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000049_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004b_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0003.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0004.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructure_149.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005d_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005f_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000061_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000098_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_FPGA_Generate_and_Acquire.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_178.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_179.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_180.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_181.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbDelayer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbPowerOf2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbRW.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbSerializeAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOpNot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltInFifoResetControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltinFifoCounter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaClockManagerControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaCtrlIndRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDiRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDoWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoClearControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoCountControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPopBuffer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPortReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPushPopControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFlipFlopFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaHostAccessibleRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLvJoinNumbers.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPipelinedOrGateTreeSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPulseSyncBaseWrapper.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegFrameworkShiftReg.vhd" into library

workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCoreBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaStockDcm.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaTopEnInSyncForExternalClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFixedToFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAddCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtractCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixed.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixedCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaClipContainer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandlerSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFixedPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFloatingPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToInteger.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Add.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Equal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Greater.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32GreaterOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Less.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32LessOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32NotEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Subtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmDPRAM.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmOutputHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PacketSink.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgADPRAM36KUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgByteArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchConfig.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommIntConfiguration.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDataPackingFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaRegs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFpgaDeviceSpecs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxpArithmetic.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgGray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgInStrmFifoUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgIoPort2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgLvFpgaConst.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNi6587.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaIrqRegisters.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaViControlRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiLvPrims.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgOneHot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgPuma20.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgStreamStates.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgSwitchedChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20ClkDetect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20DramMain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/RegionalClockBuf.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ResetSync.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SafeBusCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Serializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamDataReceiver.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamTcrUpdateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/StrmArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SubVICtlOrIndOpt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TheWindow.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopController.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopDomainCrosser.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimeoutManager.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TopEnablePassThru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViSignature.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNode.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNodeOut.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/bushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_idelay_ctrl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_infrastructure.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Sy nchronous_Lat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_r_opt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_w_opt.vhd" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.WARNING:ProjectMgmt - Circular Reference: work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtlWARNING:ProjectMgmt - Circular Reference: work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtlINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ADPRAM36K.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/AcquisitionEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchCommIfcArbiterBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentEnableChain.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentInputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentOutputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStateTransitionEnableChain. vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStreamStateEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSinkStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSourceStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchInterfaceDmaRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchIrqInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaIrq.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchRegisterAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchSinkStream.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ClockGenXilinxV5.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchSourceSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForBit0_ctl_3RHFpgaReadPortOnResbush old.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpg aReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Program_Onboard_Cl ock_ctl_11RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Xpoint_Switch_Writ e_ctl_0RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForMiteIoLikePortOnResInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viAc q_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viBi t00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viCl ear_T2H_DMA_Timeout10.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viFe tch_Length9.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Acq_Reset12.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Gen_Reset7.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viSo ftware_Trigger8.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForSoftware_Trigger_ctl_12RHFpgaRead PortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForTopEnablesPortOnResTopEnablePassT hru.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlop.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBoolFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopSlvResetVal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM32Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM64Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Deserializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DiagramReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncAsyncInBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBoolAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSlAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viBit00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FeedbackNonSctlCore.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopE nInIClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoPtrClockCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FloatingFeedbackGInit.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpDynamicShift.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpNormalize.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpShiftCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/GenerationEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBaseResetCross.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV_Ack.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cIssueCycle.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cReadWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmRAMArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Interface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InvisibleResholder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/IoPort2LvFpga.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co_2.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587Base.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587ConnectorSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587CoreSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000001_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000003_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000005_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000018_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000001a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructure_62.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000002c_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000043_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000045_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000049_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004b_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0003.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0004.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructure_149.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005d_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005f_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000061_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000098_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_FPGA_Generate_and_Acquire.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_178.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_179.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_180.vhd

" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_181.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbDelayer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbPowerOf2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbRW.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbSerializeAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOpNot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltInFifoResetControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltinFifoCounter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaClockManagerControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaCtrlIndRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDiRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDoWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoClearControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoCountControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPopBuffer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPortReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPushPopControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFlipFlopFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaHostAccessibleRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLvJoinNumbers.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPipelinedOrGateTreeSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPulseSyncBaseWrapper.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegFrameworkShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCoreBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaStockDcm.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaTopEnInSyncForExternalClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFixedToFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAddCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareCore.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtractCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixed.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixedCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaClipContainer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandlerSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFixedPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFloatingPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToInteger.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Add.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Equal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Greater.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32GreaterOrEqual.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Less.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32LessOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32NotEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Subtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmDPRAM.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmOutputHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PacketSink.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgADPRAM36KUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgByteArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchConfig.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommIntConfiguration.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDataPackingFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaRegs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFpgaDeviceSpecs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxpArithmetic.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgGray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgInStrmFifoUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgIoPort2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgLvFpgaConst.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNi6587.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaIrqRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaViControlRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiLvPrims.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgOneHot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgPuma20.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgStreamStates.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgSwitchedChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20ClkDetect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20DramMain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/RegionalClockBuf.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ResetSync.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SafeBusCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Serializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamDataReceiver.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamTcrUpdateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/StrmArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SubVICtlOrIndOpt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TheWindow.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopDomainCrosser.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimeoutManager.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TopEnablePassThru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViSignature.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNode.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNodeOut.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/bushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_idelay_ctrl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_infrastructure.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Sy nchronous_Lat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_r_opt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_w_opt.vhd" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.WARNING:ProjectMgmt - Circular Reference: work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl

Started : "Translate".Running ngdbuild...Command Line: ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -u -uc Puma20Top.ucf -p xc5vsx50t-ff1136-1 Puma20Top.ngc Puma20Top.ngd

Command Line: C:\NIFPGA\programs\Xilinx14_4\ISE\bin\nt\unwrapped\ngdbuild.exe-intstyle ise -dd _ngo -aul -nt timestamp -u -uc Puma20Top.ucf -pxc5vsx50t-ff1136-1 Puma20Top.ngc Puma20Top.ngd

Reading NGO file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.ngc" ...Loading design module "C:\NIFPGA\jobs\vcnPe3C_D7RFefX/IoPort2Wrapper.ngc"...Loading design module "C:\NIFPGA\jobs\vcnPe3C_D7RFefX/PumaFixedLogic.ngc"...Loading design module "C:\NIFPGA\jobs\vcnPe3C_D7RFefX/Puma20IoPort2Glue.ngc"...Loading design module"C:\NIFPGA\jobs\vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn0.ngc"...Loading design module"C:\NIFPGA\jobs\vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn1.ngc"...Gathering constraint information from source properties...Done.

Annotating constraints to design from ucf file "Puma20Top.ucf" ...Resolving constraint associations...Checking Constraint Associations...WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo37"= FROM "TNM_Custom75" TO "TNM_Custom76" 23.2476002400 ns DATAPATHONLY;> [Puma20Top.ucf(1882)]: Unable to find an active 'TimeGrp' or 'TNM' or 'TPSync' constraint named 'TNM_Custom75'.












Done...

Checking expanded design ...WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/FPGAwFIFOn1/GenResetControl.ResetControl/BuiltInFifoInput En.TopEnInFromOClkSyncToIClk/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSig x/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/FPGAwFIFOn0/GenResetControl.ResetControl/BuiltInFifoInput En.TopEnInFromOClkSyncToIClk/DoubleSyncSlAsyncInx/DoubleSyncAsyncInBasex/oSig x/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoCle arController/NiFpgaFifoPortResetx/Crossing.PopToPush/PulseSyncBasex/oLocalSig Outx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoCle arController/NiFpgaFifoPortResetx/Crossing.PushToPop/PulseSyncBasex/oLocalSig Outx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoCle arController/NiFpgaFifoPortResetx/Crossing.PopToPush/PulseSyncBasex/oLocalSig Outx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/Input.FifoCle arController/NiFpgaFifoPortResetx/Crossing.PushToPop/PulseSyncBasex/oLocalSig Outx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingE dgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FD CPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT

ransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDC PE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCP E_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingE dgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FD CPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDC PE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn

put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCP E_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataFl opx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataFl opx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.SyncORe set/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn

put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomai n/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataFl opx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.oDataFl opx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.SyncORe set/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomai n/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDom ain/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopReq uest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopReq uest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopReq uest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.Syn cOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.oDa taFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.oDa taFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FD CPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake

TransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x ' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionTimeoutRequest/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/F DCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionTimeoutRequest/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.SyncStopRequestStrobeToVi Clk/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmFifoFlagsx/IClkToOClkC rossing.SyncToOClk/DataReg/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.Fifo ClearController/NiFpgaFifoPortResetx/Crossing.PopToPush/PulseSyncBasex/oLocal SigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/ChinchDmaComponentEnableChainx/Output.Fifo ClearController/NiFpgaFifoPortResetx/Crossing.PushToPop/PulseSyncBasex/oLocal SigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/HandshakeFullCount/BlkOut.SyncOReset/c2Res etFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandshakeIr qNum/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandShakeIr qAck/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Pu lseSyncBoolx/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Puls eSyncBoolx/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha

ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu

leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Ha ndshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output

pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha

keSLVx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_8065/TimeLoopCoreFromRioClk40ToIO_Modu leA_AAcqClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handsha keSLVx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module

A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has

unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Hand shakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake

SLVx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module

A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_43/TimeLoopCoreFromRioClk40ToIO_Module A_AGenClkBufRToLv/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshake SLVx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output

pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak

eSLVx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableOut.Handshak eSLVx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[29].DFlopx/FDCPEx' has unconnected output pin

WARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[21].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[20].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[19].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk

40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[8].DFlopx/FDCPEx' has

unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[6].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[5].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[4].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[3].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[2].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[1].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Han dshakeSLV_Ackx/HBx/BlkOut.ODataFlop/GenFlops[0].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_Boucle_cadencE9e_14482/TimeLoopCoreFromRioClk40ToRioClk 40Derived5x1C00MHz/PersistEnableIn.TimedLoopDomainCrosserx/EnableInAndClr.Pul seSyncBoolx/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDC PE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.S yncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output

pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[7].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[8].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[9].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[16].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[17].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[18].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[19].DFlopx/FDCPEx' has

unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[33].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[34].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[35].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[36].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/BlkOut.oDataFlopx/GenFlops[37].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[22].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[23].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[24].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[25].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[26].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[27].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[28].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[29].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[30].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[31].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[32].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[33].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[34].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[35].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[36].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/BlkOut.o DataFlopx/GenFlops[37].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/BlkOut.Syn cOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzToInterface/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE _1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_bushold/ChinchClkShifter.ShiftRegister/SyncBusReset/Pul seSyncBasex/oLocalSigOutx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDom ainCrossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallin gEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit00/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive

'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit55/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit55/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit55/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit55/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit55/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 10].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 11].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 12].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 13].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 14].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/n_CustomArbForOutPortPortOnResFGPA_Globals_viBit66/Handsh akeSLVFromRioClk40ToIO_ModuleA_AGenClkBufRToLv/HBx/BlkOut.ODataFlop/GenFlops[ 15].DFlopx/FDCPEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/Clock DomainCrossing.BusClkToReliableClkHS/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDC PEx' has unconnected output pinWARNING:NgdBuild:440 - FF primitive 'Puma20Window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/Clock DomainCrossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFal lingEdgex/FDCPE_1x' has unconnected output pinWARNING:NgdBuild:452 - logical net 'aRsvdCtrl_OBUF' has no driver

WARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<31>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<30>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<29>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<28>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<27>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<26>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<25>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<24>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<23>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<22>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<21>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<20>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<19>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<18>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<17>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<16>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<15>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<14>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<13>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<12>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<11>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<10>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<9>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<8>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<7>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<6>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<5>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<4>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<3>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<2>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<1>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd0DdrDQ<0>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<31>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<30>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<29>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<28>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<27>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<26>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<25>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<24>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<23>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<22>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<21>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<20>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<19>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<18>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<17>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<16>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<15>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<14>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<13>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<12>' has no legal driver

WARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<11>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<10>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<9>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<8>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<7>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<6>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<5>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<4>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<3>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<2>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<1>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'd1DdrDQ<0>' has no legal driverWARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/pDisable" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/ChinchDmaComponentEnableChainx/pDisable" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopWithFlushEnableChain/Ha ndshakeTransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.SyncORe set/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomai n/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/BlkOverflow.HandshakeOverflow/BlkOut.SyncORe set/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeOverflowStopReques t/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDomai n/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeStateToBusClkDom ain/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.HandshakeUnderflowStopReq uest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/BlkUnderflow.HandshakeUnderflow/BlkOut.Syn cOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this

attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionTimeoutRequest/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/HandshakeFullCount/BlkOut.SyncOReset/c1Res etFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_Interface/IrqComponents[0].ChinchLvFpgaIrqx/HandshakeIr qNum/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<37>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<36>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<35>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<34>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<33>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<32>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<31>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<30>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<29>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<2>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<1>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzFromInterface/iLclStoredData<0>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<37>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<36>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<35>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<34>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<33>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<32>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<31>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<30>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<29>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<28>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<1>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40FromInterface/iLclStor edData<0>" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Crossing.RioClk40ToInterface/BlkOut.Syn cOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/n_bushold/RioClk40Derived5x1C00MHzCrossing.RioClk40Derive d5x1C00MHzToInterface/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDom ainCrossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20Window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/Clock DomainCrossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "PumaFixedLogicx/FixedRegsClkXingx/mFlatDataToRegHS/BlkOut.SyncOReset/c1Reset FastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "PumaFixedLogicx/FixedRegsClkXingx/I2cCrosser/BlkOut.SyncOReset/c1ResetFastLc l" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:483 - Attribute "INIT" on "Puma20IoPort2Gluex/FixedRegisterDataCross/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.WARNING:NgdBuild:470 - bidirect pad net 'aUserGpio<35>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'aUserGpio_n<44>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'aUserGpio_n<42>' has no legal driverWARNING:NgdBuild:470 - bidirect pad net 'aUserGpio_n<2>' has no legal driver



-------------------------------

NGDBUILD Design Results Summary:

Number of errors: 0 Number of warnings: 697

Writing NGD file "Puma20Top.ngd" ...Total REAL time to NGDBUILD completion: 2 min 51 secTotal CPU time to NGDBUILD completion: 1 min 32 sec

Writing NGDBUILD log file "Puma20Top.bld"...

NGDBUILD done.

Process "Translate" completed successfullyINFO:TclTasksC:1850 - process run : Translate is done.INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ADPRAM36K.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/AcquisitionEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/BuiltinFIFOCoreFPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchCommIfcArbiterBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentInputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentOutputStateHolder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStateTransitionEnableChain. vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaComponentStreamStateEnableChain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaInputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaOutputFifoInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSinkStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchDmaSourceStreamStateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchInterfaceDmaRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchIrqInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchLvFpgaIrq.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchRegisterAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ChinchSinkStream.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ClockGenXilinxV5.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CrossSwitchSourceSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForBit0_ctl_3RHFpgaReadPortOnResbush old.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForClear_T2H_DMA_Timeout_ctl_15RHFpg aReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Acq_Reset_ctl_18RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Gen_Reset_ctl_10RH FpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Program_Onboard_Cl ock_ctl_11RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForIO_Module_bksl_Xpoint_Switch_Writ e_ctl_0RHFpgaReadPortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForMiteIoLikePortOnResInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viAc q_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viBi t00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viCl ear_T2H_DMA_Timeout10.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viFe tch_Length9.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Acq_Reset12.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viIO _Module_bksl_Gen_Reset7.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForOutPortPortOnResFGPA_Globals_viSo ftware_Trigger8.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForSoftware_Trigger_ctl_12RHFpgaRead PortOnResbushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/CustomArbForTopEnablesPortOnResTopEnablePassT hru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlop.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopBoolFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopFallingEdge.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DFlopSlvResetVal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM32Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DPRAM64Bits.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Deserializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DiagramReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncAsyncInBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncBoolAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncSlAsyncIn.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSL.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/DoubleSyncWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viAcq_Regional_Clock_Loop11.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viBit00.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FGPA_Globals_viIO_Module_bksl_Acq_Reset12.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn0.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FPGAwFIFOn1.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FeedbackNonSctlCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoIO_ModuleA_AAcqClkBufRToLvFPGAwFIFOn0TopE nInIClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FifoPtrClockCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FloatingFeedbackGInit.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpDynamicShift.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpNormalize.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/FxpShiftCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/GenerationEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeBaseResetCross.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeSLV_Ack.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/HandshakeWithResetValueSLV.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cIssueCycle.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/I2cReadWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InStrmRAMArray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Interface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/InvisibleResholder.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/IoPort2LvFpga.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NI_FlexRIO_Helper_VIs_lvlib_colon_Rising_Edge _Detect_vi_co_2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587Base.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587ConnectorSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Ni6587CoreSerdes.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000001_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000003_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000005_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000018_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000001a_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0000.vhd

" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000029_CaseStructure_62.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000002c_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000043_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000045_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000049_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004b_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0002.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0003.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0004.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructureFrame_0005.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000004d_CaseStructure_149.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000059_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005a_SequenceFrame.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005d_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000005f_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000061_SequenceFrame.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_00000098_TimedLoopDiagram.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0000.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_0000009c_CaseStructureFrame_0001.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_FPGA_Generate_and_Acquire.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_178.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_179.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_180.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaAG_TimedLoopControllerContainer_181.vhd " into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbDelayer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbPowerOf2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbRW.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaArbSerializeAccess.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBoolOpNot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltInFifoResetControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaBuiltinFifoCounter.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaClockManagerControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaCtrlIndRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDiRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaDoWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoClearControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoCountControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPopBuffer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPortReset.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFifoPushPopControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaFlipFlopFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaGlobalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaHostAccessibleRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderRead.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLocalResHolderWrite.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaLvJoinNumbers.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPipelinedOrGateTreeSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaPulseSyncBaseWrapper.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegFrameworkShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaRegisterCoreBase.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaSelect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaShiftReg.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaStockDcm.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiFpgaTopEnInSyncForExternalClk.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFixedToFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatAddCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatSubtractCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixed.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFloatToFixedCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaClipContainer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalInput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFpgaStockDigitalOutput.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpAdd.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCoerce.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompare.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpCompareToZero.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpDecrement.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpEnableHandlerSlv.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvFxpSubtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFixedPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToFloatingPoint.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvToInteger.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Add.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Equal.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Greater.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32GreaterOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Less.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32LessOrEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32NotEqual.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/NiLvXipFloat32Subtract.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmDPRAM.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmFifoFlags.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/OutStrmOutputHandler.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PacketSink.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgADPRAM36KUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgByteArray.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgChinchConfig.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommIntConfiguration.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgCommunicationInterface.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDataPackingFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaFifos.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgDmaRegs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFloat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFpgaDeviceSpecs.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgFxpArithmetic.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgGray.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgInStrmFifoUtil.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgIoPort2.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgLvFpgaConst.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNi6587.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaBoolOp.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaFifo.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaIrqRegisters.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiFpgaViControlRegister.vhd" into library work

INFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiLvPrims.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgNiUtilities.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgOneHot.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgPuma20.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgRegister.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgStreamStates.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PkgSwitchedChinch.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBase.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/PulseSyncBool.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20ClkDetect.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20DramMain.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Puma20Top.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/RegionalClockBuf.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ResetSync.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SafeBusCrossing.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/Serializer.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamDataReceiver.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SinkStreamTcrUpdateController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/StrmArbiter.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/SubVICtlOrIndOpt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TheWindow.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopController.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopCore.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimedLoopDomainCrosser.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file

"C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimeoutManager.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TimingEngine.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/TopEnablePassThru.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViControl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ViSignature.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNode.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/XDataNodeOut.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/bushold.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_idelay_ctrl.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/ddr2_infrastructure.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/niInstr_Basic_Elements_v1_FPGA_lvlib_colon_Sy nchronous_Lat.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_r_opt.vhd" into library workINFO:HDLCompiler:1061 - Parsing VHDL file "C:/NIFPGA/jobs/vcnPe3C_D7RFefX/resholder_w_opt.vhd" into library workINFO:ProjectMgmt - Parsing design hierarchy completed successfully.WARNING:ProjectMgmt - Circular Reference: work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl

Started : "Map".Running map...Command Line: map -intstyle ise -p xc5vsx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr b -lc off -power off -o Puma20Top_map.ncd Puma20Top.ngd Puma20Top.pcfUsing target part "5vsx50tff1136-1".vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvINFO:Security:56 - Part 'xc5vsx50t' is not a WebPack part.WARNING:Security:9b - No 'ISE' feature version 2012.12 was available for part'xc5vsx50t'.WARNING:Security:42 - Your software subscription period has lapsed. Your currentversion of Xilinx tools will continue to function, but you no longer qualify forXilinx software updates or new releases.WARNING:Security:42 - Your software subscription period has lapsed. Your currentversion of Xilinx tools will continue to function, but you no longer qualify forXilinx software updates or new releases.----------------------------------------------------------------------Mapping design into LUTs...WARNING:MapLib:701 - Signal aSync100 connected to top level port aSync100 has been removed.WARNING:MapLib:701 - Signal aSync100_n connected to top level port aSync100_n has been removed.

WARNING:MapLib:701 - Signal aDSTARA connected to top level port aDSTARA has been removed.WARNING:MapLib:701 - Signal aDSTARA_n connected to top level port aDSTARA_n has been removed.WARNING:MapLib:701 - Signal aDSTARB connected to top level port aDSTARB has been removed.WARNING:MapLib:701 - Signal aDSTARB_n connected to top level port aDSTARB_n has been removed.WARNING:MapLib:701 - Signal d1DdrDQS<3> connected to top level port d1DdrDQS<3> has been removed.WARNING:MapLib:701 - Signal d1DdrDQS_n<3> connected to top level port d1DdrDQS_n<3> has been removed.WARNING:MapLib:701 - Signal d1DdrDQS<2> connected to top level port d1DdrDQS<2> has been removed.WARNING:MapLib:701 - Signal d1DdrDQS_n<2> connected to top level port d1DdrDQS_n<2> has been removed.WARNING:MapLib:701 - Signal d1DdrDQS<1> connected to top level port d1DdrDQS<1> has been removed.WARNING:MapLib:701 - Signal d1DdrDQS_n<1> connected to top level port d1DdrDQS_n<1> has been removed.WARNING:MapLib:701 - Signal d1DdrDQS<0> connected to top level port d1DdrDQS<0> has been removed.WARNING:MapLib:701 - Signal d1DdrDQS_n<0> connected to top level port d1DdrDQS_n<0> has been removed.WARNING:MapLib:701 - Signal d0DdrDQS<3> connected to top level port d0DdrDQS<3> has been removed.WARNING:MapLib:701 - Signal d0DdrDQS_n<3> connected to top level port d0DdrDQS_n<3> has been removed.WARNING:MapLib:701 - Signal d0DdrDQS<2> connected to top level port d0DdrDQS<2> has been removed.WARNING:MapLib:701 - Signal d0DdrDQS_n<2> connected to top level port d0DdrDQS_n<2> has been removed.WARNING:MapLib:701 - Signal d0DdrDQS<1> connected to top level port d0DdrDQS<1> has been removed.WARNING:MapLib:701 - Signal d0DdrDQS_n<1> connected to top level port d0DdrDQS_n<1> has been removed.WARNING:MapLib:701 - Signal d0DdrDQS<0> connected to top level port d0DdrDQS<0> has been removed.WARNING:MapLib:701 - Signal d0DdrDQS_n<0> connected to top level port d0DdrDQS_n<0> has been removed.WARNING:MapLib:701 - Signal UserGClkLvds connected to top level port UserGClkLvds has been removed.WARNING:MapLib:701 - Signal UserGClkLvds_n connected to top level port UserGClkLvds_n has been removed.WARNING:MapLib:701 - Signal UserGClkLvttl connected to top level port UserGClkLvttl has been removed.WARNING:MapLib:701 - Signal aUserGpio<38> connected to top level port aUserGpio<38> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<38> connected to top level port aUserGpio_n<38> has been removed.WARNING:MapLib:701 - Signal aVccoAmon connected to top level port aVccoAmon has been removed.

WARNING:MapLib:701 - Signal aVccoAmon_n connected to top level port aVccoAmon_n has been removed.WARNING:MapLib:701 - Signal aVccoBmon connected to top level port aVccoBmon has been removed.WARNING:MapLib:701 - Signal aVccoBmon_n connected to top level port aVccoBmon_n has been removed.WARNING:MapLib:701 - Signal aSysMonVn connected to top level port aSysMonVn has been removed.WARNING:MapLib:701 - Signal aSysMonVp connected to top level port aSysMonVp has been removed.WARNING:MapLib:701 - Signal aLvTrig<7> connected to top level port aLvTrig<7> has been removed.WARNING:MapLib:701 - Signal aLvTrig<6> connected to top level port aLvTrig<6> has been removed.WARNING:MapLib:701 - Signal aLvTrig<5> connected to top level port aLvTrig<5> has been removed.WARNING:MapLib:701 - Signal aLvTrig<4> connected to top level port aLvTrig<4> has been removed.WARNING:MapLib:701 - Signal aLvTrig<3> connected to top level port aLvTrig<3> has been removed.WARNING:MapLib:701 - Signal aLvTrig<2> connected to top level port aLvTrig<2> has been removed.WARNING:MapLib:701 - Signal aLvTrig<1> connected to top level port aLvTrig<1> has been removed.WARNING:MapLib:701 - Signal aLvTrig<0> connected to top level port aLvTrig<0> has been removed.WARNING:MapLib:701 - Signal aUserGpio<37> connected to top level port aUserGpio<37> has been removed.WARNING:MapLib:701 - Signal aUserGpio<34> connected to top level port aUserGpio<34> has been removed.WARNING:MapLib:701 - Signal aUserGpio<33> connected to top level port aUserGpio<33> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<37> connected to top level port aUserGpio_n<37> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<34> connected to top level port aUserGpio_n<34> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<33> connected to top level port aUserGpio_n<33> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<5> connected to top level port aUserGpio_n<5> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<12> connected to top level port d0DdrAddr<12> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<11> connected to top level port d0DdrAddr<11> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<10> connected to top level port d0DdrAddr<10> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<9> connected to top level port d0DdrAddr<9> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<8> connected to top level port d0DdrAddr<8> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<7> connected to top level port d0DdrAddr<7> has been removed.

WARNING:MapLib:701 - Signal d0DdrAddr<6> connected to top level port d0DdrAddr<6> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<5> connected to top level port d0DdrAddr<5> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<4> connected to top level port d0DdrAddr<4> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<3> connected to top level port d0DdrAddr<3> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<2> connected to top level port d0DdrAddr<2> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<1> connected to top level port d0DdrAddr<1> has been removed.WARNING:MapLib:701 - Signal d0DdrAddr<0> connected to top level port d0DdrAddr<0> has been removed.WARNING:MapLib:701 - Signal d0DdrDM<3> connected to top level port d0DdrDM<3> has been removed.WARNING:MapLib:701 - Signal d0DdrDM<2> connected to top level port d0DdrDM<2> has been removed.WARNING:MapLib:701 - Signal d0DdrDM<1> connected to top level port d0DdrDM<1> has been removed.WARNING:MapLib:701 - Signal d0DdrDM<0> connected to top level port d0DdrDM<0> has been removed.WARNING:MapLib:701 - Signal d0DdrCKE<0> connected to top level port d0DdrCKE<0> has been removed.WARNING:MapLib:701 - Signal d0DdrODT<1> connected to top level port d0DdrODT<1> has been removed.WARNING:MapLib:701 - Signal d0DdrODT<0> connected to top level port d0DdrODT<0> has been removed.WARNING:MapLib:701 - Signal d0DdrBankAddr<2> connected to top level port d0DdrBankAddr<2> has been removed.WARNING:MapLib:701 - Signal d0DdrBankAddr<1> connected to top level port d0DdrBankAddr<1> has been removed.WARNING:MapLib:701 - Signal d0DdrBankAddr<0> connected to top level port d0DdrBankAddr<0> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<12> connected to top level port d1DdrAddr<12> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<11> connected to top level port d1DdrAddr<11> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<10> connected to top level port d1DdrAddr<10> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<9> connected to top level port d1DdrAddr<9> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<8> connected to top level port d1DdrAddr<8> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<7> connected to top level port d1DdrAddr<7> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<6> connected to top level port d1DdrAddr<6> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<5> connected to top level port d1DdrAddr<5> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<4> connected to top level port d1DdrAddr<4> has been removed.

WARNING:MapLib:701 - Signal d1DdrAddr<3> connected to top level port d1DdrAddr<3> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<2> connected to top level port d1DdrAddr<2> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<1> connected to top level port d1DdrAddr<1> has been removed.WARNING:MapLib:701 - Signal d1DdrAddr<0> connected to top level port d1DdrAddr<0> has been removed.WARNING:MapLib:701 - Signal d1DdrDM<3> connected to top level port d1DdrDM<3> has been removed.WARNING:MapLib:701 - Signal d1DdrDM<2> connected to top level port d1DdrDM<2> has been removed.WARNING:MapLib:701 - Signal d1DdrDM<1> connected to top level port d1DdrDM<1> has been removed.WARNING:MapLib:701 - Signal d1DdrDM<0> connected to top level port d1DdrDM<0> has been removed.WARNING:MapLib:701 - Signal d1DdrCKE<0> connected to top level port d1DdrCKE<0> has been removed.WARNING:MapLib:701 - Signal d1DdrODT<1> connected to top level port d1DdrODT<1> has been removed.WARNING:MapLib:701 - Signal d1DdrODT<0> connected to top level port d1DdrODT<0> has been removed.WARNING:MapLib:701 - Signal d1DdrBankAddr<2> connected to top level port d1DdrBankAddr<2> has been removed.WARNING:MapLib:701 - Signal d1DdrBankAddr<1> connected to top level port d1DdrBankAddr<1> has been removed.WARNING:MapLib:701 - Signal d1DdrBankAddr<0> connected to top level port d1DdrBankAddr<0> has been removed.WARNING:MapLib:701 - Signal aRsvd<1> connected to top level port aRsvd<1> has been removed.WARNING:MapLib:701 - Signal aRsvd<0> connected to top level port aRsvd<0> has been removed.WARNING:MapLib:701 - Signal d0DdrRAS_n connected to top level port d0DdrRAS_n has been removed.WARNING:MapLib:701 - Signal d0DdrCAS_n connected to top level port d0DdrCAS_n has been removed.WARNING:MapLib:701 - Signal d0DdrWE_n connected to top level port d0DdrWE_n has been removed.WARNING:MapLib:701 - Signal d1DdrRAS_n connected to top level port d1DdrRAS_n has been removed.WARNING:MapLib:701 - Signal d1DdrCAS_n connected to top level port d1DdrCAS_n has been removed.WARNING:MapLib:701 - Signal d1DdrWE_n connected to top level port d1DdrWE_n has been removed.WARNING:MapLib:701 - Signal aRsvdCtrl connected to top level port aRsvdCtrl has been removed.WARNING:MapLib:701 - Signal aFPGA_1V_ModeCntrl connected to top level port aFPGA_1V_ModeCntrl has been removed.WARNING:MapLib:701 - Signal aUserGpio<65> connected to top level port aUserGpio<65> has been removed.WARNING:MapLib:701 - Signal aUserGpio<64> connected to top level port aUserGpio<64> has been removed.

WARNING:MapLib:701 - Signal aUserGpio<63> connected to top level port aUserGpio<63> has been removed.WARNING:MapLib:701 - Signal aUserGpio<62> connected to top level port aUserGpio<62> has been removed.WARNING:MapLib:701 - Signal aUserGpio<61> connected to top level port aUserGpio<61> has been removed.WARNING:MapLib:701 - Signal aUserGpio<60> connected to top level port aUserGpio<60> has been removed.WARNING:MapLib:701 - Signal aUserGpio<47> connected to top level port aUserGpio<47> has been removed.WARNING:MapLib:701 - Signal aUserGpio<45> connected to top level port aUserGpio<45> has been removed.WARNING:MapLib:701 - Signal aUserGpio<40> connected to top level port aUserGpio<40> has been removed.WARNING:MapLib:701 - Signal aUserGpio<39> connected to top level port aUserGpio<39> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<65> connected to top level port aUserGpio_n<65> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<64> connected to top level port aUserGpio_n<64> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<63> connected to top level port aUserGpio_n<63> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<62> connected to top level port aUserGpio_n<62> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<61> connected to top level port aUserGpio_n<61> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<60> connected to top level port aUserGpio_n<60> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<47> connected to top level port aUserGpio_n<47> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<45> connected to top level port aUserGpio_n<45> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<40> connected to top level port aUserGpio_n<40> has been removed.WARNING:MapLib:701 - Signal aUserGpio_n<39> connected to top level port aUserGpio_n<39> has been removed.WARNING:MapLib:41 - All members of TNM group "ClockIn" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "Strobe" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "PfiClk" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom328" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom308" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom463" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom464" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom481" have been optimized out of the design.

WARNING:MapLib:41 - All members of TNM group "TNM_Custom482" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom384" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom387" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom383" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom388" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom389" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom391" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom392" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom399" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom400" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom395" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom396" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom386" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom397" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom398" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom385" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom394" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom393" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom390" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom409" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom410" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom420" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom423" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom419" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom424" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom425" have been optimized out of the design.

WARNING:MapLib:41 - All members of TNM group "TNM_Custom869" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom211" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom212" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom215" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom214" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom210" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom204" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom203" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom206" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom202" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom208" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom201" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom199" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom229" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom230" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom248" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom200" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom218" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom278" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom260" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom259" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom168" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_Custom174" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "TNM_DramClk200s90" have been optimized out of the design.WARNING:MapLib:41 - All members of TNM group "Sync100Grp" have been optimized out of the design.WARNING:MapLib:39 - The timing specification "MAXDELAY=9899.0001 pS" on net "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn

put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/iIResetFast" has been discarded, because the net was optimized out of the design.WARNING:MapLib:39 - The timing specification "MAXDELAY=9899.0001 pS" on net "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/iIResetFast" has been discarded, because the net was optimized out of the design.WARNING:MapLib:39 - The timing specification "MAXDELAY=9899.0001 pS" on net "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StartEnableChain/HandshakeT ransitionTimeoutRequest/iIResetFast" has been discarded, because the net was optimized out of the design.WARNING:MapLib:39 - The timing specification "MAXDELAY=9899.0001 pS" on net "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaIn put.ChinchDmaInputFifoInterfacex/StreamStateBlock.StopEnableChain/HandshakeTr ansitionTimeoutRequest/iIResetFast" has been discarded, because the net was optimized out of the design.WARNING:MapLib:39 - The timing specification "MAXDELAY=49495.0005 pS" on net "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StopEnableChain/Handshake TransitionTimeoutRequest/iIResetFast" has been discarded, because the net was optimized out of the design.WARNING:MapLib:39 - The timing specification "MAXDELAY=49495.0005 pS" on net "Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOu tput.ChinchDmaOutputFifoInterfacex/StreamStateBlock.StartEnableChain/Handshak eTransitionTimeoutRequest/iIResetFast" has been discarded, because the net was optimized out of the design.WARNING:MapLib:50 - The period specification "TS_ClockIn" has been discarded because the group "ClockIn" has been optimized away.WARNING:MapLib:50 - The period specification "TS_Strobe" has been discarded because the group "Strobe" has been optimized away.WARNING:MapLib:50 - The period specification "TS_PfiClk" has been discarded because the group "PfiClk" has been optimized away.WARNING:MapLib:50 - The period specification "TS_DramClk200s90" has been discarded because the group "TNM_DramClk200s90" has been optimized away.WARNING:MapLib:48 - The timing specification "TS_CustomFromTo47" has been discarded because its TO group (TNM_Custom168) was optimized away.WARNING:MapLib:48 - The timing specification "TS_CustomFromTo50" has been discarded because its TO group (TNM_Custom174) was optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo62" has been discarded because both its FROM group (TNM_Custom199) and TO group (TNM_Custom200) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo63" has been discarded because both its FROM group (TNM_Custom201) and TO group (TNM_Custom202) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo64" has been discarded because both its FROM group (TNM_Custom203) and TO group (TNM_Custom204) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo65" has been discarded because both its FROM group (TNM_Custom202) and TO group (TNM_Custom206) were optimized away.

WARNING:MapLib:48 - The timing specification "TS_CustomFromTo66" has been discarded because its TO group (TNM_Custom208) was optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo67" has been discarded because both its FROM group (TNM_Custom204) and TO group (TNM_Custom210) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo68" has been discarded because both its FROM group (TNM_Custom211) and TO group (TNM_Custom212) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo70" has been discarded because both its FROM group (TNM_Custom215) and TO group (TNM_Custom214) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo77" has been discarded because both its FROM group (TNM_Custom229) and TO group (TNM_Custom230) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo92" has been discarded because both its FROM group (TNM_Custom259) and TO group (TNM_Custom260) were optimized away.WARNING:MapLib:48 - The timing specification "TS_CustomFromTo116" has been discarded because its TO group (TNM_Custom308) was optimized away.WARNING:MapLib:48 - The timing specification "TS_CustomFromTo126" has been discarded because its TO group (TNM_Custom328) was optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo154" has been discarded because both its FROM group (TNM_Custom383) and TO group (TNM_Custom384) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo155" has been discarded because both its FROM group (TNM_Custom385) and TO group (TNM_Custom386) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo156" has been discarded because both its FROM group (TNM_Custom387) and TO group (TNM_Custom388) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo157" has been discarded because both its FROM group (TNM_Custom389) and TO group (TNM_Custom390) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo158" has been discarded because both its FROM group (TNM_Custom391) and TO group (TNM_Custom392) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo159" has been discarded because both its FROM group (TNM_Custom393) and TO group (TNM_Custom394) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo160" has been discarded because both its FROM group (TNM_Custom395) and TO group (TNM_Custom396) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo161" has been discarded because both its FROM group (TNM_Custom397) and TO group (TNM_Custom398) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo162" has been discarded because both its FROM group (TNM_Custom399) and TO group (TNM_Custom400) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo167" has been discarded because both its FROM group (TNM_Custom409) and TO group (TNM_Custom410) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo172" has been

discarded because both its FROM group (TNM_Custom419) and TO group (TNM_Custom420) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo173" has been discarded because both its FROM group (TNM_Custom421) and TO group (TNM_Custom422) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo174" has been discarded because both its FROM group (TNM_Custom423) and TO group (TNM_Custom424) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo175" has been discarded because both its FROM group (TNM_Custom425) and TO group (TNM_Custom426) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo176" has been discarded because both its FROM group (TNM_Custom427) and TO group (TNM_Custom428) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo177" has been discarded because both its FROM group (TNM_Custom429) and TO group (TNM_Custom430) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo178" has been discarded because both its FROM group (TNM_Custom431) and TO group (TNM_Custom432) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo179" has been discarded because both its FROM group (TNM_Custom433) and TO group (TNM_Custom434) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo180" has been discarded because both its FROM group (TNM_Custom435) and TO group (TNM_Custom436) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo185" has been discarded because both its FROM group (TNM_Custom445) and TO group (TNM_Custom446) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo194" has been discarded because both its FROM group (TNM_Custom463) and TO group (TNM_Custom464) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo203" has been discarded because both its FROM group (TNM_Custom481) and TO group (TNM_Custom482) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo249" has been discarded because both its FROM group (TNM_Custom573) and TO group (TNM_Custom574) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo250" has been discarded because both its FROM group (TNM_Custom575) and TO group (TNM_Custom576) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo251" has been discarded because both its FROM group (TNM_Custom577) and TO group (TNM_Custom578) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo252" has been discarded because both its FROM group (TNM_Custom579) and TO group (TNM_Custom580) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo253" has been discarded because both its FROM group (TNM_Custom581) and TO group (TNM_Custom582) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo254" has been discarded because both its FROM group (TNM_Custom583) and TO group

(TNM_Custom584) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo255" has been discarded because both its FROM group (TNM_Custom585) and TO group (TNM_Custom586) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo256" has been discarded because both its FROM group (TNM_Custom587) and TO group (TNM_Custom588) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo257" has been discarded because both its FROM group (TNM_Custom589) and TO group (TNM_Custom590) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo262" has been discarded because both its FROM group (TNM_Custom599) and TO group (TNM_Custom600) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo267" has been discarded because both its FROM group (TNM_Custom609) and TO group (TNM_Custom610) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo268" has been discarded because both its FROM group (TNM_Custom611) and TO group (TNM_Custom612) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo269" has been discarded because both its FROM group (TNM_Custom613) and TO group (TNM_Custom614) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo270" has been discarded because both its FROM group (TNM_Custom615) and TO group (TNM_Custom616) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo271" has been discarded because both its FROM group (TNM_Custom617) and TO group (TNM_Custom618) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo272" has been discarded because both its FROM group (TNM_Custom619) and TO group (TNM_Custom620) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo273" has been discarded because both its FROM group (TNM_Custom621) and TO group (TNM_Custom622) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo274" has been discarded because both its FROM group (TNM_Custom623) and TO group (TNM_Custom624) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo275" has been discarded because both its FROM group (TNM_Custom625) and TO group (TNM_Custom626) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo280" has been discarded because both its FROM group (TNM_Custom635) and TO group (TNM_Custom636) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo289" has been discarded because both its FROM group (TNM_Custom653) and TO group (TNM_Custom654) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo298" has been discarded because both its FROM group (TNM_Custom671) and TO group (TNM_Custom672) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo330" has been discarded because both its FROM group (TNM_Custom735) and TO group (TNM_Custom736) were optimized away.

WARNING:MapLib:47 - The timing specification "TS_CustomFromTo353" has been discarded because both its FROM group (TNM_Custom781) and TO group (TNM_Custom782) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo354" has been discarded because both its FROM group (TNM_Custom783) and TO group (TNM_Custom784) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo355" has been discarded because both its FROM group (TNM_Custom785) and TO group (TNM_Custom786) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo356" has been discarded because both its FROM group (TNM_Custom787) and TO group (TNM_Custom788) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo357" has been discarded because both its FROM group (TNM_Custom789) and TO group (TNM_Custom790) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo358" has been discarded because both its FROM group (TNM_Custom791) and TO group (TNM_Custom792) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo359" has been discarded because both its FROM group (TNM_Custom793) and TO group (TNM_Custom794) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo360" has been discarded because both its FROM group (TNM_Custom795) and TO group (TNM_Custom796) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo361" has been discarded because both its FROM group (TNM_Custom797) and TO group (TNM_Custom798) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo366" has been discarded because both its FROM group (TNM_Custom807) and TO group (TNM_Custom808) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo371" has been discarded because both its FROM group (TNM_Custom817) and TO group (TNM_Custom818) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo372" has been discarded because both its FROM group (TNM_Custom819) and TO group (TNM_Custom820) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo373" has been discarded because both its FROM group (TNM_Custom821) and TO group (TNM_Custom822) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo374" has been discarded because both its FROM group (TNM_Custom823) and TO group (TNM_Custom824) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo375" has been discarded because both its FROM group (TNM_Custom825) and TO group (TNM_Custom826) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo376" has been discarded because both its FROM group (TNM_Custom827) and TO group (TNM_Custom828) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo377" has been discarded because both its FROM group (TNM_Custom829) and TO group (TNM_Custom830) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo378" has been

discarded because both its FROM group (TNM_Custom831) and TO group (TNM_Custom832) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo379" has been discarded because both its FROM group (TNM_Custom833) and TO group (TNM_Custom834) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo384" has been discarded because both its FROM group (TNM_Custom843) and TO group (TNM_Custom844) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo397" has been discarded because both its FROM group (TNM_Custom869) and TO group (TNM_Custom870) were optimized away.WARNING:MapLib:47 - The timing specification "TS_CustomFromTo399" has been discarded because both its FROM group (TNM_Custom873) and TO group (TNM_Custom872) were optimized away.WARNING:MapLib:52 - The offset specification "TIMEGRP Sync100Grp OFFSET=IN 2500 pS VALID 3000 pS BEFORE PxieClk100 RISING" has been discarded because its pad group (Sync100Grp) was optimized away.WARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKAU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKAU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKAL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKAL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKBU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKBU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKBL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKBL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge

nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKAU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKAU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKAL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKAL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKBU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKBU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKBL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[0].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKBL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKAU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKAU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKAL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKAL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKBU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge

nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKBU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKBL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[0].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKBL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKAU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKAU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKAL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKAL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKBU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKBU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst of frag REGCLKBL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[1].DmaInp ut.ChinchDmaInputFifoInterfacex/InStrmFifox/InStrmRAMArray_inst/GenRows[0].Ge nMultBRAMS[1].ADPRAM36K_inst/BRamIs36.RAMB36_inst_REGCLKBL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/LSW/ADPRAM36Kx/BRamIs36.RAMB36_inst of frag REGCLKAU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/LSW/ADPRAM36Kx/BRamIs36.RAMB36_inst_REGCLKAU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams.

SmallAsymBram.SmallDPRAM/LSW/ADPRAM36Kx/BRamIs36.RAMB36_inst of frag REGCLKAL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/LSW/ADPRAM36Kx/BRamIs36.RAMB36_inst_REGCLKAL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/LSW/ADPRAM36Kx/BRamIs36.RAMB36_inst of frag REGCLKBU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/LSW/ADPRAM36Kx/BRamIs36.RAMB36_inst_REGCLKBU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/LSW/ADPRAM36Kx/BRamIs36.RAMB36_inst of frag REGCLKBL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/LSW/ADPRAM36Kx/BRamIs36.RAMB36_inst_REGCLKBL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/MSW/ADPRAM36Kx/BRamIs36.RAMB36_inst of frag REGCLKAU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/MSW/ADPRAM36Kx/BRamIs36.RAMB36_inst_REGCLKAU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/MSW/ADPRAM36Kx/BRamIs36.RAMB36_inst of frag REGCLKAL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/MSW/ADPRAM36Kx/BRamIs36.RAMB36_inst_REGCLKAL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/MSW/ADPRAM36Kx/BRamIs36.RAMB36_inst of frag REGCLKBU connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/MSW/ADPRAM36Kx/BRamIs36.RAMB36_inst_REGCLKBU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams. SmallAsymBram.SmallDPRAM/MSW/ADPRAM36Kx/BRamIs36.RAMB36_inst of frag REGCLKBL connected to power/ground net Puma20Window/theVI/n_Interface/ChinchDmaFifosx/DmaBlk.DmaComponents[2].DmaOut put.ChinchDmaOutputFifoInterfacex/OutStrmFifox/OutStrmDPRAMx/AsymmetricBrams.

SmallAsymBram.SmallDPRAM/MSW/ADPRAM36Kx/BRamIs36.RAMB36_inst_REGCLKBL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin IoPort2Wrapperx/IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/DualPort RAMx/InferredRamx/Mram_iRAM of frag RDRCLKU connected to power/ground net IoPort2Wrapperx/IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/DualPort RAMx/InferredRamx/Mram_iRAM_RDRCLKU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin IoPort2Wrapperx/IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/DualPort RAMx/InferredRamx/Mram_iRAM of frag RDRCLKL connected to power/ground net IoPort2Wrapperx/IoPort2x/IoPort2Basex/ReceiveSide.IoReceiveFifoBasex/DualPort RAMx/InferredRamx/Mram_iRAM_RDRCLKL_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin IoPort2Wrapperx/IoPort2x/IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFi fo.InputFifo.DualPortRAMx/InferredRamx/Mram_iRAM of frag RDRCLKU connected to power/ground net IoPort2Wrapperx/IoPort2x/IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFi fo.InputFifo.DualPortRAMx/InferredRamx/Mram_iRAM_RDRCLKU_tiesigWARNING:Pack:2874 - Trimming timing constraints from pin IoPort2Wrapperx/IoPort2x/IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFi fo.InputFifo.DualPortRAMx/InferredRamx/Mram_iRAM of frag RDRCLKL connected to power/ground net IoPort2Wrapperx/IoPort2x/IoPort2Basex/TransmitSide.IoTransmitFifox/TransmitFi fo.InputFifo.DualPortRAMx/InferredRamx/Mram_iRAM_RDRCLKL_tiesigRunning directed packing...WARNING:Pack:2549 - The register "PumaFixedLogicx/PumaSpiMgrx/SpiControllerx/mSpiClk" has the property IOB=TRUE, but was not packed into the OLOGIC component. The output signal for register symbol PumaFixedLogicx/PumaSpiMgrx/SpiControllerx/mSpiClk requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.WARNING:Pack:2549 - The register "PumaFixedLogicx/PumaSpiMgrx/SpiControllerx/mSpiClk" has the property IOB=TRUE, but was not packed into the OLOGIC component. The output signal for register symbol PumaFixedLogicx/PumaSpiMgrx/SpiControllerx/mSpiClk requires general routing to fabric, but the register can only be routed to ILOGIC, IODELAY, and IOB.WARNING:Pack:2780 - The register "PumaFixedLogicx/PumaSpiMgrx/SpiControllerx/mSpiClkRising" has the property IOB=TRUE, but it did not join an IO component because it is not connected to any IO element.WARNING:Pack:2780 - The register "PumaFixedLogicx/PumaSpiMgrx/SpiControllerx/mSpiClkCount_0" has the property IOB=TRUE, but it did not join an IO component because it is not connected to any IO element.WARNING:Pack:2780 - The register "PumaFixedLogicx/PumaSpiMgrx/SpiControllerx/mSpiClkCount_1" has the property IOB=TRUE, but it did not join an IO component because it is not connected to any IO element.Running delay-based LUT packing...Updating timing models...

WARNING:Timing:3223 - Timing constraint TS_SampleValue = MAXDELAY FROM TIMEGRP "FFS" TO TIMEGRP "FFS(PXIe100ClkDetect/pSampleValue)" 10 ns ignored during timing analysis.INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp).Running timing-driven placement...Total REAL time at the beginning of Placer: 1 mins 4 secs Total CPU time at the beginning of Placer: 39 secs

Phase 1.1 Initial Placement AnalysisPhase 1.1 Initial Placement Analysis (Checksum:eacdb088) REAL time: 1 mins 7 secs

Phase 2.7 Design Feasibility CheckWARNING:Place:838 - An IO Bus with more than one IO standard is found. Components associated with this bus are as follows: Comp: aUserGpio<0> IOSTANDARD = LVDS_25 Comp: aUserGpio<1> IOSTANDARD = LVCMOS25 Comp: aUserGpio<2> IOSTANDARD = LVCMOS25 Comp: aUserGpio<3> IOSTANDARD = LVCMOS25 Comp: aUserGpio<4> IOSTANDARD = LVCMOS25 Comp: aUserGpio<5> IOSTANDARD = LVCMOS25 Comp: aUserGpio<6> IOSTANDARD = LVCMOS25 Comp: aUserGpio<7> IOSTANDARD = LVCMOS25 Comp: aUserGpio<8> IOSTANDARD = LVCMOS25 Comp: aUserGpio<9> IOSTANDARD = LVCMOS25 Comp: aUserGpio<10> IOSTANDARD = LVCMOS25 Comp: aUserGpio<11> IOSTANDARD = LVCMOS25 Comp: aUserGpio<12> IOSTANDARD = LVCMOS25 Comp: aUserGpio<13> IOSTANDARD = LVCMOS25 Comp: aUserGpio<14> IOSTANDARD = LVCMOS25 Comp: aUserGpio<15> IOSTANDARD = LVCMOS25 Comp: aUserGpio<16> IOSTANDARD = LVDS_25 Comp: aUserGpio<17> IOSTANDARD = LVDS_25 Comp: aUserGpio<18> IOSTANDARD = LVDS_25 Comp: aUserGpio<19> IOSTANDARD = LVDS_25 Comp: aUserGpio<20> IOSTANDARD = LVDS_25 Comp: aUserGpio<21> IOSTANDARD = LVDS_25 Comp: aUserGpio<22> IOSTANDARD = LVDS_25 Comp: aUserGpio<23> IOSTANDARD = LVDS_25 Comp: aUserGpio<24> IOSTANDARD = LVDS_25 Comp: aUserGpio<25> IOSTANDARD = LVDS_25 Comp: aUserGpio<26> IOSTANDARD = LVDS_25 Comp: aUserGpio<27> IOSTANDARD = LVDS_25 Comp: aUserGpio<28> IOSTANDARD = LVDS_25 Comp: aUserGpio<29> IOSTANDARD = LVDS_25 Comp: aUserGpio<30> IOSTANDARD = LVDS_25 Comp: aUserGpio<31> IOSTANDARD = LVDS_25 Comp: aUserGpio<32> IOSTANDARD = LVDS_25 Comp: aUserGpio<35> IOSTANDARD = LVCMOS25 Comp: aUserGpio<36> IOSTANDARD = LVDS_25 Comp: aUserGpio<41> IOSTANDARD = LVDS_25 Comp: aUserGpio<42> IOSTANDARD = LVCMOS25

Comp: aUserGpio<43> IOSTANDARD = LVDS_25 Comp: aUserGpio<44> IOSTANDARD = LVCMOS25 Comp: aUserGpio<46> IOSTANDARD = LVDS_25 Comp: aUserGpio<48> IOSTANDARD = LVDS_25 Comp: aUserGpio<49> IOSTANDARD = LVDS_25 Comp: aUserGpio<50> IOSTANDARD = LVDS_25 Comp: aUserGpio<51> IOSTANDARD = LVDS_25 Comp: aUserGpio<52> IOSTANDARD = LVDS_25 Comp: aUserGpio<53> IOSTANDARD = LVDS_25 Comp: aUserGpio<54> IOSTANDARD = LVDS_25 Comp: aUserGpio<55> IOSTANDARD = LVDS_25 Comp: aUserGpio<56> IOSTANDARD = LVDS_25 Comp: aUserGpio<57> IOSTANDARD = LVDS_25 Comp: aUserGpio<58> IOSTANDARD = LVDS_25 Comp: aUserGpio<59> IOSTANDARD = LVDS_25

WARNING:Place:838 - An IO Bus with more than one IO standard is found. Components associated with this bus are as follows: Comp: aUserGpio_n<0> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<1> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<2> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<3> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<4> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<6> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<7> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<8> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<9> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<10> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<11> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<12> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<13> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<14> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<15> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<16> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<17> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<18> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<19> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<20> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<21> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<22> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<23> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<24> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<25> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<26> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<27> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<28> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<29> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<30> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<31> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<32> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<35> IOSTANDARD = LVCMOS25

Comp: aUserGpio_n<36> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<41> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<42> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<43> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<44> IOSTANDARD = LVCMOS25 Comp: aUserGpio_n<46> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<48> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<49> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<50> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<51> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<52> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<53> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<54> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<55> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<56> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<57> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<58> IOSTANDARD = LVDS_25 Comp: aUserGpio_n<59> IOSTANDARD = LVDS_25

Phase 2.7 Design Feasibility Check (Checksum:eacdb088) REAL time: 1 mins 8 secs

Phase 3.31 Local Placement OptimizationPhase 3.31 Local Placement Optimization (Checksum:a5d03411) REAL time: 1 mins 8 secs




Phase 7.2 Initial Clock and IO Placement

ERROR:Place:906 - Components driven by IO clock net <Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenClkBufIo> can't be placed and routed because location constraints are causing the clock region rules to be violated. IO Clock net <Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenClkBufIo> is being driven by BUFIO <Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/TimingEnginex/GenClo ckBuffers/DataClkInBufIO> locked to site "BUFIO_X0Y11" Because of this location contraint, <Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenClkBufIo> can only drive clock region "CLOCKREGION_X0Y2". The following components driven by <Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenClkBufIo> have been locked to sites outside of these clock regions: Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[0].MasterOserdes (Locked Site: OLOGIC_X0Y133 CLOCKREGION_X0Y3) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat

aSer/SerialGen[1].SlaveOserdes (Locked Site: OLOGIC_X0Y144 CLOCKREGION_X0Y3) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[4].MasterOserdes (Locked Site: OLOGIC_X0Y115 CLOCKREGION_X0Y2) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[9].SlaveOserdes (Locked Site: OLOGIC_X0Y104 CLOCKREGION_X0Y2) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[8].MasterOserdes (Locked Site: OLOGIC_X0Y113 CLOCKREGION_X0Y2) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[6].SlaveOserdes (Locked Site: OLOGIC_X0Y96 CLOCKREGION_X0Y2) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[1].MasterOserdes (Locked Site: OLOGIC_X0Y145 CLOCKREGION_X0Y3) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[3].SlaveOserdes (Locked Site: OLOGIC_X0Y158 CLOCKREGION_X0Y3) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[5].MasterOserdes (Locked Site: OLOGIC_X0Y107 CLOCKREGION_X0Y2) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[0].SlaveOserdes (Locked Site: OLOGIC_X0Y132 CLOCKREGION_X0Y3) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[9].MasterOserdes (Locked Site: OLOGIC_X0Y105 CLOCKREGION_X0Y2) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[8].SlaveOserdes (Locked Site: OLOGIC_X0Y112 CLOCKREGION_X0Y2) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[2].MasterOserdes (Locked Site: OLOGIC_X0Y155 CLOCKREGION_X0Y3) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[5].SlaveOserdes (Locked Site: OLOGIC_X0Y106 CLOCKREGION_X0Y2) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[6].MasterOserdes (Locked Site: OLOGIC_X0Y97 CLOCKREGION_X0Y2) Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[2].SlaveOserdes (Locked Site: OLOGIC_X0Y154 CLOCKREGION_X0Y3)INFO:TclTasksC:1850 - process run : Map is done. Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenerationEnginex/Dat aSer/SerialGen[3].MasterOserdes (Locked Site: OLOGIC_X0Y159 CLOCKREGION_X0Y3) Please evaluate the location constraints of both the BUFIO and the components driven by <Puma20Window/theCLIPs/IO_Module_CLIP0/Ni6587CoreSerdesx/GenClkBufIo> to ensure that they follow the clock region rules of the architecture. For more information on the clock region rules, please refer to the architecture user's guide. To debug your design with partially routed design, please allow mapper/placer to finish the execution (by setting environment variable XIL_PAR_DEBUG_IOCLKPLACER to 1).

Phase 7.2 Initial Clock and IO Placement (Checksum:dec8a28a) REAL time: 1 mins 32 secs

Total REAL time to Placer completion: 1 mins 32 secs Total CPU time to Placer completion: 1 mins 6 secs ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Mapping completed.See MAP report file "Puma20Top_map.mrp" for details.Problem encountered during the packing phase.

Design Summary

--------------Number of errors : 2Number of warnings : 415

Process "Map" failed

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