Xilinx CPLDs and FPGAs

Module F2-1

CPLDs and FPGAsXC9500 CPLDXC4000 FPGASpartan FPGASpartan II FPGAVirtex FPGA

XC9500 CPLDs5 volt in-system programmable (ISP) CPLDs5 ns pin-to-pin36 to 288 macrocells (6400 gates) Industry’s best pin-locking architecture10,000 program/erase cyclesComplete IEEE 1149.1 JTAG capability

FunctionBlock 1

JTAGController

FunctionBlock 2

I/O

FunctionBlock 4

3

Global Tri-

States 2 or 4

FunctionBlock 3

I/O

In-SystemProgramming Controller

FastCONNECTSwitch Matrix

JTAG Port3

I/O

I/O

Global Set/Reset

Global Clocks

I/OBlocks

1

XC9500 Function Block

ToFastCONNECT

FromFastCONNECT

2 or 43 GlobalTri-State

GlobalClocks

I/O

I/O

36

Product-Term

Allocator

Macrocell 1

ANDArray

Macrocell 18

Each function block is like a 36V18 !

XC9500 Product Family9536

Macrocells

Usable Gates

tPD (ns)

Registers

Max I/O

36 72 108 144 216

800 1600 2400 3200 4800

5 7.5 7.5 7.5 10

36 72 108 144 216

34 72 108 133 166

Packages VQ44PC44 PC44

PC84TQ100PQ100

PC84TQ100PQ100PQ160

PQ100PQ160

288

6400

10

288

192

HQ208BG352

PQ160HQ208BG352

9572 95108 95144 95216 95288

CPLDs and FPGAsXC9500 CPLDXC4000 FPGASpartan FPGASpartan II FPGAVirtex FPGA

XC4000 ArchitectureCLB

CLB

CLB

CLB

SwitchMatrix

ProgrammableInterconnect I/O Blocks (IOBs)

ConfigurableLogic Blocks (CLBs)

D Q

SlewRate

Control

PassivePull-Up,

Pull-Down

Delay

Vcc

OutputBuffer

InputBuffer

Q D

Pad

D QSD

RDEC

S/RControl

D QSD

RDEC

S/RControl

1

1

F'G'

H'

DIN

F'G'

H'

DIN

F'

G'H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

Y

X

H1 DIN S/R EC

XC4000E/X Configurable Logic Blocks

D QSD

RDEC

S/RControl

D QSD

RDEC

S/RControl

1

1

F'G'

H'

DIN

F'G'

H'

DIN

F'

G'H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

YQ

Y

XQ

X

H1 DIN S/R EC

2 Four-input function generators (Look Up Tables)- 16x1 RAM or Logic function2 Registers- Each can be configured as Flip Flop or Latch- Independent clock polarity- Synchronous and asynchronous Set/Reset

D Q

SD

RD

EC

S/RControl

D Q

SD

RD

EC

S/RControl

1

1

F'G'

H'

DIN

F'

G'

H'

DIN

F'

G'

H'

H'

HFunc.Gen.

GFunc.Gen.

FFunc.Gen.

G4G3G2G1

F4F3F2F1

C4C1 C2 C3

K

YQ

Y

XQ

X

H1 DIN S/R EC

XC4000 CLB

Look Up Tables

Capacity is limited by number of inputs, not complexity

Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM

Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLBExample:

A B C D Z0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 10 1 0 1 1 . . .1 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

Look Up Table

Combinatorial LogicAB

CD

Z

4-bit address

GFunc.Gen.

G4G3G2G1

WE

2(2 )4

= 64K !

XC4000X I/O Block Diagram

Shaded areas are not included in XC4000E family.

Xilinx FPGA Routing1) Fast Direct Interconnect - CLB to CLB2) General Purpose Interconnect - Uses switch matrix

CLB

CLB

CLB

CLB

SwitchMatrix

SwitchMatrix

3) Long LinesSegmented across chipGlobal clocks, lowest skew2 Tri-states per CLB for busses

Other routing types in CPLDs and XC6200

Other FPGA ResourcesTri-state buffers for busses (BUFT’s)Global clock & high speed buffers (BUFG’s)Wide Decoders (DECODEx)Internal Oscillator (OSC4)Global Reset to all Flip-Flops, Latches (STARTUP)CLB special resources

Fast Carry logic built into CLBsSynchronous Dual Port RAMBoundary Scan

What’s Really In that Chip?

CLB(Red)

Switch Matrix

Long Lines(Purple)

Direct Interconnect (Green)

Routed Wires (Blue)Programmable Interconnect Points, PIPs (White)

Xilinx XC4000E FPGAs

CPLDs and FPGAsXC9500 CPLDXC4000 FPGASpartan FPGASpartan II FPGAVirtex FPGA

Xilinx Spartan FPGAs

CPLDs and FPGAsXC9500 CPLDXC4000 FPGASpartan FPGASpartan II FPGAVirtex FPGA

Xilinx Spartan-II FPGAs

Block RAM

Delay-Locked Loop

Phase-Locked Loop

CPLDs and FPGAsXC9500 CPLDXC4000 FPGASpartan FPGASpartan II FPGAVirtex FPGA

Virtex FPGAs

Virtex-II FPGAs

Virtex-II Pro FPGAs