Xilinx academy 02-99 RWW Xilinx Confidential HardWire TM Products: FPGA cost reduction made simple...
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Transcript of Xilinx academy 02-99 RWW Xilinx Confidential HardWire TM Products: FPGA cost reduction made simple...
Xilinx academy 02-99 RWW Xilinx Confidential
HardWireTM Products:FPGA cost reduction made simple
FPGA HardWire
CORES
Xilinx academy 02-99 RWW Xilinx Confidential
Objectives
At the conclusion of the presentation attendees
should understand the following:
HardWire definition and mission
FPGA/HardWire relationship
HardWire value to customers
FPGA and ASIC vendors competitive offerings
Basic selling strategy
Xilinx academy 02-99 RWW Xilinx Confidential
Defining HardWire
Products— Three generations of technology leadership
History— Success in the market
Philosophy— The mission of HardWire
Service— Focus on customer satisfaction
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Definition
HardWire products are silicon and software products developed with four goals
Provide FPGA emulation using ASIC technology
Use turnkey development based on FPGA design database
Offer FPGA cost reduction
Provide resource reduction vs traditional ASIC re-design
Xilinx academy 02-99 RWW Xilinx Confidential
The Xilinx Advantage“Design-Once”
Fast Development Time-to-Market Concurrent Engineering Flexibility
No Customer Re-design No Customer Vectors FPGA Features Significant cost reduction
HardWire
ConversionFPGADesign
HardWireASICHardWire
Fastest Time from Design Concept to Low-cost Silicon
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Methodology“Design Once”
Xilinx
ATPXilinx
ATP
Prototypes Prototypes
Test
Development
Test
Development
VerificationVerification
Place and RoutePlace and Route
VerificationVerification
CaptureCapture
Typical ASIC Design Phases
FPGA
Design
Xilinx HardWire Methodology
Production ReadyPrototypesProduction Ready
Prototypes
Physical Data BasePhysical Data Base
Iterations
Gate ArrayRedesign Path
Physical Data Base Conversion
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Technology Roadmap
FPGA transition productHW focus on Virtex
HW1 HW2 XH3 XH3L XH4
Customlayers
1 4 6 6 TBD
FPGA XC2K,3K,4K XC4KE,EX,XL,XC5200
XC4KE,EX XC4KXL,XLA Virtex
Process 1.0 -.8 .6 -.45 .5 .35 TBD
Voltage 5v/3.3v 5v/3.3v 5v 3.3v 2.5v
Value TAT Cost FPGAfeatures
FPGAfeatures
Cost,features
Status Obsolete Production Production OFB 2H99 Design
Xilinx academy 02-99 RWW Xilinx Confidential
Xilinx Has Seven Years of FPGA Conversion Experience with HardWire
Over 800 Xilinx FPGA’s Converted
Over 6 Million Devices Shipped
>90% first-time-right Prototypes
Experience with Complex Designs— PCI, RAM, Configuration emulation (CE), JTAG
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Mission
That is superior to traditional ASICs
a. reduced customer resource b. reduced customer risk
by linking to Xilinx FPGAs
c. reduced “Time-to-Volume” production
Provide Customers with a CostEffective Logic Solution
Extend FPGA Leadership
Xilinx academy 02-99 RWW Xilinx Confidential
Vice Presiden t & G ene ra l M anagerC lay Johnson
Adm in . A ssistan tL inda Sm ith
So ftw a reICLayout
D esign C ente r M anagerN igel H erron
SW M ethodo logy
R &D ManagerTBD
D irecto r o f Enginee ringS tephen D oug lass
P ETE
Product Eng inee ringM anager
D ocumen ta tionEng inee ring
Supe rvisorP ro to type Team
N ew Product &Pro to type P lann ing
M anagerProduct Eng inee ring and Opera tions
D on Pecko
Product Manage rsR ob Sch reckR onald W indomProg ram M anagerC aro lyn W ad ley
M anagerM arke ting
She lly D avis
M arketing M anagerH ow ard Bog row
P ETech
PE and Opera tions M anager
D irectorH i-R el
R ick Padovan i
HardWire is Organized for Customer Support
Xilinx academy 02-99 RWW Xilinx Confidential
The FPGA/ HardWire relationship
Xilinx Strategy— Lead the industry with features,density and cost
HardWire is Key— 4K FPGAs + HW bridge the ASIC gap
The FPGA/ ASIC battle— Design once, sell twice
Customer Product Lifecycles— Good intentions vs reality
Xilinx academy 02-99 RWW Xilinx Confidential
Xilinx Product Focus FPGA Family HardWire Comments
Not planned No price advantagegoing to HardWire
HW2,XH3,XH3L HardWire Supports4KE/EX/XL/XLA and5200
Not planned Technologydevelopment focussedon Virtex
In development Architecturedevelopment inprocess
Xilinx academy 02-99 RWW Xilinx Confidential
Market Strategy: Strategic FPGA Support
Strategically support XC4KE/EX/XL FPGA cost reduction requirements
Win higher volume FPGA opportunities
Lessen ASIC competitive threat to FPGA sales
Use as “strategic differentiator” vs. FPGA vendors
Create incremental revenue at target accounts
Xilinx academy 02-99 RWW Xilinx Confidential
Product Strategy: FPGA Emulation
Emulate the FPGA using ASIC technology
Support all FPGA features possible per family
Provide substantial price reduction over FPGA
Reduce Customer Re-Design Requirements
Create Customer Time-To-Volume Advantage
Provide a Viable Alternative to ASIC Development
Xilinx academy 02-99 RWW Xilinx Confidential
Sales Strategy: Sales and Service Tool This product is a strategic sales tool
— Defense: protect existing sockets— Offense: lock down cost sensitive wins
Offer as a “service” where appropriate
Position capabilities and limitations
Differentiate from ASIC design or FPGA netlist “re-design”
Distinguish “FPGA cost reduction” from “ASIC price competitor”
Xilinx academy 02-99 RWW Xilinx Confidential
Den
sity
Volume1KU 10KU 100KU 1000K
XC4KXL/A
(XC4036XL/A)
(XC4020XL/A)
XC4KXL /A + HardWireSweet SpotXC4KXL/A +
HardWirestrategic
Use HardWire to Support XC4XL/A:Density and volume are keys
(XC4085XL/A)
XC4KXL/A+ HardWireOpportunistic
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Product Roadmap
* 1st Production submittals
FPGANOWHW2
NOWXH3
3Q99 *XH3L
TBDXH4
E/ EX(5V) X
XL(3.3V) X X
XV
Virtex TBD
FPGA transition productHW focus on Virtex
Xilinx academy 02-99 RWW Xilinx Confidential
Xilinx FPGA + HardWire Advantage“Design Once”
Logic Design
FPGA
HardWireASIC
“Make”Non-Turn-key“Buy”
Turn-Key
Unique Xilinx Logic Methodology
Xilinx academy 02-99 RWW Xilinx Confidential
Typical Product Life Cycle ModelV
OL
UM
E
PRODUCTIONRAMP-UP
UNPLANNED UPSIDE
END-OF-LIFE
PROGRAMMABLE VOLUME
HardWire Device
Design and prototype with FPGA
Production ramp in FPGA during HW conversion
FPGA for production upsides and system E-O-L
Xilinx academy 02-99 RWW Xilinx Confidential
FPGA PROTOTYPE
Customer’s Plan is Different
END-OF-LIFE
HardWire Device
Most customers use the model below
The problem with this model is:— Always redesign— Production never ramps this fast!
PRODUCTION RAMP IN ASIC ORHARDWIRE
Xilinx academy 02-99 RWW Xilinx Confidential
Real Product Life Cycle The Value of FPGA + HardWire
Redesign flexibility with FPGA Initial production with FPGA Convert to HardWire when code is stable
VOLUME
END-OF-LIFE
HardWire Device
PROTOTYPE &SYSTEMVERIFICATION
REDESIGNWITH OFF-THESHELF FPGA
UNPLANNED UPSIDE
PRODUCT FAILS
PRODUCTIONRAMP WITHFPGA
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire’s Value to Customers
HardWire’s value proposition— There’s more to value than just product cost
The methodology— DesignLock: The key to HardWire
The technology— Drop-in replacement for FPGAs
Leveling the field vs ASICs— Differentiating HardWire vs ASICs
Xilinx academy 02-99 RWW Xilinx Confidential
Customer Benefit HardWire Value
Risk Reduction DesignLock
Resource Reduction Turnkey development
Total Cost Reduction Small die size (HW2/ XH3/L)
Project Time-to-VolumeReduction
FPGA + HardWirecombination
HardWire Value Proposition
Xilinx academy 02-99 RWW Xilinx Confidential
XilinxHolds the Patenton FPGAConversionWithoutRe-Design
Xilinx academy 02-99 RWW Xilinx Confidential
DesignLocktm Mapping Preserves CLB Relative Position
CLBPlacementPreserved
ASIC Place and Route Algorithms Use Best Random
Case for Overall Fit
FPGA
HardWire Device
ASIC
Xilinx academy 02-99 RWW Xilinx Confidential
DesignLocktm Minimizes Routing Change
FPGA Device Routing
Generic ASIC Routing Can Change Critical Paths
DesignLocktm Preserves Routing and Relative Timing
Xilinx academy 02-99 RWW Xilinx Confidential
DesignLock™Feature Customer BenefitLogic preserved No design verification
Routing preserved No timing simulation
Scan logic inserted No test vectors required
DesignLocktm Reduces Customer Resources
Xilinx academy 02-99 RWW Xilinx ConfidentialN
etlist Translation to A
SIC Library
Design Verification
Fix Logic Errors
Place and Route
Timing Sim
ulation
Fix Timing Errors
Write Test Vectors
Build Prototypes
Test Prototypes
Build Production U
nits
As N
eeded: Problem
solving Logic re-design, verification, sim
ulation
Design
Entry
Customer
ASIC Vendor
In an ASIC Conversion The Customer Does the Work
Xilinx academy 02-99 RWW Xilinx Confidential
Customer
Xilinx
HardWire Product Development is TurnkeyWe do the work so the customer doesn’t have to
Customer reviews reports and tests prototypes.Conversion work and test development done by Xilinx.Conversion to a generic ASIC requires more work by the customer.
Design Entry
Design C
onversion
Scan logic insertion
Place and Route
Generate final
conversion report
Review
preliminary
conversion report
Build Prototypes
Test Prototypes
Build Production U
nits
CE Integration
JTAG
Integration
Simulation
LVS/ DR
C
RA
M Integration
Review
final conversion report
Xilinx academy 02-99 RWW Xilinx Confidential
FPGA Features Built Into XH3/L
FpgASIC I/O Uses
FPGA JTAG:No change
to test program
FPGA I/O(Driver, ESD,
5V Tolerant)
FPGA Features
Efficient Hi-PerformanceASIC Core PAD
OSC
POR,CE
VREF,CLKS
Core
Cor
e
FPGA Cores
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Advantage Customer Benefit
DesignLock™ No verification/simulation Same I/O as FPGA Same start-up timing Same RAM as FPGA No test vectors to write
XH3/L Architecture FPGA Compatibility
Turn-key Conversion No customer resources
HardWire Differentiation versus ASIC
Xilinx academy 02-99 RWW Xilinx Confidential
Competition: Imitation is the greatest form of flattery
FPGA vendors— Altera MPLD: Convert only if we have to— Lucent: MACO is O.K., but you really want an ASIC
ASIC vendors— AMI: Jack of all conversions master of none— Orbit: If at first you don’t succeed, lower the price— Temic: Are we back in the conversion business?— NEC,Toshiba,etc.: FPGA conversion worth the effort?
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Competition: Altera
MPLD becoming a focus product line Minimal resources currently dedicated Focussed on Max 8K and 10K designs Strategic opportunities only Lower FPGA price to compete with HardWire
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Competition: Lucent MACO
HardWire’s #1 customer Limited internal customer focus Resources dominated by ASIC business request Move major accounts to ASIC products Customer resource intensive conversion Orca + ASIC vs Xilinx FPGA+HardWire
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Competition: Atmel
Focus on ASIC business Use limited PLD offerings+ASIC to compete Limited success converting Xilinx features Focus on lower density conversions Aggressive pricing to hide limitations
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Competition: AMI
FPGA conversions to grow ASIC business Aggressive pricing Questionable ability to convert FPGA features Customer services including N:1 Positions fast TAT and no charge for re-spins Excess fab capacity for 5v conversions Limited experience with 3.3v conversions
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Competition: Orbit
Leads with price Selectively takes $0 NRE deals Limited success implementing FPGA features .5 fab for sale 3.3v capability through fab partners Xilinx support removed from product literature
Xilinx academy 02-99 RWW Xilinx Confidential
HardWire Competition: ASIC Vendors-NEC,Toshiba,IBM,etc.
Focus is ASIC business 4KE/EX/XL conversions are resource drain Fixed pin-outs may differ from FPGA pin-out FPGA features difficult to emulate Test vectors required Customer must re-verify converted design Xilinx assumes risk and responsibility, ASIC
vendors assign risk to customer
Xilinx academy 02-99 RWW Xilinx Confidential
Future of Competitive Offerings FPGA vendors
— Lucent-Continue to support MACO for opportunistic business. Strategic accounts serviced by ASIC
— Altera-APEX, conversion competition forcing end of MPLD. Appearance of product line may remain.
ASIC vendors— AMI/Orbit/Temic: New FPGA architectures difficult to
convert. Focus on ASIC only business. Orbit business in jeopardy
— NEC,Toshiba,Hitachi:Focus will remain on ASIC only opportunities. Virtex features too difficult to emulate in traditional ASIC architectures.
Xilinx academy 02-99 RWW Xilinx Confidential
Keys to Success Selling FPGA+HardWire
Leverage FPGA— Lead with strength of FPGA products
Good Discovery— Information is key to our success
Proper Positioning— Focus on the right opportunities
Customer Support— Good communication simplifies the process
Xilinx academy 02-99 RWW Xilinx Confidential
Lead Sales Efforts with Strength of FPGA
Sell benefits of FPGA products first— Flexibility,ease of design,design verification— Time to volume is critical to customers— FPGA features and cores are barriers to ASICs— FPGA process migration leads to cost reduction— HardWire is here to support FPGA sales
Xilinx academy 02-99 RWW Xilinx Confidential
Good Discovery Information:Keep the competition honest
Competitive factors— FPGA vendor, ASIC, conversion house
Design specifics— Features, package, schedules
Decision influences— Cost, resources, risk, time to market
Production forecast— Verification in FPGA, production start
Xilinx academy 02-99 RWW Xilinx Confidential
Positioning HardWire Sets Expectations
HardWire is valuable to Xilinx customers— Conversion success is our #1 goal — Significant FPGA cost reduction is our target— FPGA +HardWire reduces time to volume — Density focus on 4KE/EX/XL— Volume focus on opportunities >10KU
Xilinx academy 02-99 RWW Xilinx Confidential
Customer Support Leads to Satisfaction
Communication is key to a successful conversion— Milestone communication — Design functionality verification before submittal— Review of design center reports with customer— Design/ feature implementation review prior to
conversion, conversion report review and sign-off— Follow-up on action items
Xilinx academy 02-99 RWW Xilinx Confidential
Key Messages for HardWire
Reduced conversion risk through
DesignLockTM
High density/ high volume 4KXL FPGA opportunities
Turnkey conversion:
Minimal customer interface
Competitive sales toolversus
FPGA competition
HardWire products: FPGA cost reduction made
simple