XII CONFERENCE

DCIS'97

TECHNMSOHEI N F O R M A T ! O N S 3 ! B L ; C T H E K

UNlVEHSITATSSiBLiOTHEKHANNOVER

Proceedings of

THE XII DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS

CONFERENCE DCIS'97

Edited by

L. Garcia Franquelo

A. Torralba

M. A. Aguirre

TABLE OF CONTENTS

INTRODUCTORYSECTION

The XII DCIS Conference XIX

Organizing Committee and Local Secretariat XXReviewers XXI

PLENARY SESSIONS...

Plenary Session 1Chairman: Jose Luis Huertas. CNM, Sevilla

NEW TRENDS AND CHALLENGES ON ACTIVE FILTERSProf. Edgar Sanchez Sinencio. Dept. of Electrical Engineering. Texas A&M University (USA)

Plenary Session 2Chairman: Joan Figueras. Universitat Politecnica de Catalunya, Barcelona

BLOCK-DRIVEN ANALOG-DIGITAL INTERFACE DESIGN.Prof. Jose E. Franca. Instituto Superior Tecnico, Lisboa (Portugal)

Plenary Session 3Chairman: Jose Maria Insenser. SIDSA, Tres Cantos (Madrid)

AN OVERVIEW OF FPGA RESEARCH.Prof. Stephen Brown. Dept. of Electrical and Computer Engineering. Universityof Toronto (Canada)

TUTORIALS

Tutorial 1: MODERN MONOLITHIC ANALOG FILTERSProf. Edgar Sanchez-Sinencio. Texas A&M University (USA)

Tutorial 2: CMOS ANALOG-DIGITAL INTERFACE DESIGNProf. Jose E. Franca. Instituto Superior Tecnico. Lisboa (Portugal)

Tutorial 3: AN OVERVIEW OF FIELD-PROGRAMMABLE DEVICES (SPLDS, CPLDS, FPGAS)

Prof. Stephen Brown. University of Toronto (Canada)

PANELS..

Panel 1: LONG TERM RESEARCH IN MICROELECTRONICSOrganizer: Javier Uceda Antolin. Universidad Politecnica de Madrid

Panel 2: R&D IN ELECTRONICS, THE EUROPEAN PERSPECTIVEOrganizer: Carlos Lopez Barrio. Telefonica I+D

Panel 3: NEW TRENDS AND APPLICATIONS FOR FPGA'SOrganizer: Joan Cabestany Moncusi. Universitat Politecnica de Catalunya

SESSIONS..

Session 1: TECHNOLOGICAL ASPECTS IN THE DESIGN OF IC's AND SENSORS...Chairman: Daniel Auvergne. LIRMM/UM2, Montpellier

EASY AND CHEAP CMOS TRANSISTOR MISMATCH CHARACTERIZATION AND CONSEQUENTSIMULATIONT. Serrano-Gotarredona and B. Linares-BarrancoInstituto de Microelectronica de Sevilla. Centro Nacional de Microelectronica

SCALING TRENDS FOR THE DELTA-I NOISE IN SUB-MICRON CMOS 15TECHNOLOGIESJ.L. Gonzalez, X. Aragones, F. Moll and A. RubioElectronic Engineering Department. UPC

TECHNOLOGICAL COMPENSATION CIRCUIT FOR ACCURATE TEMPERATURE 19SENSORR. Amador, A. Polanco, H. Hernandez, E. Gonzalez and A. NagyCentro de Investigacion en Microelectronica. Ciudad Habana - Cuba

Session 10: BOUNDARY SCAN TECHNIQUES 2 5

Chairman: Salvador Bracho. Universidad de Cantabria, Santander

THE POST APPROACH TO ON-LINE FAILURE DETECTION BASED ON BST 27J.M. Vieira dos Santos and J.M. Martins Ferreira(*)I. S. Engenharia do Porto - Portugal(*) Universidade do Porto - Portugal

HIGH-LEVEL TEST SPECIFICATION AND PLANNING FOR MIXED SIGNAL BOARDS WITHBOUNDARY SCAN 3 3

J.C. Ferreira(*)O, A.C. Leao(*)("*). J.M. Silva(*)(") and J. Silva Matos(*)(")(*) Instituto de Engenharia de Sistemas e Computadores. Porto - Portugal{") Faculdade de Engenharia de Universidade do Porto - Portugal(***) Instituto Superior de Engenharia do Porto - Portugal

EXPERIMENTS ON MIXED CURRENT/VOLTAGE TESTING USING THE IEEE P1149.4INFRASTRUCTURE 3 9

J. Machado, A. C. LeaoC), J.C. Alves and J. Silva Matos

Faculdade de Engenharia da Universidade do Porto - Portugal(*) Instituto Superior de Engenharia do Porto - Portugal

A VIRTUAL AND A REAL PROTOTYPE OF A BOUNDARY SCAN TESTER 45E. de la Torre, F. Matias, J.M. Uhagon and J. UcedaUniversidad Politecnica de Madrid. ETSI Industrials de Madrid

Session 19: ANALOGUE DESIGN 1 51Chairman: Francisco Duque. Universidad de Extremadura, Badajoz

A CURRENT-MODE WTA-MAX CIRCUIT WITH MULTI-CHIP CAPABILITY 53T. Serrano-Gotarredona and B. Linares-BarrancoInstituto de Microelectronica de Sevilla. Centro Nacional de Microelectronica

DESIGN CONSIDERATIONS OF REGULATED-CASCODE CURRENT 59COPIERSM.A. Suquet, J. Madrenas, J.M. Moreno and E. AlarconDepartment d'Enginyeria Electronica. Universitat Politecnica de Catalunya. Barcelona

A CONTINUOUS TIME BIQUAD IN SOI TECHNOLOGY 6 5

J. Sabadell, S. Celma, D. Flandre and P.A. MartinezGrupo de Diseno Electronico. Departamento de Ingenieria Electronica y Comunicaciones.Universidad de Zaragoza

Session IN-1: COMMUNICATION APPLICATIONS 71Chairman: Rafael Burriel. Alcatel, Madrid

ASIC DESIGN FOR PUBLIC TELEPHONES 7 3

D. Navarro, J.I. Garcia Nicolas, I. Paradaf), M.A. Lopezf), A. Roy and C. Paz (*)Department of Electronics and Communications. University of Zaragoza(*) Siemens-Elasa S. A. Zaragoza

MODASC: ASIC FOR MOBILE DATA ACQUISITION SYSTEMS USING SATELLITECOMMUNICATIONS 7 7

J.M. Quero, L.G. Franquelo, C.L. Janer, J.G. Ortega, S.Toral, F Marin(*) and J. L6pez(*)Dpto. de Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla(*) Sainsel

AN ADAPTIVE EQUALISER/PREDISTORTER SYSTEM FOR WIRELESS DIGITALCOMMUNICATIONS 8 1

G. Nunez, A.Fernandez, R.Burriel, J.Casajus(*) J.M. Paez(*) and O.NietoOAlcatel Telecom. Madrid(*) Universidad Politecnica de Madrid

DESIGN AND IMPLEMENTATION OF A COMPUTER TELEPHONY CARD 8 5

III

J.A. Herrera, S. Lopez-Buedo, F. Moreno, J. Meneses and F. Fernandezf)E.T.S.I. Telecomunicacion. Universidad Politecnica de MadridOFedetec. Madrid

Session 2: INTEGRATED SENSORS AND MICROSYSTEMSChairman: Luis Castaner. Universitat Politecnica de Catalunya, Barcelona

87

TEST STRUCTURES FOR SILICON PRESSURE SENSORS INTEGRATED IN A COMMERCIALCMOS TECHNOLOGYE. Montane, S. Bota, S. Marco, M. Carmona and J. SamitierDepartament de Fisica Aplicada i Electronica. Universitat de Barcelona

89

A SIMPLE APPROACH TO AN ELECTROCHEMICAL ISFET MODEL..V. Escartin, A. Lastres and D. CriadoCentro de Investigacion en Microelectronica. Ciudad Habana - Cuba

95

SMART SENSORS FOR IMAGE PROCESSINGA.P. Vega-Leal and A. TorralbaDpto. de Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla.

99

PTAT SOURCE FOR ON-CHIP TEMPERATURE COMPENSATION OF PIEZORESISTIVEPRESSURESENSORSM. ZabalaSilicon Technologies and Microsystems Department. Centre Nacional de Microelectronica.Barcelona

105

Session 11: SELF TEST TECHNIQUESChairman: Antonio Lloris Ruiz. Universidad de Granada, Granada

111

CELLULAR AUTOMATA-BASED MIXED TEST PATTERNS GENERATOR FOR BUILT-IN SELF-TESTM.J. Lopez and S. BrachoMicroelectronic Engineering Group. T.E.I.S.A. Department. E.T.S.I.I.T University of Cantabria

113

A SYSTEM-LEVEL ARCHITECTURE FOR ON-LINE TESTING OF ANALOG CIRCUITS WITH OFF-LINE TEST FACILITIES AND BIST CAPABILITIESD. Vazquez, A. Rueda and J.L. HuertasInstituto de Microelectronica de Sevilla. Universidad de Sevilla

119

TEST OPTIMIZATION IN SWITCHED-CAPACITOR SYSTEMS THROUGH SWITCH-LEVEL FAULTCOVERAGE ANALYSISS. Mir, A. Rueda, D. Vazquez and J.L. HuertasInstituto de Microelectronica de Sevilla. Centro Nacional de Microelectronica

125

DESIGN AND VALIDATION OF FAIL-SAFE FSMS USING REGULAR STRUCTURES.. 131

IV

J.J. Rodriguez Andina, S. Fernandez and E. MandadoDepartamento de Tecnologia Electronica. Universidad de Vigo

Session 20: ANALOGUE DESIGN II 137Chairwoman: Adoracion Rueda. CNM, Sevilla

A MISMATCH-INSENSITIVE HIGH ACCURACY HIGH-SPEED CONTINUOUS-TIME CURRENTCOMPARATOR IN LOW VOLTAGE CMOS 1 3 9

R. del Rio, G. Linan, R. Dominguez-Castro and A. Rodriguez-VazquezInstituto de Microelectronica de Sevilla. Universidad de Sevilla

BIPOLAR AND MOS FOLDING BLOCKS FOR HIGH SPEED A/D 145CONVERTERSJ.R. Fernandes and M. de Medeiros SilvaINESC/I. S. Tecnico. Lisboa - Portugal

SIMULATED IMPEDANCES AND OSCILLATORS USING CMOS CCH 151I. Herrera, A. Carlosena, R. Cabeza and L. SerranoDept. de Ingenieria Electrica y Electronica. Universidad Publica de Navarra

TIME-SHARED SC FILTER BANKS IMPLEMENTATION WITH PROGRAMMABILITY BY TIMING 157J.L. Ausin, J.M. Carrillo, P. Merchan and J.F. DuqueDept. Electronica e Ing. Electro. Universidad de Extremadura

Session IN-2: COMMUNICATION AND INDUSTRIAL APPLICATIONS 1 "Chairman: Jose Luis Conesa. Telefonica I+D, Madrid

LOW INTERMODULATION CONVERTER SYSTEM FOR TV DISTRIBUTION 165M'L. de la Fuente, J.P. Pascual, E. Artal and F. L6pez(*)Departamento de Ingenieria de Comunicaciones. ETSII y de Telecomunicadon. Universidad deCantabria(*) IKUSI. San Sebastian

DESIGN AND IMPLEMENTATION OF A FBPSK MODULATOR BASED ON PROGRAMMABLELOGIC 1 6 9

J.A. Rabadan Borges, R. Perez and M.J. BetancorETSIT. Universidad de las Palmas de Gran Canaria

A NEW LOW COST INTEGRATED SOLUTION FOR FLUORESCENT LAMP EMERGENCYSYSTEM 1 7 3

J. Diaz, F.F. Linera, A. Martin, M.A. Perez and M. Jaureguizar(*)ATE. Universidad de Oviedo. E.T.S.I.I. Gijon(*) GS, S. A.

MULTIPLEXED MEASUREMENT SYSTEM IN COMPOSITE MATERIALS FOR AERONAUTICAPPLICATIONS 1 7 7

H. Lamela, J.I. Santos, A. Varo and J.A. GarciaGrupo de Optoelectronica y Tecnologia Laser. Escuela Politecnica Superior. Universidad CarlosMadrid

Session 5: MODELLING AND SIMULATION OF IC's AND SENSORS 181Chairman: Eugenio Garcia Moreno. Universitat Illes Balears, Palma de Mallorca

CROSSTALK NOISE EVALUATION FOR SUBMICRONIC CIRCUITS 183D. Deschacht and P. BatoucheLaboratoire d'lnformatique, de Robotique et de Microelectronique. Universite Montpellier II. France

A PIECEWISE-LINEAR LATTICE RESISTIVE (PLR) MODELS WITH INTERPOLATION 189J.M. Tarela and M\ V. MartinezDepartment of Electricity and Electronics. Faculty of Sciences. Vizcaya

METFAC-2: A TOOL FOR SPECIFICATION AND SOLUTION OF MARKOV PERFORMANCE,DEPENDABILITY AND PERFORMABILITY MODELS 1 9 5

J.A. Carrasco and J.L. DomingoDepartament d'Enginyeria Electronica. Universitat Politecnica de Catalunya

Session 12: METHODOLOGIES FOR ATPG 2 0 1

Chairman: Antonio Rubio. Universitat Politecnica de Catalunya, Barcelona

A SELF-TIMED SCAN-PATH ARCHITECTURE 2 0 3

T. A. Garcia, A. J. Acosta, J. M. Mora and J. RamosInstituto de Microelectronica de Sevilla. CNM

IDDQ TESTING GOS FAULTS IN ICS: THE NEED OF NEW TPG ALGORITHMS 209M. Roca, E. Isern, D. Talet and J. SeguraDept. Fisica. Universitat Illes Balears

A SPECIFIC TEST PATTERN GENERATION METHODOLOGY FOR RAM-BASED FPGA LOGICMODULES 2 1 3

M. RenovellO, J.M. Portalf), J. Figueras(") and Y. Zorian(***)(*) LIRMM-UM2. France(**)Universitat Politecnica de Catalunya(***) Logic Vision inc. USA

Session 26: ICs FOR CONTROL AND POWER APPLICATIONS 2 i 9

Chairman: Joan Peracaula. Universitat Politecnica de Catalunya, Barcelona

VI

AN IGBT SHORT-CIRCUIT PROTECTION CIRCUIT USING CMOS 2 2 1TECHNOLOGYH. ValderramaO, A. Esquivel(") and A. Rubio(")(*) ESTE. Dept. of Electronics Engineering URV. Tarragona(**) ETSET. Dept. of Electronics Engineering UPC. Barcelona

MULTI-CONVERTER DIGITAL CONTROL WITH AN APPLICATION SPECIFIC INTEGRATEDCIRCUITJ. Peracaula and J.L. BerruecoDepartment of Electronic Engineering. Power Electronics Division. Universidad Politecnica deCatalufia. E.T.S. Ing. Industriales

EC-RASP: A NEW ELECTRICAL ENERGY STATIC COUNTER BASED ON RANDOM SIGNALPROCESSING 2 3 3

S. Toral, J.M. Quero and L.G. FranqueloDpto. de Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla

Session 21: SWITCHED CURRENT CIRCUITS 239Chairman: Angel Rodriguez-Vazquez. CNM, Sevilla

NOISE AND SPEED PERFORMANCE IN SWITCHED-CURRENT MEMORY 2<t1CELLSE. Alarcon, M. lannazzo and J. MadrenasDept. Enginyeria Electronica. Universitat Politecnica de Catalunya

QUANTIZATION NOISE SHAPING DEGRADATION IN SWITCHED-CURRENT BANDPASSSIGMA-DELTA MODULATORS 2 4 7

J.M. de la Rosa, B. Perez-Verdii, F. Medeiro and A. Rodriguez-VazquezInstituto de Microelectronica de Sevilla. CNM

ANALYSIS OF CLOCK FEEDTHROUGH EFFECTS IN SWITCHED-CURRENT 253CIRCUITSJ.M. Martins and V. F.DiasINESC. Lisboa - Portugal

Session 6: CAD METHODS AND TOOLS 1 2 5 9

Chairman: Roberto Sarmiento. Universidad Las Palmas de Gran Canaria, Las Palmas de GranCanaria

FPGA'S TIMING COMPUTATIONS TARGETED TO RTL ESTIMATIONS 2 61R. Maestre, M. Fernandez and H. MechaDpto. de Arquitectura de Computadores y Au tomata . UCM

C++ FRONT-END FOR ROBDD PACKAGES. ROBDD PACKAGES COMPARATIVE 267R. Capillas. J. Riera and J. CarrabinaDepartamento de Informatics. Facultad de Ciencias. Bellaterra - Barcelona

VII

AN AUTOMATIC TECHNIQUE FOR DIGITAL CMOS CIRCUIT 273PARTITIONINGL. Ribas and J. CarrabinaMicroelectronics Group. Computer Science Dept. Universitat Autonoma de Barcelona

AN ALGORITHM TO FIND MINIMAL CUTS OF S-COHERENT FAULT TREES WITH EVENTCLASSES USING A DECISION 2 7 9

TREEJ.A. Carrasco and V. SufieDepartament d'Enginyeria Electronica. Universitat Politecnica de Catalunya

Session 8: HIGH-LEVEL SYNTHESIS AND VHDL 1 285Chairman: Juan Carlos Lopez. Universidad Politecnica de Madrid, Madrid

USING EQUATIONAL SPECIFICATIONS FOR BEHAVIORAL SYNTHESIS 287J.M. Mendias and R. HermidaDept. de Arquitectura de Computadores y Automatica. Universidad Complutense de Madrid

PERFORMANCE-DRIVEN SWITCH LEVEL LOGIC SYNTHESIS 293J. Riera, J. Velasco, L. Ribas and J. CarrabinaUnitat de Microelectronica. Dpt. D'lnformatica. Universitat Autonoma de Barcelona

A SET OF TOOLS TO HELP IN THE VHDL DESIGN FLOW OF COMPLEX SYSTEMS 299Y. Torroja, C. Lopez, T. Riesgo and J. UcedaE.T.S.I. Industriales. Universidad Politecnica de Madrid. Division de Ingenieria Electronica

A CONFIGURABLE VHDL MODEL OF FIFO MEMORIES 3 0 5

E. de la Torre, J. de la Fuente, Y. Torroja, T. Riesgo and J. UcedaE.T.S.I. Industriales. Universidad Politecnica de Madrid. Division de Ingenieria Electronica

Session 27: NEURAL AND FUZZY SYSTEMS 1 3 "Chairman: Francisco Sandoval. Universidad de Malaga, Malaga

IMPLEMENTATION OF NEURO-FUZZY MODELS WITH ANALOG SYSTOLIC 313ARCHITECTURES.... 'AJ.M. Moreno, J. Madrenas, F. Guinjoan and J. Cabestany •']Universitat Politecnica de Catalunya. Department d'Enginyeria Electronica

A ONE-TRANSISTOR-SYNAPSE STRATEGY FOR ELECTRICALLY-PROGRAMMABLEMASSIVELY-PARALLEL ANALOG ARRAY 3 1 9

PROCESSORSR. Dominguez-Castro, A. Rodriguez-Vazquez, S. Espejo and R. CarmonaInst. de Microelectronica de Sevilla. Centro Nacional de Microelectronica. C.S.I.C. Universidad deSevilla u

VIII ^

STOCHASTIC AND PWM CODING FOR AN EFFICIENT IMPLEMENTATION OF CELLULARNEURAL 325NETWORKSF. Colodro, A. Torralba, R.G. Carvajal and LG. FranqueloDept. de Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla

Session IN-3: INDUSTRIAL CONTROLChairman: Miguel Hernandez. Siemens, Munich

LOW POWER CONSUMPTION MEASURING ASIC FOR POWER LINES 331S. Urquijo, I. Unanue, A. Irizar and F. AriztiCentro de Estudios e Investigaciones Tecnicas de Guipuzcoa

MEDIRECT. A FIRST USER'S EXPERIMENT 335E. Ramos, J. Pinilla, A. TorralbaC) and L.G. FranqueloOSAINCO I+D. Sevilla(*) Dpto. Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla

A GENERATOR APPROACH FOR IMPLEMENTING HARD-WIRED DIGITAL SIGNALPROCESSORS IN ASICS 3 3 9

E. Ofner and S. SattlerAustria Mikro Systeme International AG. Austria

ELECTRONIC CONTROL OF OPTOMECHANICAL SCANNING IN A STEREO VISION SYSTEMFOR A TELEOPERATED ROBOT (ROBTET) 3 4 3

H. Lamela, E. Garcia, S. Gomez, J.R. Lopez, P. Acedo and G. CarpinteroGrupo de Optoelectronics y Tecnologia Laser. Area de Tecnologia Electronica. Departamento deIngenieria. Universidad Carlos III de Madrid

Session 7: CAD METHODS AND TOOLS II 3 4 7

Chairman: Jordi Carrabina. Universidad Autonoma, Barcelona

USING CAD TOOLS FOR THE AUTOMATIC DESIGN OF LOW-POWER SIGMA-DELTAMODULATORS 3 4 9

F. Medeiro, B. Perez-Verdii, J.M. de la Rosa and A. Rodriguez-VazquezInstituto de Microelectronica de Sevilla. CNM

CELL AREA AND PARASITIC CAPACITANCE MINIMIZATION BASED ON EXTREME-CHAINING.. 355X. Marin Lozano and J. CarrabinaDepartament d'lnformatica. Unitat de Microelectronica

VLSI FULL-CUSTOM CELL AND MACROCELL GENERATION IN GaAs 361J.A. Montiel-Nelson, V de Armas, R. Sarmiento and A. NunezCentre for Applied Microelectronics. E.T.S. de Ingenieros de Telecomunicacion. ULPGC

IX

AUTOMATIC SYNTHESIS OF ANALOG FUZZY CONTROLLERSR.G. Carvajal, A. Torralba, F. Colodro and L.G. FranqueloDpto. de Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla

369

Session 9: HIGH-LEVEL SYNTHESIS AND VHDL IIChairman: Juan Meneses. Universidad Politecnica de Madrid, Madrid

375

REUSABILITY AND PARALLELISM EFFECTS ON THE PARTITIONING PROCESS FOR ACODESIGNENVIRONMENTJ.A. Maestro and D. MozosDpto. de Arquitectura de Computadores y Automatica. Universidad Complutense de Madrid

377

THE PCI LOCAL BUS TOOLKITF.J. Palao(*), P. Merino and J.C. LopezLaboratorio de Sistemas Integrados. Departamento de Ingenieria Electronica. UniversidadPolitecnica de Madrid(*) Lucent Technologies Network Systems

383

EMBEDDED SYSTEM SPECIFICATION IN ADAA. Lopez, M. Veiga, P. Sanchez and E. VillarMicroelectronics Engineering Group. TEISA Department. University of Cantabria

389

Session 28: NEURAL AND FUZZY SYSTEMS IIChairwoman: Teresa Riesgo. Universidad Politecnica de Madrid, Madrid

395

A HIGH-YIELD ART1 MICROCHIP AND ITS APPLICATION IN MULTI-ART1SYSTEMST. Serrano-Gotarredona and B. Linares-BarrancoInstituto de Microelectronica de Sevilla. Centro Nacional de Microelectronica

397

MULTIPLEXING STRATEGY FOR MIXED SIGNAL CMOS FUZZY CONTROLLERSR. Navas-Gonzalez, F. Vidal-Verdu and A. Rodriguez-Vazquez(')Dept. de Electronica. Universidad de Malaga(*) Dept. of Analog and Mixed-Signal Circuit Design. Centro Nacional de Microelectronica.Universidad de Sevilla

401

AN ANALOG CMOS UNIVERSAL MEMBERSHIP FUNCTION CIRCUIT WITH FULLYINDEPENDENT, ADJUSTABLEPARAMETERSR.G. Carvajal, A. Torralba, F. Colodro and L.G. FranqueloDpto. de Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla

407

Session IN-4: INDUSTRIAL TOOLS FOR ASIC's..Chairman: Juan Mulet. Cotec, Madrid

413

TRADEOFFS FOR THE DESIGN OF PROGRAMMABLE INTERCONNECTS IN FPGA'S 415J. Faura and J.M. InsenserSemiconductores Investigacion y Diseno, S.A. Madrid

RAISE: A DETAILED ROUTING ALGORITHM FOR FIELD-PROGRAMMABLE GATE ARRAYS 421V. Baena-Lecuyer, M.A. Aguirre, A. Torralba, L.G. Franquelo and J. Faura(")Dpto. de Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla(*) Semiconductores Investigacion y Diseno, S. A. Madrid

FORMALCHECK: APPLYING VERIFICATION TOOLS TO LOGIC DESIGN 425J. Calero, C. Roman and G. de PalmaLucent Technologies, Bell Labs Innovations

ELECTRONIC DESIGN OPTIMIZATION BY MODELLING RELIABILITY, MAINTAINABILITYAND TESTABILITY 4 2 9

E. ZabalaLabein

Session 13: GaAs INTEGRATED CIRCUITS 4 3 3

Chairman: Antonio Nunez. Universidad Las Palmas de Gran Canaria, Las Palmas de Gran Canaria

A LOW POWER PIPELINED GaAs ROM 435L. Hernandez, J.F. Lopez, F. Tobajas, R. Esper-Chain, R. Sarmiento and A. NiinezCentre for Applied Microelectronics. University of Las Palmas de Gran Canaria

NEW HIGH SPEED GAAS MEMORY CELL 4 4 1

A. Bernal("), R.P. Ribas and A. GuyotTIMA Laboratory. Grenoble.(*) Universidad del Valle. Cali - Colombia

A GalnP/GaAs HBT DIELECTRIC RESONATOR OSCILLATOR AT 6.7 GHZ 447S. Perez, D. FloriotO, Ph. Maurin("), Ph. Bouquet(") P.M. Gutierrez, J. Obregon("*) and S.L.Delagef)Universidad de Salamanca. Departamento de Fisica Aplicada(*) THOMSON-CSF LCR. Orsay Cedex - France(**) THOMSON-CSF Composant Microelectroniques. Massy Cedex - France(***) IRCOM Universite de Limoges. Limoges Cedex - France

Session 4: DELAY AND TIMING MODELLING 4 5 1

Chairman: Jaume Segura. Universitat Illes Balears, Palma de Mallorca

TIMING ANALYSIS MODEL BASED ON SENSITIVITY FOR DCFL FAMILY WITH HFET'S 453J. Garcia, A. Hernandez, B. Gonzalez, J. del Pino and A. NunezCentre for Applied Microelectronics. University of Las Palmas de Gran Canaria

XI

PERFORMANCE ANALYSIS AND PROPAGATION DELAY TIME ESTIMATION OF LOGICFAMILIES WITH HBTS 4 5 9

J. del Pino, A. Hernandez, B. Gonzalez, J. Garcia and A. NunezCentre for Applied Microelectronics. University of Las Palmas de Gran Canaria

FULLY PHYSICAL CHARACTERIZATION OF THE DELAY DEGRADATION EFFECT INSUBMICRONIC CMOS INVERTERS 4 6 5

J. Juan-Chicof), M.J. Bellidof), A.J. Costa("), A. Barrigaf*) and M. Valencia(')Instituto de Microelectronica de Sevilla. Centro Nacional de Microelectronica(*) Dpto. de Tecnologia Electronica de la Universidad de Sevilla(**) Dpto. de Electronica y Electromagnetismo de la Universidad de Sevilla

AN ANALYTICAL MODEL OF THE CHARGE DRIVEN BY CMOS BUFFERSJ.L. Rosello, E. Isern, M. Roca, E. Garcia and J. SeguraPhysics Dept. Univ. Illes Balears

Session 22: MIXED SIGNAL DESIGN "75Chairman: Manuel de Medeiros Silva. INESC, Lisboa

DISCRETE-TIME CHAOTIC CODEC 4 7 7

M. Delgado-Restituto and A. Rodriguez-VazquezCentro Nacional de Microelectronica. Sevilla

INFLUENCE OF HARDWARE NON IDEALITIES ON CONTINUOUS-TIME CHAOTICOSCILLATORS 4 8 3

M. Delgado-Restituto and A. Rodriguez-VazquezCentro Nacional de Microelectronica. Sevilla

LOW-NOISE LOGIC FAMILIES FOR MIXED SIGNAL IC'S 489E.F.M. Alburquerque, M. de Medeiros and V.F. DiasINESC/I. ST. Lisboa - Portugal

CAPACITANCE MODELLING FOR MIXED SIGNAL APPLICATIONS IN DIGITAL CMOSTECHNOLOGY 4 9 5

S.A. Bota, J.M* Gomez, E. Montane and J. SamitierDepartament de Fisica Aplicada i Electronica. Universitat de Barcelona

Session IN-5: INDUSTRIAL TECHNOLOGY 5°1Chairman: Juan Jose Mangas. Cotec, Madrid

AIPAC: INTRODUCING AN ADVANCED INTERCONNECTION TECHNOLOGY IN PORTUGAL 503G. da Silva Arroz, C. Beltran(*) and V. Chatinho(*)Instituto Superior Tecnico. Lisboa - Portugal(*) INESC. Lisboa - Portugal

XII

LIGHT INDUCE VOLTAGE ALTERATION (LIVA): AN INDUSTRIAL APPROACH TO AN ICTESTING TECHNIQUE 5 0 7

J. Barbero and E. CorderoAlcatel - Espana S.A. Laboratorio Central de Calidad

AMORPHOUS-WIRE CURRENT SENSORS 511M.J. Prieto, A.M. Pernia, F. Nuno, J.M. Lopera, R. Gutierrez and L. Alvarezf)Universidad de Oviedo. Area de Tecnologia Electronica(*) Alcatel Espana, S. A. Dpto. de Tecnologia de Electronica de Potencia. Madrid

CURRENT SENSOR BASED ON ANISOTROPIC MAGNETORRESISTENCE EFFECT 515A.M. Pernia, J.M. Lopera, M.J. Prieto, F. Nuno and S. Ollero(*)Universidad de Oviedo. Area de Tecnologia Electronica(*) Alcatel Espana, S. A. Dpto. de Tecnologia de Electronica de Potencia. Madrid

Session 14: POWER CONSUMPTION 519Chairman: Denis Deschacht. LIRMM, Universite de Montpellier II

ON ESTIMATING STATIC POWER CONSUMPTION IN PSEUDO-NMOS PROGRAMMABLELOGIC 521S. Fransi, S. Manich and J. FiguerasDepartament Enginyeria Electronica. Universitat Politecnica de Catalunya

WORST CASE DYNAMIC POWER CONSUMPTION 527S. Manich and J. FiguerasDepartament Enginyeria Electronica. Universitat Politecnica de Catalunya

AN EXPERIMENTAL APPROACH FOR POWER CONSUMPTION ANALYSIS 533J. Garcia and J. RiusDepartament Enginyeria Electronica. Universitat Politecnica de Catalunya

Session 3: DIGITAL IC DESIGN 539Chairman: Horacio Lamela. Universidad Carlos III, Madrid

PERFORMANCE COMPARISON OF CMOS DIFFERENTIAL CIRCUITS FOR LOW-POWER ANDSELF-TIMED APPLICATIONS 5 4 1

R. JimenezO, A.J. Acosta, A. Barriga, M. Bellido and M. ValenciaInstituto de Microelectronica de Sevilla. CNM. Universidad de Sevilla(*) Dept. de Ingenieria Electronica, de Sistemas Informations y Automatica. Universidad de Huelva

CROSSTALK EFFECTS IN BASIC GATE INPUTS AND TOLERANT PROPOSAL 547J.A. Sainz, A. Aledo, L.A. Aguado and M. Roca(*)EUITI. Universidad del Pais Vasco(*) Universidad de las Islas Baleares

XIII

A PRACTICAL APPROACH TO DESIGNING HIGH-SPEED CMOS CIRCUITS WITH TSPC 553LOGIC...N. Simon and L. Ribas(*)Institut de Microelectronica de Barcelona. Centre Nacional de Microelectronica(*) Microelectronics Group. Computer Science Dept. Universitat Autonoma de Barcelona

A LIBRARY OF REUSABLE ARITHMETIC COMPONENTS 559P.L. Ruiz, T. Riesgo, Y. Torroja, E. de la Torre and J. UcedaUniversidad Politecnica de Madrid. E.T.S.I. Industriales. Division de Ingenieria Electronica

Session 23: IMAGE PROCESSING IC DESIGN 565Chairman: Armando Roy. Universidad de Zaragoza, Zaragoza

HARDWARE FOR LOSSLESS WAVELET COMPRESSION OF MEDICAL IMAGES: A CRITICALREVIEW 567I. Urriza, L.A. Barragan, J.I. Artigas, J.I. Garcia and D. NavarroDepartament of Electronics and Communications Engineering. University of Zaragoza

FPGA BASED IMAGE PREPROCESSING SYSTEM FOR ENHANCED PARALLEL PORT 573J.L. Martin, J. Ezquerra and P. IbanezUniversidad del Pais Vasco. Departamento de Electronica y Telecomunicaciones

A PCI-BASED COMPUTER VISION SYSTEM 579F. Lisa, J. Noguera, F. Cuadrado, D. Rexachs, D. Benitez(') and J. CarrabinaDept. of Computer Science. Universitat Autonoma de Barcelona(*) Dept. of Computer Science. Universidad de Las Palmas de Gran Canaria

A WAVELET TRANSFORM AND ZERO-TREE PROCESSOR FOR IMAGE AND VIDEOCOMPRESSION 5 8 5

G. KnowlesDept. de Informatica. UIB. Palma - Balears

Session IN-6: INDUSTRIAL FPGA APPLICATIONS 591Chairman: Jose Calero. Lucent Technologies

A RECONFIGURABLE TEST-BED BASED ON FPGA'S FOR THE VERIFICATION OFINTEGRATED 5 9 3

CIRCUITSP. Matas and P. PlazaTelefonica I+D. Madrid

FIPSOC: A FIELD PROGRAMMABLE SYSTEM ON CHIP 597J. Faura, M.A. AguirreO, J.M. Moreno("), P. Van DuongC") and J.M. InsenserSIDSA. Madrid

xrv

(*) Dept. de Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla(**) Universitat Politecnica de Catalunya(*") MIKRON GmbH. Germany

WELDING DATA ACQUISITION BASED ON FPGA '. 603R. Millan, J.M. Quero and L.G. FranqueloDept. de Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla

DSP AND FPGA BASED SYSTEM TO CONTROL A WIND TURBINE GENERATORIMPLEMENTING A VARIABLE SPEED VECTORIAL CONTROL 6 0 9

METHODM. Perales, F. Barrero, J.L. Mora, E. Galvan, J.M. Carrasco and L.G. FranqueloDpto. de Ingenieria Electronica. Escuela Superior de Ingenieros. Universidad de Sevilla

Session 15: LOW POWER 6 1 3

Chairwoman: Mar Martinez. Universidad de Cantabria, Santander

TEMPERATURE AND VOLTAGE DERATING CALCULATION FOR TIMING ESTIMATION IN THELOW VOLTAGE 6 1 5

DOMAINJ.M. Daga and D. AuvergneLIRMM, UMR CNRS/Universite de Montpellier II. France

LEAKAGE POWER SENSITIVITY TO PROCESS VARIATIONS IN SUBMICRON CMOS DIGITALCIRCUITS 621A. Ferre and J. FiguerasDepartament d'Enginyeria Electronica. Universitat Politecnica de Catalunya

QUIESCENT CURRENT DETECTABILITY OF VTH AND BRIDGING DEFECTS IN A FOLDEDCASCODE CELL 6 2 7

A.M. Brosa, R. Rodriguez and J. FiguerasDepartament d'Enginyeria Electronica. Universitat Politecnica de Catalunya

Session 17: FPGA'S BASED SYSTEMS 1 6 3 3

Chairman: Enrique Mandado. Universidad de Vigo, Vigo

FPGA DESIGN OF A DMA CONTROLLER FOR VME-SPARC SHARED 635MEMORYL. Entrena, L. de Zulueta, A. Quesada, J.A. Espejo, J.M. Pena, L. Mengibar, E. Olias, J.L. Ruiz(")and A. Tichell(')Area de Tecnologia Electronica. Universidad Carlos III. MadridO TGI, S. A. Madrid

VHDL DESCRIPTION AND FPGA IMPLEMENTATION OF A NOTCH LMS ADAPTIVE FILTER FOR 641NOISE CANCELINGA. Rosado, J. Calpe, M. Bataller, J.F. Guerrero, J.V. Frances and M. MartinezGPDS. Dpto. Informatica y Electronica. Universidad de Valencia

XV

USING FPGAs FOR THE RAPID PROTOTYPING OF PROGRAMMABLE INTERFACESORIENTED TO MICROCONTROLLER 647SYSTEMSM.D. Valdes, M.J. Moure and E. MandadoDepartamento de Tecnologia Electronica. Instituto de Electronica Aplicada "Pedro Barrie de laMaza". Universidad de Vigo

Session 24: PARALLEL IMAGE VIDEO PROCESSING 653Chairman: Roman Hermida. Universidad Complutense de Madrid, Madrid

AN ARCHITECTURE CONCEPT FOR HARDWARE ACCELERATED IMAGE SEGMENTATION.... 655S. Herrmann, H. Mooshofer and W. StecheleInstitute for Integrated Circuits. Technical University of Munich

A FLEXIBLE HARDWARE ACCELERATOR FOR FILTER ALGORITHMS IN DIGITAL VIDEOCODING 661A. Hutter, C. Graber, P. Kindsmuller and W. StecheleInstitute for Integrated Circuits. Technical University of Munich

A FLEXIBLE PARALLEL AND PIPELINED ARCHITECTURE TO IMPLEMENT REGULARFLOWGRAPH FAST TRANSFORMS 6 6 7

J.A. Munoz, S. Alexandres, F. Moreno and J. MenesesElectronics Engineering Department. E.T.S.I. Telecomunicacion. U.P.M.

Session IN-7: INDUSTRIAL VHDL APPLICATIONS 673Chairman: Eugenio Villar. Universidad de Cantabria, Santander

THE SKYPLEX DEMODULATOR ASIC 675MA. Rey, F. Alcala, J. Ribaf) and G. VazquezOAlcatel Espacio(*) Polytechnic University of Catalonia

VHDL DESIGN FOR HIGH COMPLEXITY ALGORITHMS. OPTIMIZED 32-CHANNNELS ADPCMTRANSCODER (G.726) MODULE DESIGN 6 7 9

J.M. Hernandez and J. AmengualASICs Design. Access Systems Division. ALCATEL TELECOM

DESIGN'AND IMPLEMENTATION OF A DATA ACQUISITION AND GENERATING SYSTEM WITHPROGRAMMABLE SAMPLING RATE 6 8 3

I. Lacadena, J. Meneses, F. Moreno, D. MenciaO and J. Reyes(')E.T.S.I. Telecomunicacion. Universidad Politecnica de Madrid(*) IS2. Parque Tecnologico de Madrid

DES-CHIP 685J.A. Moran, J. M. Fernandez, S. Alexandres, J. Meneses, C. SantosO and J. M. Catenaf*)

Dpto. de Ingenieria Electronica. ETSI Telecomunicacion. Universidad Politecnica de Madrid

XVI

(*) Semiconductores Investigacion y Diseno S. A. Madrid

(") Sistemas Electronicos S. A.

Session 29: PARALLEL HARDWARE 689

Chairman: Eduardo Boemo. Universidad Autonoma de Madrid, Madrid

CONTROLLER FOR A FINE GRANULARITY MULTIPROCESSOR 691ARCHITECTUREJ.C. Moreno and A. Alcolea

Department of Electronics and Communications Engineering. University of Zaragoza

ARCHITECTURE AND MEMORY SYSTEM FOR THE SUCCESSIVE DOUBLING 697METHODM. Sanchez, J. Lopez and E. Lopez Zapata

Universidad de Malaga

ON THE DESIGN OF FPGA-BASED MULTIOPERAND PIPELINE ADDERS 7°1

M.A. Martinez, J.Valls and E.I. Boemo(*)

Departamento de Ingenieria Electronica. Universidad Politecnica de Valencia

(*) Escuela Tecnica Superior de Ingenieria Informatica. Universidad Autonoma de Madrid

Session 18: FPGA'S BASED SYSTEMS II 7 °7

Chairman: Emilio Olias. Universidad Carlos III, Madrid

RECONFIGURABLE FOVEAL SENSORS BASED ON FPGA'S 7 0 9

Pelegrin Camacho, F. Arrebola and F. Sandoval

Dpto. Tecnologia Electronica. E.T.S. Ingenieros de Telecomunicacion. Universidad de Malaga

FPGA IMPLEMENTATION OF FUZZY CONTROLLERS 715

E. Lago, M.A. Hinojosa, C.J. Jimenez, A. Barriga and S. Sanchez-Solano

Instituto de Microelectronica de Sevilla. Centro Nacional de Microelectronica

CONTRIBUTION OF FPGA TO FUZZY LOGIC ?21

G. Aranguren, L.L. Nozal and M. Barron

Electronics and Telecommunications Department. Universidad del Pais Vasco

A METHOD FOR TEMPERATURE MEASUREMENT ON RECONFIGURABLE SYSTEMS 7 2 7

S. Lopez-Buedo and E. Boemo

Laboratorio de Microelectr6nica. Escuela Tecnica Superior de Informatica. Universidad Autonoma deMadrid

Session 25: DIGITAL SIGNAL PROCESSING 7 3 1

Chairman: Emilio Lopez Zapata. Universidad de Malaga, Malaga

XVII

PIPELINED SUBMODULAR ISOMORPHIC MAPPED RNS 733MULTIPLIERSA. Garcia Rios and A. Lloris RuizDepartment of Electronics and Computer Technology. University of Granada

A SCALING SCHEME BASED IN CONVENTIONAL RNS ARITHMETICAL 739CIRCUITSA. Garcia Rios and A. Lloris RuizDepartment of Electronics and Computer Technology. University of Granada

A MICROELECTRONIC CORE FOR A PROGRAMMABLE DIGITAL HEARING 7 45AIDJ.A. Hidalgo, A. Daza, A. Oballe, J.C. Tejero and A. GagoDept. de Electronica. E.T.S. Industriales. Universidad de Malaga

Session 16: SPECIAL PROCESSORS AND COPROCESSORS 751Chairman: Walter Stechele. TUM, Munich

THREE-DIMENSIONAL ROTATION BASED ON GENERAL PURPOSE 3D CORDIC 753ALGORITHM....D. Reche Martinez, J. Villalba Moreno and E. Lopez ZapataDpto. de Arquitectura de Computadores. Universidad de Malaga

FPGA IMPLEMENTATION OF A VECTOR PROCESSOR FOR THE ESTIMATION OF HIGHER-ORDER 7 5 9

MOMENTSJ.C. Alves, A. Puga, L.Corte-Real and J.Silva MatosFEUP - Faculdade de Engenharia da Universidade do PortoINESC - Instituto de Engenharia de Sistemas e Computadores. Porto - Portugal

VLSI IMPLEMENTATION OF AN ARCHITECTURE FOR ANGLE COMPUTATION AND 7 65ROTATION...J.M. Calo, E. Antelo and J.D. BrugueraDept. Electronica e Computation. Universidad de Santiago de Compostela

AUTHORS LIST 7 7 1

XVIII