xfest2012 ppt video v1 2 may18 -...

AttentionAttention

The material contained in this presentation is the property of Avnet Electronics Marketing. Use of this material in it’s whole or in part is

Content is copyright by its original authors, and is used by permission This compendium is the property of Avnetg

restricted to Avnet’s X-Fest program and Avnet employees. Any use by non-Avnet employees outside of the X-Fest program is prohibited.

permission. This compendium is the property of Avnet Electronics Marketing and its X-fest partners. Use of this material in its whole or in part is restricted to Avnet’s X-fest

A t’ l th i i l i htFor additional information, please contact Jim Beneke at Avnet ([email protected]).

program, Avnet’s employees, or the original copyright owner.

For additional information or use requests, please contact Jim Beneke at Avnet ([email protected])

D i i Hi h Pi l R t Designing High Pixel-Rate Video Systems y

with Xilinx FPGAsFollow @avnetxfestTweet this event: #avtxfest www.facebook.com/xfest2012

3Course Objectives

At the end of the course, you will …– Understand how the Zynq™-7000 Extensible

Processing Platform (EPP) is the optimal platform for customizable high pixel rate video imaging andcustomizable high pixel-rate video, imaging and intelligent video systems

– Learn how Model-Based Design with MATLAB® and Simulink® can accelerate development of complex image processing algorithms

Copyright © 2011. Avnet, Inc. All rights reserved. Follow @avnetxfest | Tweet this event: #avtxfest

4Agenda

New Trends in Video

Zynq™-7000 Extensible Processing Platform (EPP)Your Intelligent Video Solution

Get Started Now with the Xilinx Zynq-7000 Video and Imaging Kity g g

Creating a Custom Video Accelerator using High-Level tool flowsg g


5New Trends in Video

High Pixel-Rate Video– Sharper images

=> higher video resolutionsMore responsive / capturing motion– More responsive / capturing motion => faster frame rates

Intelligent Video / Embedded Vision– Video system that isn’t a general purpose computer– Image sensor inclusive– Understands its environment through visual means


6High Pixel-Rate Video

A Video System with the following characteristics– Video throughput of 1080P60 or more

Video ThroughputTh h t Vid R l ti X F R t– Throughput = Video Resolution X Frame Rate

– Common Industry Benchmark = 1080P60• 1920 x 1080 pixels @ 60 frames/sec => 125 M pixels/sec1920 x 1080 pixels @ 60 frames/sec 125 M pixels/sec• 24bit RGB => 3 Gbits/sec

High Pixel-Rate >= 3Gbits/sec


7Video Resolution is Ever Increasing

1080P60 is pervasive7680x4320

Emerging standardsUHD (7680 × 4320)– UHD (7680 × 4320)

Provides sharper images

1920x1080

640x480

Provides sharper images– Find artifacts/features

HD imagers replacing SD cameras with Pan/Tilt/Zoom– The vision system is able to “see” the entire scene


– PTZ can be implemented digitally with video scaler

8Throughput is Ever Increasing

Throughput of imagers is growing exponentially

ec)

pixe

ls/s

el R

ate

(G

Pixe


9Capturing Motion – How Fast do I Need ?

Frame Rate

Event Duration Frame RateP W lki 1 30 f

– Depends on what you are observing

Person Walking 1 sec 30 fpsMachinery 250-500 msec 120 fpsMilkdrop 200 msec 250 fpsBlink of an eye 100 msec 500 fpsAirbag 30 msec 5000 fpsWelding 5 msec 15000 fpsWelding 5 msec 15000 fpsBallistics 100 usec 40000 fpsGlass crack 1 usec 250000 fps


10Capturing Motion – How to “Stop” the Motion

Exposure Time– Amount of time that the image sensor is “open” to

collect photonsframe time

exposure time

frame 0 frame 1 frame 2 frame 3

Trade-off between– receiving sufficient lighting


– obtaining a crisp image without any motion blur

11Capturing Motion – How to “Stop” the Motion

Global Shutter versus Rolling Shutter– Capture undistorted motion requires global shutter

rolling shutter

globalshutter


12Capturing Motion - Quiz

What’s wrong with this image ?– Motion blur– Exposure period is too long

What’s wrong with this image ?– Image distorted

What’s rong ith this image ?

g– Rolling shutter

What’s wrong with this image ?– Nothing, successful “stop motion”– Global shutter


Global shutter

13Challenges of Supporting High-Pixel Rate Video

The Challenges– Video Interfaces

• Custom interfaces• New emerging standards• New emerging standards• Multiple video interfaces (stereo, multi-view)• Sensor fusion (visible + IR/thermal)

– Video Processing• Custom hardware required to process HD images

7 S i P bl L i l th h ll !


7-Series Programmable Logic solves these challenges !

14Intelligent Video

Very hot topic in the industry !– expanding into many new application and markets

E b dd d Vi i Alli Embedded Vision Alliance– inspire and empower embedded system designers

to use embedded vision technologygy– http://www.embedded-vision.com

Video Content Analysis (VCA)– extract meaning from visual inputs


– break down images/videos into meta-data

15Intelligent Video – Typical Block Diagram

Intelligent Video Processing Pipeline

ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection




ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection

Image Acquisition– Parallel Interface (720P-1080P 30 frames/sec)Parallel Interface (720P-1080P, 30 frames/sec)– Serial Interface (1080P, 60 frames/sec or more)




ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection

Image Pre-Processing– Defect Pixel correctionDefect Pixel correction– Color Filter Array– Noise Reduction– Color Correction / Conversion– Gamma Correction




ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection

Feature Detection– TemplateTemplate– Edges– Corners– SURF, …– Motion




ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection

Feature Extraction/Matching– Identify areas which contain features of interestIdentify areas which contain features of interest– Assemble features together– Match groups of features with referencesg p




ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection

Object Detection / Tracking– Surveillance : people boundariesSurveillance : people, boundaries, …– Automotive : cars, signs, lanes, …– Industrial : bar codes, labels, …, ,


21Challenges of Implementing Intelligent Video

The Challengesg– Many vision functions will require highly parallel or

specialized hardware– Algorithms are diverse and dynamic, so fixed-

function compute engines are less attractive– Intelligent Video is being used in a broad range of– Intelligent Video is being used in a broad range of

new applications and markets requiring algorithms that are not yet available off the shelf

Z 7000 EPP l th h ll !


Zynq-7000 EPP solves these challenges !

22Agenda

New Trends in Video





23Introducing the Zynq™-7000 EPP

Complete ARM®-based Processing SystemDual ARM Cortex™ A9 MPCore™ processor centric– Dual ARM Cortex™-A9 MPCore™, processor centric

– Integrated memory controllers & peripherals– Fully autonomous to the Programmable Logic

7 SeriesProcessing Memory

Tightly Integrated Programmable Logic

– Used to extend Processing System

ProgrammableLogic

Common Peripherals

Custom

CommonPeripherals

ProcessingSystem

MemoryInterfaces

ARM®

Dual Cortex-A9 MPCore™ Systemg y

– High performance AXI based Interface– Scalable density and performance

Peripherals

Common AcceleratorsCustom Accelerators

Advantages for Video– Flexible I/O => Video Interfaces– Flexible Memory => Video Storage

DSP P f Vid P i


– DSP Performance => Video Processing

24Flexible I/O => Video Interfaces

54 Dedicated Peripheral I/Osintegrated peripherals

Configuration InterfacesI2C SPI– integrated peripherals

– I2C, SPI, USB, SD Card, Ethernet

350 Multi-Standard and

– I2C, SPI– USB

Parallel/Serial Interfaces350 Multi Standard and High Performance I/O

– Up to 200 3.3V capable multi-standard I/O

Parallel/Serial Interfaces– DVI, HDMI– CameraLink– CoaXPress

– Up to 150 high performance I/O

High Performance IntegratedS i l T i

– Serial LVDS, HiSPI, MIPI

High-Speed Serial InterfacesSerial Tranceivers – Two largest devices only – Up to 16 transceivers– Up to 12 5 Gbps

g p– DisplayPort– 3G-SDI


– Up to 12.5 Gbps

25Flexible I/O – Customize your Video System

DDR3

S AXI4 HPProcessing Processing SystemSystem DDR Memory Controller

AMBA® Switcheses

M_AXI4_GP

S_AXI4_HPx

AXI4 Stream

APUDual Core

Cortex-A9 + OCM

BA

®Sw

itcheHardened

Peripherals (USB, GigE, CAN, SPI, UART,I2C,

GPIO)

AM

BGPIO)

VIDEOINPUT

VIDEOOUTPUTVIDEO

INPUTVIDEOINPUT

VIDEOOUTPUTVIDEO

OUTPUT


26Flexible Memory => Video Storage

BRAMExtensible Block RAM (36 Kb Blocks)

Video Line BuffersHD video line:– Extensible Block RAM (36 Kb Blocks)

– Up to 545 Block RAMs (2,180KB)– HD video line:

– 1920 * 32 bits = 61Kb– 2 Block RAMs

Dedicated Memory Controller– DDR3 / DDR2 / LPDDR2 Memory– Configurable as 16bit or 32bit

Video Frame Buffers– HD video frame storage

– 1920 * 1080 * 32 bits – Up to 1Gbit of storage– Up to 32Gbps of bandwidth– Accessible by the fabric using

high performance AXI interconnect

= 66Mb– 16 video frames

– HD video frame bandwidth1920 * 1080 * 32 bits * 60 fpshigh-performance AXI interconnect – 1920 * 1080 * 32 bits * 60 fps= 4 Gbps

– 8 video streams (peak)


27Flexible Memory – Video Frame Buffer

DDR3

S AXI4 HP

video frame buffers

Processing Processing SystemSystem DDR Memory Controller

AMBA® Switcheses

M_AXI4_GP

S_AXI4_HPx

AXI4 Stream

APUDual Core

Cortex-A9 + OCM

BA

®Sw

itcheHardened


GPIO)

AM

BGPIO)

VIDEOINPUT

VIDEOOUTPUT

AXIVDMA

P i S t ’ M i Ti htl C l d ith F b i !


Processing System’s Memory is Tightly Coupled with Fabric !

28DSP Performance => Video Processing

Up to 5 million ASIC gates900 DSP48 Sli

Video AcceleratorsImage Processing Pipeline 900 DSP48 Slices

– 2 DSP48E1 Slices / Tile– 638 MHz Fmax

1080 GMACs of

– Image Processing Pipeline– Video Scaling, OSD, …– Feature Detection– Feature Extraction 1080 GMACs of

DSP Processing Performance


29DSP Performance through Parallelism

Fully Fully Parallel ImplementationParallel Implementation(Zynq(Zynq--7000 EPP)7000 EPP)

Sequential Sequential (Standard(Standard DSPDSP Processor)Processor)

CoefficientsCoefficients

Data InData In

XX

(Zynq(Zynq--7000 EPP)7000 EPP)

Data InData In Reg

Reg

Reg

Reg

Reg

Reg

Reg

Reg

(Standard (Standard DSP DSP Processor) Processor)

SingleSingle--MAC UnitMAC Unit

CoefficientsCoefficients

50 50 clock clock cycles cycles

d dd d

XX

++5050 operationsoperations

XX

++

C0C0 C0C0XXC1C1 XXC2C2 XXC3C3 XXC57C57…

Data OutData Out

neededneededRegReg

Data OutData Out

50 50 operations operations in 1 clock cyclein 1 clock cycle

1.2 GHz50 clock cycles

= 24 MSPS638 MHz

1 clock cycle= = 638 MSPS


Zynq-7000 Delivers up to 1080 GMACs of DSP Performance

30Video IP – Don’t Re-Invent the Wheel !

ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection

Ready to use IP for common video functionsXilinx Video and Imaging Processing Pack

Chroma Resampler GAMMA Correction Motion Adaptive Noise ReductionChroma Resampler GAMMA Correction Motion Adaptive Noise Reduction

Color Correction Matrix Image Characterization Object Segmentation

Color Filter Array Interpolation Image Edge Enhancement On-Screen Display

Deinterlacer Image Noise Reduction Video DMA

Defective Pixel Correction Image Statistics Engine Video Controller

AXI Video DMA RGB to YCrCb Color-Space Converter YCrCb to RGB Color-Space Converter

Additional IP available through Alliance Partners Cycle-accurate C models for all Xilinx Video IP


Xylon: LogicBRICKS

31Video IP - Intelligent Video Use Case

S AXI4 HP

ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection


AMBA® Switcheses

M_AXI4_GP

S_AXI4_HPx

AXI4 Stream

APUDual Core

Cortex-A9 + OCM

BA

®Sw

itcheHardened


GPIO)

AM

BGPIO)

MOTIONVIDEO IMAGE

AXIVDMA

AXIVDMA

OBJECT

AXIVDMA

IMAGE VIDEOOSDIMAGE


MOTIONADAPTIVE NR

VIDEOSCALER

IMAGECHARACT.

OBJECTSEGMENT.

IMAGESENSOR

VIDEOOUTPUT

OSDIMAGEPIPELINE

32Agenda

New Trends in Video





33Xilinx Zynq-7000 Video and Imaging KitEnabling High-Definition Video and Image Processing Applications

Hardware Reference Designs– Xilinx ZC702 Baseboard– Avnet FMC Image-ON module

• HDMI Input/Output

g– Software Video Processing

with Hardware Acceleration– Video Scaler/OSD• HDMI Input/Output

• 1080P60 Image Sensor

Development Tools

Video Scaler/OSD– Real-Time Camera

p– Xilinx Video IP (hardware eval)– Xilinx ISE® Design Suite

Embedded Edition

Software– Linux

FreeRTOS


– FreeRTOS

34ZC702 Baseboard

FPGA– Z7020 CS484– Z7020 CS484

Communication– Gb Ethernet– Host USB– Host USB

Video/Display– HDMI Output (1080P60)

DDR3 Memory DDR3 Memory– Total Size = 1Gb

• 16 frames of 1080P video (32 bit pixels)– Bandwidth = 32 pins @ 1066 Mbps = 32 GbpsBandwidth 32 pins @ 1066 Mbps 32 Gbps

• assuming 75% efficiency (24 Gbps),6 streams of 1080P60 video (32 bit pixels)


35FMC Module

ON Image Sensor FMC Module– Low Pin Count (LPC) FMC – HDMI Input/Output

C bl I t f t I S– Cable Interface to Image Sensor


36HDMI Input/Output

HDMI Input Interface– Analog Devices ADV7611 (non-HDCP device)

• 1080P60 capable• 16 bits YCbCr 4:2:2, embedded syncsy

HDMI Output Interfaces (x2)– Analog Devices ADV7511

1080P60 bl• 1080P60 capable• ZC702 : 16 bits YCbCr 4:2:2, separate syncs• FMC : 16 bits YCbCr 4:2:2, embedded syncs

Linux Drivers– Standard Linux drivers for video (v4l2, fbdev)

Standard Linux drivers for audio (alsa)


– Standard Linux drivers for audio (alsa)

37Application Specific Cabling Solution

LCD Coaxial Embedded Display Interface(LCEDI)– Allows very flexible placement of image sensor– Avnet/TE developed application specific solutionAvnet/TE developed application specific solution

Exceptional electrical performance for– Serial LVDS– eDP (2.7 Gbps per lane)

Avnet LCEDI Cable– 12 single-ended signals12 single ended signals

• ref clk, triggers, SPI– 10 differential pairs

lk d t [7 0]


• clk, sync, data[7:0]

38VITA Image Sensor

VITA family overview– high pixel-rate image sensors– global shutter and rolling shutter– scalable to higher resolutions and frame ratesscalable to higher resolutions and frame rates– 10 bit pixels

Image Sensor Active Area Frame Rate ThroughputVITA-1300 1280 x 1024 150 fps 2.5 GbpsVITA-2000 1920 x 1200

640x480256 256

92 fps555 fps1730 f

2.5 Gbps

256x256 1730 fpsVITA-5000 2592 x 2048 75 fps 5 GbpsVITA-25K 5120 × 5120 53 fps 20 Gbps


VITA-2000 included in kit (chosen for 1080P60 capability)

39Video Processing with Acceleration

Objectivebl S f U d l H d l d– enable Software Users to develop Hardware accelerated

applications– Real-time demonstration of hardware acceleration

Demonstrations– Sobel filter in software

• CPU utilization during Software Sobel is 100%• CPU utilization during Software Sobel is 100%• 1080P video at 6 frames per second

– Accelerate Sobel filter in hardwareCPU tili ti i <5% d i H d S b l• CPU utilization is <5% during Hardware Sobel

• 1080P video at 60 frames per second


Enabling the Software User

40Video Processing with Acceleration

S AXI4 HP

DDR3


AMBA® Switcheses

M_AXI4_GP

S_AXI4_HPx

AXI4 Stream

APUDual Core

Cortex-A9 + OCM

BA

®Sw

itcheHardened


GPIO)

AXIVDMA

SOBELFILTER

AM

BGPIO)

HDMIINPUT

HDMIOUTPUT

AXIVDMA

CVC GraphicsController

AXITPG


41Real-Time Camera Processing

Objective

ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection

j– Demonstration and Evaluation of Xilinx Image Processing IP

cores1080P60 C R f D i– 1080P60 Camera Reference Design

Demonstration:– VITA-2000 image sensorVITA 2000 image sensor– Xilinx Image Processing Pipeline– Linux Application with Web-based GUI

C fi i f i i i li• Configuration of image processing pipeline cores• Application examples for auto white-balance, auto gain• Capture image through the network


Development platform for front-end image processing

42Real-Time Camera – Block Diagram

Processing

DDR3

Firmware gSystem DDR Memory Controller

AMBA® Switches

ches

Hardened

M_AXI4_GP

S_AXI4_HPx

AXI4 Stream

on SD Card

APUDual Core

Cortex-A9 + OCMA

MB

A®

SwitcPeripherals

(USB, GigE, CAN, SPI, UART,I2C,

GPIO)

PC runningWeb-based GUI

A

CAMERAINPUT

HDMIOUTPUT

AXIVDMA

IMAGEPROCESSING

PIPELINE

VITA-2000 CameraHDMI Monitor

Programmable Logic


HDMI Monitor

43Real-Time Camera - Image Acquisition

ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection

VITA Receiver - Serial LVDS De-SerializerSerial LVDS @ 620Mbps

Sync

62MHz 62MHz 248MHz

VITA2000

SerialLVDS

Receiver

SYNC

DATA

yDecoder

& CRC

Checker

DATA(40bits)

SYNC

DATA(40bits)

SYNC

4:1PIXEL(10bits)

SYNC

HDL Simulation Testbench

SYNC SYNC(10 bits)

SYNC SYNC

– Support for ISIM (Xilinx), Active HDL (Aldec)


44Real-Time Camera – Image Proc. Pipeline

ImageAcquisition

Image PreProcessing

Feature Detection

FeatureMatching

ObjectDetection

Processing System (PS)ZVIK Camera Linux ApplicationGain

Control

AutoE

AutoGain

Global Contrast

Auto White

ExposureControl

ImageStatistics

ZVIK Web CGILinux Application

ControlBrowser

NetworkExposure ContrastWhite Balance

Control StatisticsHandler

Linux Kernel

Control Network

Image Statistics

AXI4-Lite Add your custom IP here !

Color FilterArrayInterpolation

EdgeEnhance

NoiseReduction

DefectivePixelCorrection

Color Correction Matrix

GamaCorrection

CameraInput

Programmable Logic (PL)

Display


Video and Image Processing Pack Drivers / Application Examples (Linux)

45Agenda

New Trends in Video





46AutoESL Design Flow

QoR that rivals hand coded RTLFast compilation and design exploration– Fast compilation and design exploration

– Algorithm feasibility– Architecture exploration

Comprehensive coverageComprehensive coverage– C/C++/SystemC– Arbitrary precision– Floating-pointg

Accelerated verification– 2 to 3 orders of magnitude faster

than RTL for larger design

Customer proven results


47Model-Based Design with MATLAB/Simulink

Abstract Modeling EnvironmentBehavioral implementations– Behavioral implementations

– Not locked to software of hardware implementations– True algorithm exploration

Code GenerationCode Generation– Embedded Coder– HDL Coder

MathWorks solutions for Intelligent VideoMathWorks solutions for Intelligent Video– Image Acquisition Toolbox

• Image acquisition and pre-processing

– Computer Vision System Toolbox– Computer Vision System Toolbox• Feature detection, feature matching, object detection

– Statistics Toolbox• Feature classification


48Computer Vision System Toolbox

Key Features– Feature detection:

• HARRIS, SURF, MSER

– Feature matchingg– Object detection and tracking

• Viola-Jones detection, CAMShift tracking

– Motion estimationMotion estimation• block matching, optical flow, and template matching

– RANSAC-based estimation of geometric transformations or fundamental matrices

htt // th k / d t / t i i /


http://www.mathworks.com/products/computer-vision/

49MathWorks Design Flow for Zynq EPP

Algorithm Model

Embedded

Software Model Hardware Model

HDL CoderCoder

C code

HDL Coder

RTL code

Zynq Template

Xilinx EDK

Development


Development Board

50Next Steps

Buy the Zynq-7000 Video and Imaging Kit– On-Line tutorials

X-Fest courses: – Software Acceleration in Zynq™-7000

Xilinx Customer Education Courses:Zynq 7000 EPP for System Architects– Zynq-7000 EPP for System Architects

– Embedded Systems Software Design– Advanced Features and Techniques of Embedded Systems Design– DSP Design Using System Generator

Attend a Speedway


51Demos

Avnet booth– Real-Time Camera reference design demo

Xilinx booth– Video Processing with Acceleration demo

Analog Devices boothZynq running Linux with ADV7511 HDMI transmitter– Zynq running Linux with ADV7511 HDMI transmitter

MathWorks booth– Model-Based Design with MATLAB/SimulinkModel Based Design with MATLAB/Simulink– Computer Vision System Toolbox


Appendixpp

Follow @avnetxfestTweet this event: #avtxfest www.facebook.com/xfest2012

53Zynq-7000 EPP - Target Markets


High Pixel-Rate Camera DemogAppendix Slides


55Zynq-7000 High Pixel Rate Camera Demo

PurposeShow a web controlled Image Processing Pipeline– Show a web controlled Image Processing Pipeline running on the Xilinx Zynq Video and Imaging Kit

K M Key Messages– The Zynq device is ideally suited for video processing– The Zynq Video Kit is a great way to explore the videoThe Zynq Video Kit is a great way to explore the video

processing capabilities of Zynq– Xilinx provides several key video IP blocks to speed your

design effortsdesign efforts– The Avnet On-Semi FMC module included in the kit

provides a high-performance image sensor camera along


with HDMI I/O


Real-time camera i tprocessing setup



Processing

DDR3

Firmware Processing System DDR Memory Controller

AMBA® Switches

hes

Hardened

M_AXI4_GP

S_AXI4_HPx

AXI4 Stream

on SD Card

APUDual Core

Cortex-A9 + OCMM

BA

®Sw

itchHardened


GPIO)

PC runningWeb-based GUI

AM

CAMERAINPUT

HDMIOUTPUT

AXIVDMA

IMAGEPROCESSING

PIPELINE

VITA-2000 CameraProgrammable Logic


HDMI Monitor


Processing System (PS)

Xilinx Image Processing IP Cores & Example Application

ZVIK Camera Linux ApplicationGain

Control

AutoE

AutoGain

Global Contrast

Auto White

ExposureControl

ImageStatistics

ZVIK Web CGILinux Application

ControlBrowser

Network

Exposure ContrastWhite Balance

Control StatisticsHandler

Linux Kernel

Image Statistics

AXI4-Lite Add your custom IP here !

Color FilterArrayInterpolation

EdgeEnhance

NoiseReduction

DefectivePixelCorrection

Color Correction Matrix

GamaCorrection

CameraInput

Programmable Logic (PL)

Display


Video and Image Processing Pack Drivers / Application Examples (Linux)

Video Proc. With Accel. DemoAppendix Slides


61Zynq Video TRD

PurposeShowcase Zynq 7000 EPP ZC702 Evaluation Kit– Showcase Zynq-7000 EPP ZC702 Evaluation Kit video capability

Key Messagesy g– Highlights hardware acceleration of a video

applicationHi hli ht id i f 1080P60 id– Highlights video processing of a 1080P60 video stream

– Runs under embedded LinuxRuns under embedded Linux– Similar to Zynq-7000 EPP Video and Imaging Kit

which uses same TRD interfaced to a 1080P60 image


sensor

62Zynq Video TRD

Demo utilizes ZC702 Evaluation Kit with Avnet HDMI In/Out FMC cardAvnet HDMI In/Out FMC card

Video source is a Roku player running Angry Birds– Output is 1080P60 HD Video

Demonstrates high performance fabric based offloading of processingbased offloading of processing functions

Software application developed using SDK d d LiSDK and runs under Linux

Hardware Accelerator developed in C using AutoESL High-Level Synthesis


g g y

63Zynq Video TRD

32-bit DDR3 – 533 Mhz(Max - 17 out of 32 Gbps)

Software Sobel built as a Linux applicationDesign feature highlights

667 MHz ARM

150 Mhz 64-bit AXI4 AFI HP1 Port(Using 4 Gbps out of max 9.6 Gbps) Platform comes

with Xylon Display C t llController


1080P60 Video Hardware Sobel Filter created using C with AutoESL HLS

64Zynq Video TRD

Sobel FilterSobel Filter Output

(Edge Detect)

Live Video Sobel Output on Video

10X Acceleration using Fabric (60 fps vs. 6 fps) CPU utilization during Software Sobel is 100%

CPU tili ti i 5% d i H d S b l CPU utilization is <5% during Hardware Sobel Enables more CPU time for customer application


TE ConnectivityyAppendix Slides


66Application Specific Cabling Solution

LCD Coaxial Embedded Display Interface – LCEDI– Allows very flexible placement of image sensor– Avnet/TE developed application specific solution

Image SensorHeadBoard

LCEDI

HDMIIN

HDMIOUT

FMC Carrier

FMC adapter

LCEDICabling Solution


67LCEDI Connector Features

LCEDI SR connectors are designed for system applications– Used on FMC-IMAGEON

P id ti l l t i l Provides exceptional electrical performance in both LVDS and eDPapplications– 2.7 Gbps per lane per eDP standard

Foot Print Compatible with I-PEX “FPL” C“FPL” Conn

Mating Height :– 9 35mm at 44P (With screws)


– 9.35mm at 44P (With screws)

68LCEDI Cabling Features and Benefits

Mixed Cable UseTypical COAX Cable Assembly

– Micro Coax• Twin Coax AWG 40 or smaller• Ideal for differential signal (LVDS)Cable Pinout COAX and Discrete• Ideal for differential signal (LVDS)• Different impedances available

– 42.5Ω, 50Ω, etc.

Cable Pinout – COAX and Discrete

– Discrete Wire • AWG 32 Teflon or smaller• Designed for digital signals and powerDesigned for digital signals and power

Better Shielding Effectiveness with Upper/Lower Shell Construction


Allows assembly flexibility

Analog DevicesgAppendix Slides


Th W ld L d i Hi h P f Si l P i S l tiThe World Leader in High-Performance Signal Processing Solutions

Analog Devices Video Products

March 7, 2012

—Analog Devices Confidential Information—


Video Input Products


Video Input Product Selection GuideS E L E C T

Analog Features ADV7180 ADV7180 ADV7180 ADV7180 ADV7181C ADV7184 ADV7188 ADV7401 ADV7403 ADV7441A ADV7802 ADV7800 ADV7844 ADV7842Digitizer Speed (MSPS) 86 86 86 86 110 54 54 140 140 170 150 150 170 170Max Component Format 480i/576i 480i/576i 480i/576i 480i/576i 720p/1080i 480i/576i 480i/576i 720p/1080i 720p/1080i 1080p 60 1080p 60 1080p 60 1080p 60 1080p 60Max VGA Format SXGA SXGA SXGA UXGA SXGA SXGA UXGA UXGAAnalog Input Channels 6 3 6 3 6 12 12 12 12 12 12 12 12 12YPbPr

2D Y/CVideo Decoders

3D Y/CVideo Decoders

RGBHDMI FeaturesInput Ports 2 4 212‐bit Deep Colour InputFast‐Port‐SwitchingSupport mandatory 3D formatsAudio Channel Return (ARC)Ethernet (HEC)+5V DetectionHot‐Plug DetectionCECEDID readback using HDMI +5VEDID Size 256 bytes 512 bytes 512 bytesIEC60958 PCM compatible 8‐channel 8‐channel 8‐channelIEC61937 compressed audio compatibleDSD (Direct Stream Digital) 6‐Channel 6‐ChannelDST (Direct Stream Transfer)HBR (High Bit Rate)I2S 4 Outputs 4 Outputs 4 OutputsSPDIF (* Outputs 1‐4 shared with I2S pins) 1 Output 5 Outputs* 5 Outputs*Repeater Software EnabledHDMI Monitoring + Analog Input 2 port 2 portHDMI Monitoring + Analog Input 2 port 2 portBoth HDCP Key and Non‐Key Versions

Decoder Features3dD Comb Feature3D Noise Reduction (DNR)Time‐Base‐Corrector (TBC)Line‐Doubler (480i‐>p)Parallel Digital Input PortAnalog Monitor Output

SDRAM Memory TypeSDR/DDRExternal

SDR/DDRExternal

SDR/DDRExternal

SDR/DDRExternal

SDRAMSi 64Mbi 64Mbi 64Mbi 64MbiSDRAM Size ≥ 64Mbit ≥ 64Mbit ≥ 64Mbit ≥ 64Mbit

RGB SCART SupportSimultaneous SD/PS Output

Other FeaturesMax Output Data Resolution 8‐bit 8‐bit 8‐bit 8‐bit 10‐bit 8‐bit 10‐bit 8‐bit 10‐bit 10‐bit 12‐bit 12‐bit 12‐bit 12‐bitPixel Bus Width 16‐bit 8‐bit 8‐bit 8‐bit 20‐bit 16‐bit 20‐bit 24‐bit 30‐bit 30‐bit 48‐bit 36‐bit 36‐bit 36‐bitIntergrated OSD SupportRecommened for AutomotiveNDA Required

PackageType 64‐QFP 40‐LFCSP 48‐LQFP 32‐LFCSP 64‐QFP 80 LQFP 80 LQFP 100‐QFP 100‐QFP 144‐QFP 176‐QFP 176‐QFP 425‐BGA 256‐BGA


Size (mm) 10 x 10 6x6 7x7 5x5 10 x 10 14 x 14 14 x 14 14 x 14 14 x 14 20 x 20 24 x 24 24 x 24 19 x 19 17x17Temp Range (deg C) (Consumer) ‐40 to +85 ‐40 to +85 ‐10 to +70 ‐40 to +85 ‐40 to +85 ‐40 to +85 ‐40 to +85 ‐40 to +85 ‐40 to +85 0 to +85 0 to +85 0 to +70 0 to +70Temp Range (deg C) (Automotive) ‐40 to +125 ‐40 to +125 ‐40 to +85 ‐40 to +85 ‐40 to +85

StatusSamples Released Released Released Released Released Released Released Released Released Released Released Released Released ReleasedMP Released Released Released Released Released Released Released Released Released Released Released Released Released Released

Standalone HDMI Receiver Selection Guide S E L E C T

ADV7611 ADV7612 ADV7619 AD9393

General FeaturesHDMI Input Ports 1 2 2 1Max Speed (MHz) 165 225 300 80Xpressview Fast SwitchingXpressview Fast SwitchingSupport mandatory 3D formatsSupport 4K x 2K12‐bit Deep Colour Inputx.v.Color+5V and Hot‐Plug DetectionCECEDID read from +5VStereo AudioMulti‐Channel I2S OutputSPDIF OutputHi h Bit R t A di S tHigh‐Bit‐Rate Audio SupportRepeater Software EnabledBoth HDCP Key and Non‐Key Versions Non key

Data OutputsMax Output Data Resolution 8‐bit TTL 12‐bit TTL 12‐bit TTL 8‐bitPixel Bus Width 24‐bit 36‐bit 48‐bit 24‐bitPixel Bus Width 24 bit 36 bit 48 bit 24 bitAutomotive GradeNDA Required

PackageType 64‐LQFP 100‐LQFP 100‐LQFP 76‐BGASize (mm) 10x10 14x14 16x16 6x6


Temp Range (deg C) ‐40 to +85 ‐40 to +85 ‐40 to +85 ‐10 to +85StatusSamples Released Released Released ReleasedMP Released Released Released Released

ADV7842 – 3D Video Decoder & 2:1 HDMI Rx

S E L E C T

SDRAMDDR-RAM

Key Features

Digital Clock Synthesis

ADCsInputMux

Output

AIN1-9

SYNC 1/2 36-bit

SD Processor3D CombFrame Sync Line

Doubler

HDMI 225 MHz DDeeeepp CCoolloorr 33DD formats: All mandatory formats (v1.4a)

DPLLComponentProcessor

BackendCSC

DataPreprocessor

DPP

Video

OutputFormatter

ControlI2C

HS/VS

CECCEC

TTLSYNC

I2C

All mandatory formats (v1.4a) Many other formats

Xpressview™ HDCP switching CEC command buffer Hot Plug Assertion

HDMIProcessor

AudioController

Data ProcessorVDP

Port Mux&

Cable EQ

HDMI1-2

C C

4x I2SSPDIF

FastSwitch

Hot-Plug Assertion (open drain output)

Expanded Colorimetry Analog

Y/C 3D C b filt iHDCP Engine

EDIDReplicatorController

PacketInfoframeMemory

HDCPKEYS

DDC+5VHPA

Y/C 3D-Comb filtering 170 MSPS 12b ADCs EDID for VGA input

(shares with HDMI EDID) Part HDCP Package Op Temp


g p pADV7842KBCZ-5 yes 17 mm 1 mm ¢

BGA 256-ball–10 ~ 70 °C

ADV7842KBCZ-5P no

ADV7844 – 3D Video Decoder & 4:1 HDMI

S E L E C T

Rx Key Features

HDMIStandardDefinition

SDRAMDDR-RAM

HDMI 225 MHz DDeeeepp CCoolloorr 33DD formats:

All mandatory formats (v1.4a) Many other formats Digital Clock Synthesis

ADCInputMux

AIN1-12

SYNC 1 4 36 bit

DefinitionProcessor

3DYCFrame Sync

LineDoubler

Many other formats AŘC support Xpressview™ HDCP

switching All 4 ports: Any↔Any

Digital Clock SynthesisDPLL

TrilevelSlicer

ComponentProcessor

BackendCSC

DataPreprocessor

DPP

Video

OutputFormatter

ControlI2C

TRI

1-6

SYNC 1-4HS/VS 1-2

CECCEC

36-bitTTLSYNC

po s y y CEC command buffer Hot-Plug Assertion

(open drain output) Expanded Colorimetry

HDMIProcessor

AudioController

VideoData Processor

VDPPort Mux

&Cable EQ

HDMI1-4

6 CECCEC

4x I2SSPDIF

FastSwitch

p y Analog

Y/C 3D-Comb filtering 170 MSPS 12b ADCs EDID for VGA input

HDCP EngineEDID

ReplicatorController


HDCPKEYS

DDC+5VHPA

Part HDCP Package Op Temp


EDID for VGA input (shares with HDMI EDID)

g p p

ADV7844KBCZ-5 yes 19 mm 0.8 mm ¢ BGA 425-ball 0 ~ 70 °C

ADV7611 Low Power HDMI RxS E L E C T

Single input HDMI Rx Low power for portable Low power for portable

applications Integrated CEC Controller HDMI 1 4 3DTV formats


ControlI2C

SyncProcessing

Component

Backend CSC O

utput Form

Video

Data Preprocessor

&Color Space

HDMI 1.4, 3DTV formats Up to 165 MHz

1080p/60 & UXGA 127 KSVs supported

HDMIProcessor

AudioPacket

Processor

I2C

CEC

HDMI

CEC

ComponentProcessor

matter

o

HDMI Port&

Cable EQ

Converter

Audi 127 KSVs supported

S/PDIF & I2S (stereo) TDM 4 I2S stereo ch’s

SACD

HDCP Engine

Processor


HDCPKEYS

DDC

Q io

SACD DSD output interface

Compressed SACD DST output interface Part HDCP Key Package Op Temp


p High bit rate audio ADV7611BSWZ yes 12 mm 0.5mm ¢

LQFP 64-pin–40 ~ 85 °C

ADV7611BSWZ-P no

ADV7612 – 2:1 HDMI RxS E L E C T


Data Preprocessor

&

SyncProcessing

Backend CSC O

utput

P0 – P35LLCHS

HDMIAudioPacket

ControlI2C

Port Mux&

CEC

&Color Space

Converter

Port AP B

CECComponentProcessor

Formatter

HSVS_FIELDDE

I2S0 /DSD0 B/ HBR0I2S1 /DSD1 A/ HBR1

Processor

HDCP Engine

PacketProcessor



HDCPKEYS

&Cable EQ

Port B

DDC ADDC B

FastSwitchBetween All Inputs

S / S /I2S2 /DSD2 B/ HBR2I2S3 /DSD3 A/ HBR3LRCLK /DSD2B / DST_FFSCLK / DST_CLKMCLKOUT

2 input HDMI 1.4 Rx at 225 MHz Xpressview™ fast switching

4 stereo I2S channels SACD – DSD output interface

C d SACD DST t t i t f

SPDIF / DSD0A / DST

127 KSVs supported 3DTV support Integrated CEC Controller S/PDIF digital audio input

Compressed SACD – DST output interface High bit rate (HBR) audio



S/PDIF digital audio inputADV7612BSWZ yes 16 mm 0.5mm ¢

LQFP 100-pin–40 ~ 85 °C

ADV7612BSWZ-P no

ADV7619 – 2:1 HDMI Rx for 4K×2K

S E L E C T

resolutionDigital Clock SynthesisDPLL

Data Preprocessor

&C l S

SyncProcessing

Backend CSC O

utput F

P0 – P47LLCHS

HDMIProcessor

AudioPacket

ControlI2C

Port Mux&

CEC

Color SpaceConverter

Port AP t B

CECComponentProcessor

ormatter

HSVS_FIELDDE

I2S0 /DSD0 B/ HBR0I2S1 /DSD1 A/ HBR1

Processor

HDCP Engine

Processor



HDCPKEYS

Cable EQPort B

DDC ADDC B

FastSwitchBetween All Inputs

I2S2 /DSD2 B/ HBR2I2S3 /DSD3 A/ HBR3LRCLK /DSD2B / DST_FFSCLK / DST_CLKMCLKOUTSPDIF / DSD0A / DST

2 input HDMI 1.4 Rx at 300 MHz TMDS Double-wide 48-bits (running at 150 MHz)

output

High speed resolution supports 3DTV formats up to 1080p/60 full resolution 4K×2K resolution at 30 Hz

SPDIF / DSD0A / DST

Xpressview™ fast switching 127 KSVs supported Integrated CEC controller S/PDIF digital audio input

SACD – DSD output interface Compressed SACD – DST output interface



4 stereo I2S channels High bit rate (HBR) audio

ADV7619KSVZ yes 16 mm 0.4 mm ¢ TQFP 128-pin 0 ~ 70 °C

ADV7619KSVZ-P no

S E L E C T

ADV7622/ADV7623 HDMI Transceivers

Four HDMI Inputs One HDMI Outputp p Fast Switching Among All Inputs (ADV7623 only) Hardware Accelerated HDCP Repeater Engine HDCP 1.3 Encoding and Decoding HDMI 1 4a 3D TV format support HDMI 1.4a 3D TV format support Up to 225MHz TMDS clock Character-Based OSD (ADV7623 only) 8 Channel I2S and S/PDIF Audio I/O


ADV7622BSTZ yes 22 mm


Supports S/PDIF Audio Return Channel (ARC) Integrated CEC Controller EDID Replicator

0.5mm ¢ LQFP 144-pin

0 ~ 70 °CADV7623BSTZ yesADV7623BSTZ-P no


Video Output Products


Digital Video Transmitter Selection GuideHDMI Tx + MIPI‐DSI Rx

ADV7533 ADV7523A ADV7527 ADV7525 ADV7524A ADV7526 ADV7541 ADV7511 ADV7513 ADV7511WRecommended for New Designs ?Input PortsTTL parallel interface width ‐ 16 16 24 16 24 16 36 24 24

HDMI Tx(Home/Pro AV)

HDMI Tx(Camera & Portable)

RGB 4:4:4 12‐bit DDR 12‐bit DDR as 12b DDR as 12b DDRYCbCr 4:4:4 12‐bit DDR 12‐bit DDR up to 720p60 up to 720p60YCbCr 4:2:2

Output PortsHDMI output

HDMI FeaturesHDMI Version 1.4a 1.4a 1.4a 1.4a 1.4a 1.4a 1.4a 1.4a 1.4a 1.4aMax Pixel clock 80 MHz 80 MHz 80 MHz 80 MHz 150 MHz 150 MHz 150 MHz 225MHz 165 MHz 165 MHzOn‐chip HDCP supportHDCP Version 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3Support for CEA‐861D video formatsVideo Resolution 720p/1080i 720p/1080i 720p/1080i 720p/1080i 1080p 1080p 1080p 1080p 1080p 1080p12‐bit Deep Colour support 12‐bit to 1080i including 444Extended Colorimetry (x,v,Color™)

b dd dITU656 Embedded Syncs3D Ready720p/1080i1080p241080p24/25/30

Max Graphics Resolution XGA 75Hz XGA 75Hz XGA 75Hz XGA 75Hz SXGA 75Hz SXGA 75Hz SXGA 75Hz UXGA UXGA 60Hz UXGA 60HzColor Space Conversion Prog Prog Prog Prog Prog Prog Prog Prog/Auto Prog/Auto Prog/AutoCEC supportCEC supportIntegrated I2C master for DDC bus+5v Tolerant I/O for HPD and I2CI2S channels 2 2 2 8 2 8 2 8 8 8SPDIF

PackageType 49‐WLCSP 49‐WLCSP 49‐WLCSP 64‐WLCSP 49‐WLCSP 64‐WLCSP 49‐WLCSP 100‐LQFP 64‐LQFP 64‐LQFPSize (mm) 3 5 x 3 5 3 5 x 3 5 3 x 3 3 5 x 3 5 3 5 x 3 5 3 5 x 3 5 3 5 x 3 5 16 x 16 12 x 12 12 x 12


Size (mm) 3.5 x 3.5 3.5 x 3.5 3 x 3 3.5 x 3.5 3.5 x 3.5 3.5 x 3.5 3.5 x 3.5 16 x 16 12 x 12 12 x 12Lead pitch (mm) 0.5 0.5 0.4 0.4 0.5 0.4 0.5 0.5 0.5 0.5Temp Range (deg C) ‐10 ~ +85 ‐25 ~ +85 ‐25 ~ +85 ‐25 ~ +85 ‐25 ~ +85 ‐25 ~ +85 ‐25 ~ +85 0 ~ +70 ‐25 ~ +85 ‐40 ~ +105

StatusSamples Released Released Released Released Released Released Released Released Released ReleasedMP Released Released Released Released Released Released Released Released Released Released

ADV7511: High Performance HDMI™ v1 4- TransmitterHDMI™ v1.4- Transmitter Supports display resolutions at 25~225 MHz

(up to 1080p deep color) Incorporates extended HDMI v1.3/1.4 features Audio

Data4:2:2

MCLKI2S[3:0]

S/PDIF

CEC CECInterpreter CEC

HDCPKeys*

DDeeeepp CCoolloorr support (12-bit 4:4:4) Supports extended colorimetry (e.g.

x.v.ColorTM) HBR audio formats DST/DSD audio formats Audio Return Channel

DataCapture

VideoData

4:4:4&ColorSpaceConverter

HDCPEncryption

D[35:0]

SCLK

I S[3:0]LRCLK

T 1

Tx0VsyncHsync

Keys

Audio Return Channel 33DD Ready (720p50/60 & 1080p24/25/30)

Integrated CEC support Buffer CEC signals Off-loads real-time monitoring from host µP

L t db

DataCapture

Registers&Config.Logic

TMDSOutputsDE

CLK

HPDINT

Tx1

Tx2

TxC

Hsync

ARC Rx(SPDIF) ARC

Low standby power Software driver Easy implementation *Optional on-chip HDCP support Automated or programmable color space converter Flexible video inputs:

I2CSlave HDCP &

EDIDMicro-controller

I2CMaster

SCLSDA

DDCSDADDCSCL

p RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 36-bit input interface

Integrated I2C Master for DDC bus +5V tolerant I/Os for HPD and I2C 1 8V & 3 3V supplies Part HDCP Package Temp

—Analog Devices Confidential Information—82

1.8V & 3.3V supplies Part HDCP Package TempADV7511KSTZ Internal 16 mm 0.5 mm ¢

LQFP 100-pin Pb-free 0 ~ 70 °CADV7511KSTZ-P N/A

ADV7511W: High Performance HDMI™ 1 4 T itt f A t tiv1.4- Transmitter for Automotive

Supports display resolutions at 25~165 MHz (up to 1080p/UXGA)Automotive qualification (AEC-Q100, ADI0012)

I t d d HDMI 1 3/1 4 fAudioData

4:2:2

MCLKI2S[3:0]

S/PDIF


HDCPKeys*

Incorporates extended HDMI v1.3/1.4 features Supports extended colorimetry (e.g. x.v.ColorTM) HBR audio formats DST/DSD audio formats 33DD Ready (720p50/60 & 1080p24/25/30)

DataCapture

VideoData


HDCPEncryption

D[23:0]

SCLK

I S[3:0]LRCLK

T 1

Tx0VsyncHsync

Keys

Integrated CEC support Buffer CEC signals Off-loads real-time monitoring from host µP

Low standby power Software driver Easy implementation

DataCapture


TMDSOutputsDE

CLK

HPDINT

Tx1

Tx2

TxC

Hsync

y p On-chip HDCP support Automated or programmable color space converter Flexible video inputs:

RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 24 bit input interface

I2CSlave HDCP &


I2CMaster

SCLSDA

DDCSDADDCSCL

24-bit input interface Integrated I2C Master for DDC bus +5V tolerant I/Os for HPD and I2C 1.8V & 3.3V supplies

Part HDCP Package Temp



ADV7511WBSWZ Internal 12 mm 0.5 mm ¢ePad LQFP 64-pin Pb-free

–40 ~ 105 °C

ADV7513: High Performance HDMI™ 1 4 T ittv1.4 Transmitter

Supports display resolutions at 25~165 MHz (up to 1080p/UXGA) Incorporates extended HDMI v1.3/1.4 features

S t t d d l i t ( C l TM)AudioData

4:2:2

MCLKI2S[3:0]

S/PDIF


HDCPKeys*

Supports extended colorimetry (e.g. x.v.ColorTM) HBR audio formats DST/DSD audio formats 33DD Ready (720p50/60 & 1080p24/25/30)

Integrated CEC supportB ff CEC i l

DataCapture

VideoData


HDCPEncryption

D[23:0]

SCLK

I S[3:0]LRCLK

T 1

Tx0VsyncHsync

Keys

Buffer CEC signals Off-loads real-time monitoring from host µP

Low standby power Software driver Easy implementation On-chip HDCP support

DataCapture


TMDSOutputsDE

CLK

HPDINT

Tx1

Tx2

TxC

Hsync

p pp Automated or programmable color space converter Flexible video inputs:

RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 24-bit input interface

Integrated I2C Master for DDC bus

I2CSlave HDCP &


I2CMaster

SCLSDA

DDCSDADDCSCL

Integrated I C Master for DDC bus +5V tolerant I/Os for HPD and I2C 1.8V & 3.3V supplies Released




ADV7513BSWZ Internal 12 mm 0.5 mm ¢ePad LQFP 64-pin Pb-free

–25 ~ 85 °C

Support:ppSupport resources for core market

Customers can download datasheets and other technical d t f ADI i i (EZ)documents from ADI engineering zone (EZ)http://ez.analog.com/docs/DOC-1712

Customers can get quick technical supports from EZhttp://ez.analog.com/community/video

Advantiv™ Video Evaluation Boards and in stock (low-cost @ $199) @ $ ) Designed by ProAV SMS team EVAL-ADV7842-7511(P) is in stock EVAL ADV7612 7511(P) is in stock EVAL-ADV7612-7511(P) is in stock EVAL-ADV7619-7511(with HDCP keys) is in stock EVAL-ADV7619-7511P (without HDCP keys) is in stock


EVAL-ADV7850-7511 will be in stock in May, 2012

85

CypressypAppendix Slides


C USBCypress USB3.0 Solutions

USB Business Unit – October 2011

CYPRESS CONFIDENTIAL

Cypress EZ-USB® FX3™

88CYPRESS CONFIDENTIAL

Making USB Universal™: EZ-USB FX3

Add USB3.0 connectivity to any systemGeneral Programmable Interface (GPIF™ II)

High bandwidth data pipe connection Move over 400 MB/s of data for further processing

Enable powerful (>200 MIPS) data processingEnable powerful (>200 MIPS) data processing32-bit ARM9 processor with 512KB SRAM

ARM9

512kB SRAM

II SB

3.0

JTAG

32

µP

ASIC

GP

IF™

US

US

B 2

.0O

TG

32End

Points

FPGA

Image Sensor

CYPRESS CONFIDENTIAL 89

UART I2CSPI I2S

EZ-USB® FX3™ Features and Benefits

Features Benefits

USB 3 0 Connectivity 10x Performance compared to USB 2 0USB 3.0 ConnectivityFully Integrated USB 3.0 PHY + Controller + Link LayerCompliant with USB 3.0 v1.0 Specification

10x Performance compared to USB 2.0 (5 Gbps vs. 480 Mbps)

General Programmable Interface (GPIF II) Connect with any industry standard or nonGeneral Programmable Interface (GPIF II)Up to 32 bits, 100 MHz Programmable Parallel Interface

Connect with any industry standard or non standard interfaces in systems with FPGA, ASIC, ASSP, Image Sensors

ARM926EJSPo erf l 32 bit 200MH Processor

Fully accessible core with 512 KBOn Chip SRAM to b ild c stom applicationsPowerful 32-bit, 200MHz Processor On Chip SRAM to build custom applications

Power ManagementCompliant with USB 3.0 and Battery Charging spec 1.1

Better control over low power states Faster Battery Charging

Other Serial InterfacesI2C, SPI, UART, I2S

Enables connectivity to system peripherals

The industry’s first and only flexible Super Speed USB 3.0


The industry s first and only flexible Super Speed USB 3.0 peripheral controller

EZ-USB® FX3 Specifications SummaryUSB• USB 3.0 Device• USB 2.0 OTG• 32 EndpointsGPIF™ II KGPIF™ II• Interface behavior programmed with a state machine

• Master or Slave, Synchronous or Asynchronous

FX3

DVK

• 8 / 16 / 24/ 32 bit configuration, up to 100MHz

Core, Memory and Programmability• ARM926EJS core

512KB f M• 512KB of Memory• Critical USB APIs and implementation examples• Program access via Cypress tools or standard ARM toolsOther Serial Interfaces• I2C (Boot EEPROM), SPI, UART, I2SI2C (Boot EEPROM), SPI, UART, I2S• Most unused IOs can be configured as GPIOsPower Supply, Clocking and Package• High voltage (3 to 6V Vbus or Vbatt) supply• 1.2V core. 1.8 - 3.6V IOs

19 2MH C t l


• 19.2MHz Crystal• 121 Balls, 10 x 10mm, 0.8 mm pitch BGA package

xfest2012 ppt video v1 2 may18 -...

Documents

Transcript of xfest2012 ppt video v1 2 may18 -...