8/7/2019 Writing Engineering Abstracts(33)

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Writing Engineering Abstracts(33)

工程英文摘要撰寫 

柯泰德線 英文論文編修訓練服務 http://www.chineseowl.idv.tw 

工程英文 

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強有力的工程英文摘要撰寫包括以下要素:

•簡介背景 (研究建構+研究問題)

•目標 

•方法 

•歸納希望的結果 

•對特定領域的貢獻 

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範例 (1 of 2)

簡介背景  (研究建構+研究問題) Logic circuits can achieveoptimization by full custom design flow, i.e. manual designand layout, thus enhancing product performance andlowering costs more than that achieved by the design flowof hardware description language (HDL). Conversely, a

larger logic ASIC includes more than 1,000,000 gates in achip, which is difficult for full custom design to implement.For a larger ASIC, full custom design flow requiresadditional personnel, making it extremely difficult to achievetime to market delivery.目標 Therefore, this work describes

a novel HDL-based scheme for designing logic circuits,capable not only of re-use as an IP in different processes,but also of automatic regeneration of physical circuits.

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範例 (2 of 2)

方法 All logic circuits are described by program editing. Theprograms are then synthesized to gate level formats. Next,all gates are placed and routed by auto-place-and-route(APR) software to physical layered circuits. Additionally,simulation parameters are estimated from APR software.

Moreover, the APR results are confirmed via simulationthat includes the processed parameters. Furthermore, alldescription programs are re-used. 歸納希望的結果及 Simulation results indicate that, in addition to automaticallygenerating production via software, the proposed HDL-

based scheme decreases personnel by 50% for the sameIP procedure and accelerate market to time delivery. 其對特定領域的貢獻  Importantly, automatic design flow of theproposed scheme avoids manually controlled errors,ultimately increasing product throughput and reducingpersonnel.

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範例二 (1 of 2)

簡介背景  (研究建構+研究問題) Device mis-matchingalways complicates circuitry design owing to the inability toidentify the origin, thus accentuating the importance ofprocess control. In practice, circuit designers must add anincreasing number of devices in the circuitry to overcome

process deviation. For instance, mis-matching cangenerate a yield loss of 20-30%. Whereas a larger chipsize implies a higher product price, a higher retail pricelowers market competitiveness. 目標Therefore, this studyinvestigates the correlation between process parameters

and product yield.

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範例二 (2 of 2)

方法  By adopting the statistical process control (SPC)method, process parameters are collected from the in-lineWIP. Major process-related factors are then identified usingcorrelation analysis. Next, the product yield is verifiedbased on these factors. Additionally, these process

parameters are stringently controlled to decrease the lossof product yield. 歸納希望的結果及  While analysis resultsclarify the correlation between process parameters andproduct yield, circuitry designers can focus on incorporatingthe above factors without increasing device size, 其對特定

領域的貢獻 ultimately reducing the chip area and loweringthe retail price.

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Further details can be found at

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