Week II

University of Malaya

Dr.HarikrishnanDepartment of Electrical Engineering

e-mail: [email protected]

KEEE 4469Analog VLSI Circuit Design

MOS Large Signal Characteristic

Figure 1(a) Figure 1(b)

University of Malaya KEEE 4469 HRK 2/17

The current, iD is generally given by :

In the realm of circuit design, it is more desirable to express the model equations in terms ofelectrical rather than physical parameters. For this reason the drain current is often expressedas :


( ) 2D n x GS T DS DSW 1i C v V v vL 2

=

(1)

( )D GS T DS DS1i v V v v2

= (2)

MOS Large Signal Characteristic (contd)where the transconductance parameter is given in terms of physical parameters as :

( )2ox WC A VL

=

There are various regions of operation of the MOS transistor based on the model of (2).These regions of operation depend on the value of vGS-VT. If vGS-VT is zero or negative, thenthe MOS device is in the cutoff region and (2) becomes :

D GS Ti 0, v V 0= (3)


In this region, the channel acts like an open circuit.

Figure 2

A plot of (2) with = 0 as a function of vDS is illustrated in Figure 2 for various values of vGS VT.At the maximum of these curves the MOS transistor is said to saturate. The value of vDS atwhich this occurs is called the saturation voltage and is given by :

Thus, VDS(sat) defines the boundary between the remaining two regions of operation . If vDS isless than vDS(sat), then the MOS transistor is in the nonsaturated region and (2) becomes :

MOS Large Signal Characteristic (contd)

( ) GS TDS satv v V=

( ) ( )1 = <


The third region occurs when vDS is greater than vDS(sat) or vGS VT. At this point current iDbecomes independent of vDS. Therefore, vDS in (2) is replaced by vDS(sat) to get :

( ) ( )D GS T DS DS DS GS T1i v V v v , 0 v v V2

= <

( )2D GS Ti v V ,2

= ( )GS T DS0 v V v< equation above indicates that drain current remains constant once vDS is greater than vGS VT.In reality this is not true as drain voltage increases, the channel length is reduced resulting inincreased current. This phenomenon is called channel length modulation.

MOS Large Signal Characteristic (contd) When channel length modulation is accounted for, iD is given by :

The output characteristic of the MOS transistor developed for the various region of operation isnormalized and given by :

( ) ( )2D GS T DSi v V 1 v ,2

= + ( )GS T DS0 v V v<


Figure 3

MOS Transistor Body Effect

In default it is always assumed the bulk and source are grounded, so that vB = vS = 0 held.Often circuit consideration make this convenient arrangement impossible and vS vB mustbe used.

Obviously the voltage vS vB must be such that the source-bulk junction is reverse biased; otherwise a large current will flow inside the transistor. This current may damage thedevice and in any case will impede its proper operation.

Thus in say in an nMOS transistor, the bulk must be biased to make it negative with


respect to both source and drain. The depletion region around the channel will becomewider if the reverse voltage between the bulk and the source is increased.

Since the voltage vG = VT is the gate voltage necessary to maintain the depletion region,VT will increase in magnitude. The dependence of VT on the voltage vSB = vS vB can beshown as :

( )T T0 P SB PV V 2 v 2= + + (3a)Here, VT0 is the threshold voltage for vSB = 0 and is a device constant given by :

S imp

x

2 qNC = (3b)

MOS Transistor Body Effect (contd)In (3), S is the permittivity of silicon : S= 0KS, KS 11.7. Also, Nimp is the density of the impurityions in the bulk. For nMOS, Nimp = NA, the acceptor ion density; for pMOS, Nim= ND, the donorion density. Finally, P is a material constant of the bulk; value is around 0.3 V

Small Signal Representation


Figure 4(a)

Small Signal Representation (contd)


Figure 4(b)where :

Dds

DS

igv

=

D

mbSB

igv

=

Dm

GS

igv

=

Small Signal Representation (contd)Here, gd is the incremental drain conductance, while gm and gmb are transconductance whichcan be represented by voltage controlled current sources (VCCS). The values of gm, gmb and gdcan be found from iD and (3a) :Assuming : k

2

=

( ) ( )2D GS T0 P SB P DSi k v V 2 v 2 1 v = + + + ( )( )Dm GS T0 P SB P DSig 2k v V 2 v 2 1 v

v

= = + + +


( )( )( )

m GS T0 P SB P DSGS

DS D

g 2k v V 2 v 2 1 vv

2 k 1 v i

= = + + + = + (4)

( )( )Dmb GS T0 P SB P DSSB P SB

m

P SB

ig k v V 2 v 2 1 vv 2 v

g 22 v

= = + + + +

= + (5)

( )2Dd GS T0 P SB PDS

DDS

ig k v V 2 v 2v

i1 v

= = + +

=

+ (6)

A good approximation , gm and gmb are proportional to , while gd is proportional to iD.

The other important component of the complete small-signal model of the MOS are thecapacitors representing the incremental variations of stored charges with changingelectrode voltages. These play an important role in the high-frequency operation ofthe device.

The intrinsic components of the terminal capacitances of the MOS devices (associated

Di


MOS Branching Capacitance


The intrinsic components of the terminal capacitances of the MOS devices (associatedwith reverse-biased pn junctions, channel and depletion regions) are strongly dependenton the region of operation, while the extrinsic components (due to layout parasitics,overlapping regions, etc.) are relatively constant.

Assuming again that the transistor operates in the saturation region, it can be assumedthat the channel begins at the source and extends over two-thirds of the distance to thedrain. In this region of operation, the most important capacitance are the following :

Cgd :Gate-to-Drain Capacitance. This is due to the overlap of the gate and the draindiffusion. It is a thin-oxide capacitance and hence to a good approximation it can beregarded as being voltage independent.

Cgs :

Gate-to-Source Capacitance. This capacitance has two components, Cgsov, thegate-to-source thin oxide overlap capacitance and Cgs, the gate to channelcapacitance. The latter (in saturation region) is where Cox is the total thinoxide capacitance between the gate and the surface of the substrate. Cgs is nearlyvoltage independent in the saturation region.

Csb :

Source-to-Substrate Capacitance. This capacitance also has two components :Csbpn, the pn junction capacitance between the source diffusion and the substrate,and Csb, which can be estimated as two-thirds of the capacitance of the depletionregion under the channel. The overall capacitance Csb has a voltage dependencewhich is similar to that of an abrupt pn junction.

C : Drain-to-Substrate Capacitance. This is a pn junction capacitance and is thus


x2C 3


Cdb : Drain-to-Substrate Capacitance. This is a pn junction capacitance and is thusvoltage dependent.

Cgb : Gate-to-Substrate Capacitance. This capacitance is usually small in the saturationregion; its value is around 0.1Cox

Figure 5 illustrates the physical structure of an nMOS transistor and the locations of thecapacitances in the cutoff (Figure 5(a)), saturation (Figure 5(b)) and triode (Figure 5(c))regions.

Table I lists the terminal capacitors of the nMOS device and their estimated values in thethree regions of operation. The notations used are those shown in Figure 5(a)-(c).

nMOS Parasitic Capacitances


Figure 5(a)

Figure 5(b) Figure 5(c)

MOS Terminal Capacitances

Capacitance Cutoff Saturation Triode Region

gsC

gdC

ov oxWL C ox ov2WC L L'3

+

ox ov ox

1WC L WL'C2

+

ov oxWL C ov oxWL C ox ov ox1WC L WL'C2

+

Table I. Terminal Capacitances of a MOS in Three Main Regions


gbC

sbC

dbC

ov oxWL C

( )S pn sbA C V

( )d pn dbA C V

( )( )

ox pn db

ox pn cb

1 WL'C C V3

C C V+

( ) ( )S pn sb pn sb2A C V WL'C V3+

( )d pn dbA C V

0



High Frequency Equivalent Circuit

University of Malaya KEEE 4469 HRK 14/17Figure 6

MOS Small Signal Construction

From the models of Figure 4(a) and Figure 6, a number of general statements can be madeabout the desirable construction of a MOS :

a.For high ac gain, gm should be large. This will be the case, by (4), if k (nCoxW)/2L islarge. Thus the oxide should be thin to maximize Cox (which is the oxide capacitance perunit area); also, W/L should be as large as possible. These measures, however, tend toincrease the size and thus the cost of the integrated circuit. Also, by (4), the quiescent(bias) current iD should be as large as the allowable dc power dissipation permits.


b. As the negative sign in (5) indicates, the body effect reduces the gain. To minimize gmb, (5)and (3b), we need large Cox, small Nimp (lightly doped substrate) and a large bias voltagevSB for the source.

c. Ideally the MOS transistor in saturation should behave as a pure current source. Hence asFigure 4(a) illustrates, rds should be large. By (6), this requires a small bias curent iD, alarge bias voltage vDS and a small . Since is introduced by channel length modulation, itcan be reduced by increasing L and also by increasing Nimp.

MOS As Circuit ElementsExample 1Calculate the incremental impedance seen at node A of the circuits shown in Figure 7(a) and7(b).

v i



Example 2Show that the transconductance gm in the saturation region is equal to the DC drain conductance inthe triode region (Assume : Vds

MOS As Circuit Elements (contd)Example 3Using the definition , calculate the channel resistance of an nMOS transistor from :( )D DR 1 i v=

a.

b.

( )D n x G T DWi C v V vL=

DD n x G T D

W vi C v V vL 2

=


c. ( ) ( )2D G T D G Ti k v V 1 v v V= +

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