cubesat.wdfiles.comcubesat.wdfiles.com/local--files/obdh-psu-interface/PLM... · Web viewOBDH –...

OBDH-PSU Interface Test N.Attree and G.Douglas

OBDH – PSU Interface

N.Attree and G.Douglas

1 AbstractOne of issues facing any Picosatellite is the lack of surface area to hold photovoltaic cells. Given buying highly efficient solar cells is beyond our budget, we must ensure that what power we do obtain is not wasted, in order to do this power must be monitored and managed. We have attempted to interface the Power Supply Unit and MSP430 via a protocol know as I²C. While we have been unsuccessful, the results have found a critical flaw in the MSP430 that must be addressed for the project to proceed.

2 TheoryInter-Integrated Circuit (I²C) is a simple form of serial data transmission commonly used between Integrated Circuits. In the context of PLUME, both the Power Supply Unit (PSU) and the MSP430 have an in built I²C module. It is our intent to use this in order to monitor the voltage, current and temperature of both the solar cells and the on-board battery. Knowing the amount of power available for a mission such as PLUME is of the upmost importance as it is run on a very tight power budget.

2.1 I²C as a Communications ProtocolI²C consists of two multiplexed serial connections, Serial Data (SDA) and Serial Clock (SCL), which can connect a multitude of devices and transfer data in single byte blocks. These devices can be a mixture of both master and slaves up to 127 different modules (assuming only standard 7-bit addressing is used). Within PLUME there are currently only two devices that will need to use I²C, one a slave and the other a master, thus arbitration and other multi-master issues will largely be redundant.

The master device is responsible for managing the bus, generating the clock signal and initialising commands, whereas the slave is largely passive until called upon. I²C is an asynchronous protocol, meaning that the PSU and OBDH boards can run using separate clocks, yet still communicate. There are limitations to this however, the difference in time period of each clock cannot be greater that an eighth of a clock cycle. Because of the flexibility of the MSP430, we can configure it to run at a similar speed to the TTC Node and fall safely within these limits.

Figure 1 Demonstration of SDA Changing State and Transmitting1

1 Figure 4 from Philips I2C specification (UM102004)

1


When inactive the two buses are held in a high logic state, a device will initiate a START condition by dropping SDA to a low state. This will then initiate SCL which likewise drops low. Once SCL is low, the transmitting device is free to change SDA to either high or low to signify binary 1 or 0. After an allotted low period, SCL will again rise and the receiver will take SDA’s value as the Most Significant Bit (MSB) of the transferred byte. After another allotted period clock will again drop low and the process is continued. On reception of the 8th bit the receiver is responsible for acknowledging the transfer with an ACK bit. In the I²C protocol this is signified by a high state on SDA. If an acknowledgement is not received then the transmission will cease. In order to allow slower slave devices to process this information, control of the clock is passed to the slave device which can hold it low until it is ready to acknowledge. This is referred to as Clock Stretching

Figure 2 Diagram depicting the transmission of multiple bytes along SDA and SCL2

The first byte of I²C is always the address of the receiving device, in most standard cases, including PLUME; this is 7 bits in length. However, if needed, this can be extended to 10 bits. The final bit of the address is the read/write (R/W ) bit which when low signifies that the sending device is reading from the receiver and vice versa if the bit is high. Either command or data bytes will then be sent in the manner described above until a stop condition is initiated. This is denoted by a low SDA bus rising while SCL is high.

Figure 3 Data Transmission Composition3

2.2 The PSUThe PSU consists of six solar panels (which are currently under development), a battery and an Electronic Power System board (EPS). The EPS contains the control electronics and the Telemetry and Tele-Command (TTC) node which is used for communication with OBDH via I²C.

As mentioned the solar panels have yet to be manufactured so for the purpose of testing, a solar array simulation circuit (See Figure 7). This allows power to be supplied to the EPS board through the Solar Array (SA) connectors.

2 Figure 15.3 from MSP430 User Manual (Slau049f)3 Figure 15.5 from MSP430 User Manual (Slau049f)

2


The battery consists of two Lithium Polymer cells mounted in series, side by side on top of the power generation board; this has been purchased from Clyde Space, along with the EPS board and is purpose built for CubeSats. The board contains an integrated thermostatically controlled heater, battery telemetry and cell over and under-voltage protection and over-current protection.

The battery board has the following characteristics:

Size: 58.5mm x 37mm x 5mm.Mass (total for two cells + PCB) 62gCapacity: 1250mAh.Maximum charge voltage 8.2V.Minimum discharge voltage 6.4V.End of Charge Limit (EoC): 4.1V.End of Discharge Limit: 3.2V.

and is rated for the following conditions4:

Radiation up to 500krad.Discharge between -20°C and 60°C.Charge between 0°C and 45°C.

The battery heater is an independent analogue circuit which automatically comes on to keep the batteries above 0°C. It can be overridden by a command from the I²C bus to conserve power or if a fault is detected.

The TTC node is part of the ESP board and is made up of a Microchip PIC16F690 8-bit micro-controller, as well as an analogue-to-digital converter (ADC), FLASH based program memory, built in RAM, 8MHz crystal oscillator clock and I²C slave interface.

The node can sample various physical parameters of the PSU system including panel voltage, current and temperature, and battery voltage, current, current direction and temperature before converting them via the ADC to digital telemetry data ready for I²C transmission.

The TTC node is hard coded with the I²C address 0x01 and supports a maximum transfer speed of 400kbps. (For a full list of read and write commands see Appendix 6.5)

2.3 OBDH Software InterfaceAs previously stated, the MSP430 is largely compatible with the I²C protocol, having a number of registers already built in to accommodate data transfer. By setting appropriate values in these registers, the I²C process can be mostly automated, meaning software will simply have to pass the correct address and data values to transmit. Both the reading and the writing of I²C data will have an independent function that can be called from anywhere within the main programming loop. Along

4 Data taken from Clydespace Manual (CS-RP-062M)

3


with this, a specific function to check different parameters of the PSU will be written that can likewise be called.

Below is a list of the registers as well as their basic function. Further details can be found in Chapter 15.3 in the MSP430 User Manual (Slau049f).

U0SART – Activates and configures the board as an I²C device. This includes setting properties such as master mode.

Transmit Control Register (I²CTCTL) - Sets the properties of the device including transfer mode and source clock selection.

Data Control Register (I²CDCTL) - Monitors the data flow of the busy and indicates when it is active.

Data Register (I²CDRB/I²CDRW) – Contains data either received or to be sent depending on mode.

Clock Prescaler Register (I²CPSC) – Used to divide the assigned clock in order to reduce transfer speed.

Shift Clock High/Low Register (I²CSCLH/I²CSCLL) – Used to further stretch the high and low periods of the clock

Own Address Register (I²COA) - assign an address to the MSP430 Slave Address Register (I²CSA) - assign a target address for the transmission Interrupt Enable Register (I²CIE) - Enable interrupts on the bus Interrupt Flag Register (I²CIFG) - Register containing interrupt flags Interrupt Vector Register (I²CIV) - Used to determine which flag caused an

interrupt

Figure 4 Clock Scaling from Input Signal (I²CIN) to Final I²C Clock5

2.4 Electrical InterfaceAs well as software considerations, we must also take into account the electrical needs of the I²C bus. Three state logic, as the name suggests, has three possible states. The most significant are the concepts of binary 1 and 0. Further there is the possibility of a ‘Don’t Care ‘(DC) bit. This indicates that the device set to this state is inactive. Beginning with the DC state, this is signified by high impedance on a device and as such there is negligible current between it and the bus. When a device does become active, it can be set to either high or low. High is taken as a floating reference; the bus is released by a device and is allowed to charge through the pull up resistors, in the same manner as a simple Resistor-Capacitor (RC) circuit. Likewise, to drop the bus to a low state, the bus is allowed to discharge, lowering the voltage to near zero.

5 Figure 15-13 from MSP430 User Manual (Slau049f)

4


The thresholds for the low and high states on I²C are taken as above 70% and 30%. However, Voltage cannot simply drop instantaneously, however, because of the RC circuit similarity; we can calculate the rise time.

V=V DD e−t /R pc [1 ]

Considering first the High and then the Low state:

0.7×V=V DD e−t /RpC

Solve for t=1.2039729×RpC

0.3×V=V DDe−t /R pC

Solve for t=0.3566749×RpC

Therefore ∆ t=0.8473×R pC

Given that a maximum rise time will be known and capacitance will depend on the dimensions of the bus, we can rearrange to find a maximum pull up resistor.

Rpmax=∆ tmax

0.8473×C[2 ]

Figure 5 (a) Maximum Pull up Resistance as a Function of Capacitance (b) Minimum Pull up Resistance as a Function of Voltage6 NB. MSP430 uses Standard Mode

However the devices on the bus must be protected as an excess current can cause damage. This means that there is also a minimum requirement of the pull up resistor to manage the current. It is specified7 that the current on I²C must be atleast 3mA; as such we can calculate the minimum.

Rpmin=V DD−V OLIOL

[3 ]

6 Figure 29-30 from Philips I2C Specification (UM102004)7 Philips I2C Specification (UM102004) – Table 5 Characteristics of the SDA and SCL I/O stages

5


Even at the maximum value of V DD(3.6V) and minimum V OL (0V though this implies that there is no load) given by the specification along with the minimum operating current of 3mA, we get a relatively low value of 1k2Ω.

3 Test Plan3.1 Pin DescriptionsThe majority of the pins on the PC104 connector are not used by the PSU and therefore do not need to be connected during testing. Because the EPS is flight hardware, upmost care will be taken, with both ESD protocols and a laminar bench used. Likewise, while more robust, the MSP430 is static sensitive thus a static matt will also be required. Pins will be connected using wire as stacking the boards is not an option. While they are required to be long enough to separate the boards, they must be as short as possible in order to reduce capacitance in the bus.

There are two sets of pins that are assigned as I²C buses by the MSP430, H1.41/43 or H1.21/23. However, on the EPS board, pins H1.41 and H1.43 are used as the I²C bus such that, in order to use H1.21 and H1.23, a zero ohm resistor must be introduced. As shown in Figure 6, SDA is on H1.23/41 and SCL on H1.21/43

H1.24 (ON_I²C) can be used to manually turn the TTC node on and off but is not normally needed as the node has a default setting as on8. H2.25, H2.26, H2.27 and H2.28 are all connected to the power buses (5V for the first two and 3.3V for the second pair). H2.29, H2.30 and H2.32 are all digital grounds, one of which will be used in order to form a common ground.

3.2 Preliminary Testing SetupIn order to confirm that the PSU board is functioning correctly a short preliminary test is conducted before interfacing. This is to discover the charge status of the battery and the functionality of the TTC node by interfacing it directly with a laptop. Firstly the EPS board is removed from its Clyde Space packaging and set up, with the battery board on top, on a grounded mat in a laminar flow bench.

Grounded wrist straps are worn at all times when handling both the EPS and OBDH boards and gloves with the EPS in order to protect against organic materials.

Using pre-soldered push-pin headers the removal of the pull pin and closing of the separation switch are simulated as in previous testing. This activates the BCRs and power buses and must be done before putting any power into the BCRs to prevent damage. The connections are shown in Figure 6 below.

H2.34 to H2.44H2.36 to H2.42.

8 From private E-mail correspondence with Kevin Worrall at Clyde Space. Available at request from either [email protected] or [email protected].

6

mailto:[email protected]



Figure 6 Schematic representation of headers 1 and 2. Pins that have the same colour are connected together. The red lines indicate which pins need to be connected to simulate the

removal of the pull-pin and the closing of the separation switch.9

In order to test the majority of the ADC telemetry commands a power input to the PSU is needed. As previously mentioned the solar panels have yet to be assembled so power is delivered by a standard, current limiter equipped, power supply through a solar array simulation circuit as shown in Figure 2. The power supply is checked by multimeter before the test and the simulation circuit, which is contained on a small breadboard with soldered wire connections, is set up.

Figure 7 Solar array cell equivalent circuit

There are three sets of SA pins corresponding to X, Y and Z solar panels (Fig. 8) with each set having six pins for power, return and telemetry. The pins for SA1 (Y axis) are described in Table 1. The other sets have equivalent connections. For testing, push connectors have been acquired and wires soldered in, colour coded with red and black for standard power and ground and purple for telemetry. Pins 1 and 2(+ axis) have yellow tags and pins 3 and 4(- axis) have red tags. The power supply is turned on and the current limiter is set to 0.5A and the voltage initially to 0V.

Pin Name Use1 +Y_VARRAY Power2 GND Return3 +Y_TEMP_TELEM Telemetry4 -Y_VARRAY Power5 GND Return6 -Y_TEMP_TELEM Telemetry

Table 1 Header SA1 pin description10

9 Adapted from Figure 2.2 - Clydespace Manual C1-USM-5003-CS-EPS10 From Clydespace Manual (C1-USM-5003-CS-EPS)

7

+ -

+-


Figure 8 Location of the three SA headers on the PSU board11

Next the EPS board must be connected to a laptop in order to check that the TTC node is functioning. This is done via a USB-I²C adaptor board which is connected to the EPS by wires soldered on a second pin header. The pins needed are as follows:

H2.29 GND to DGNDH1.41 I²CData to SDAH1.43 I²CCLK to SCL

The adaptor board is then connected to the laptop by USB cable. The laptop is equipped with QuickUSB diagnostics to read the I²C signals. This is opened and the read and write addresses set to 1, message length to 2 and period to 1ms. This can be changed to 2ms if problems occur.

At this point the voltage across the solar equivalent circuit is raised to power up the system. The voltage is slowly raised from 0 to up to 8V checking the voltmeter and ammeter to make sure that 8V and 0.5A are not exceeded.

The battery voltage is then checked manually by touching a mulitmeter across pins H2.46 (unregulated battery bus) and H2.30 (ground).

TTC node read and write commands from the Table 3 (Appendix 6.5) can then be sent and the board returns telemetry data in hexadecimal form. This is translated using the conversion table, also in Table 3.

3.3 OBDH-PSU Integration SetupThe OBDH test board is stored and transported in a static proof bag and, when in use, is placed on a static mat, next to the laminar flow bench with the PSU hardware, keeping them separate to minimize contamination. The OBDH board is not clean so this is not ideal, however cleaning either board would be difficult and time consuming so maintaining a distance between them on the bench is the best solution.

11 Adapted from Clydespace Manual (C1-USM-5003-CS-EPS)

8


The OBDH is set up with its mains power supply and a USB adaptor to a laptop for downloading code. A logic analyser is then used and logic probes attached to the I²C pins (described below) on the OBDH board to record the signals sent and received.

The PSU is set up in the laminar flow bench as before with the pull pin and separation switch headers and a current limited power supply delivering power through the solar array simulation circuit.

A different header is then attached to H1 with the I²C connections as shown in Fig 9.

The OBDH used the alternative I²C clock and data pins (H1.21 and H1.23 respectively), meaning 0ohm resistor bridges must be made to the standard clock and data (H1.43 and H1.41) pins as described in the Clyde Space manual(??). Other than this the pins are the same as for previous tests but with longer wires to reach the OBDH board.

On the OBDH end the wires have individual soldered push pin connections, which are slotted into the corresponding pins, as well as the pull-up resistors.

Figure 9 Full pin connection diagram for integration testing.12

Once all the connections have been made the PSU board can be powered and the voltage slowly raised to a maximum of 8V and 0.5A as before.

The code to be tested is then downloaded to the OBDH board from the laptop and the Power Up Clear button is pressed to reset the board and begin the code cycle.

The first program to be tested simply sends arbitrary bits to the PSU address (0x01) in order to confirm that the I²C is working. The signals are recorded with the logic analyser and, with the correct timing scale; the individual bits transmitted can be picked out by eye.

After I²C communication is proved to be working, more code will be written to receive read commands from the board so that telemetry, such as battery voltage

12 Adapted from Figure 2.2 - Clydespace Manual C1-USM-5003-CS-EPS

9


and current, can be written to and read from the board. These data can be read by eye from the logic analyser, translated and checked by hand by measuring with a voltmeter as in previous testing.

3.4 Battery Test SetupIn order to test the battery system fully the PSU will be connected to the OBDH board which will record data over several full charging and discharging cycles.

The PSU board and battery will be set up as for the integration test. For charging this involves powering the battery through the solar array equivalent circuit with an appropriate power supply, chosen to simulate the average power the CubeSat can expect in orbit. For discharging a load circuit, composed of resistors, will simulate the average power expected to be drawn by the other subsystems. For details see the charging/discharging test plan document13.

The OBDH board will then be connected as in the section above. Code will be written to record battery data (current, voltage, temperature and current direction) periodically to generate a log file of telemetry data which will be saved to the SD card. The SD card can then be removed at the end of the test and read with a suitably equipped laptop; the recorded data will then be compared to timed multimeter measurements as above. Characterising the battery will be valuable when the satellite is in orbit, as it will allow us to manage the power budget and prevent loss of all power.

3.5 Powering the OBDH Board from the PSUThe final test, once all other parts are shown to be working, will be to send and receive telemetry and telecommand with the OBDH board powered through the PSU. This will involve connecting the two boards as above and additionally connecting the OBDH to the 5V bus so that it can draw power from the PSU. This is done by connecting to the H2.26 and H2.25 pins.

We will proceed cautiously by testing the OBDH on its own first, with one certified power pack, before testing it alongside the PSU board.

To do this additional wires will be soldered to the push connector on the PSU board to pins H2.26 and H2.25 and fitted with push connectors on the other end to fit to these two pins on OBDH.

The PSU will be set up with power delivered from power packs, through the solar array equivalent circuits to the OBDH board. The same code from above will be used to send and receive commands to measure this voltage and current input and compare to real measurements made with multimeters as before. This test should show the whole PSU system (minus the as yet not purchased solar arrays) working together with OBDH to provide power, telemetry and the ability to send telecommands.

13 PLM-PSU-ChargeDischTest-307-2 available on cubesat.wikidot.com

10


4 Results, Conclusion and Evaluation4.1 Preliminary Testing ResultsThe voltage was raised to 5.9V and the board drew 0.34A through the yellow SA2 pins (+X). The battery voltage was measured as 7.51V.

Commands were sent and decoded as follows:Command Hex Received Decoded Result

Battery 1 Voltage 00 F1 7.34 V00 F2 7.33 V00 F3 7.32 V

Battery 1 Temperature 02 0A 25.614 °C02 09 25.777 °C02 0A 25.614 °C

Battery 1 Current Direction 03 FF Battery Discharging03 FF Battery Discharging03 FF Battery Discharging

Battery 1 Current 03 80 2.79528296 mA03 80 2.79528296 mA

Table 2 Preliminary Results for EPS test

4.2 Clocking

As well as using the I2C simulator to ensure that the EPS was working, the duration of the clock cycle was also measured. The documentation for the EPS (CubeSat Power System User Manual) states that the bus can handle a maximum speed of 400 kbps (kilobits per second) which would correspond to I2C fast mode (I²C-bus Specification and User Manual).

By monitoring the transmission, using a logic analyser, the clock cycle was found to be 12 ±1 µs which in turn gives a frequency range of 77 - 91kHz. By using the registers I²CPSC and I²CSCLH/I²CSCLL, it was possible to get a signal in this range. By setting I2CPSC to 0x03 and both I²CSCLH and I²CSCLL to 0x0A, it was possible to divide the MSP430 8MHz clock by 48, giving a frequency of 83.3 kHz. This was then verified using the logic analyser to monitor an address being sent from the MSP430.

It is entirely possible that the I2C simulator was the limiting factor in this experiment as there was very little information available, however the fact that the EPS has been shown to run at this speed indicates that it should respond to the MSP430. When proceeding, it will be assumed that the EPS can only handle Standard mode I2C and as such is restricted by the more stringent restrictions laid out in Table 6 (p37) of the I²C-bus Specification and User Manual (UM102004).

11


4.3 I²C Signals

Figure 10 Annotated I2C signal. No ACK bit is present

Figure 10 shows the resultant signal from the MSP430 when connected to the EPS. It is clear to see that the signal is I2C like. However where the acknowledgement bit is expected, the slave device continues to hold the clock line low. It is not known why this is the case and until this is solved, there is no way to proceed as it cannot be said that the EPS is correctly receiving the I2C data.

4.4 Pull-up Resistors and Switching Circuit

As previously stated, in order to operate correctly, any I2C device requires adequate pull up resistors. The EPS was found to contain two 1kΩ pull up resistors14. On the MSP430 values of 1k, 1.2k, 2.7k, 4.7k, 5.6k and 10k have all been found to hold the bus high and still give sufficiently small rise time to allow I2C transmission.

It is suggested in CubeSat Kit Design for Concurrent SPI + I2C Operation (Memo from Andrew E. Kalman, 14th June 2008) that use of both SPI devices, in our case the SD card, and I2C required additional circuitry (see Appendix 6.2 , Figure 11) in order for communication to be successful. The MSP430 uses the same lines for both SPI and I2C, leading to conflicts and erroneous or even no data being transmitted.

This circuit works by applying high impedance between the I2C devices and the MSP430 when I2C_ON is held low, such that the signal does not pass. When I2C_ON is held high, the impedance is minimal and as such the passes. It is not essential but is recommended that the SD card be turned off in software, though this is the default status.

14 From private E-mail correspondence with Kevin Worrall at Clyde Space. Available at request from either [email protected] or [email protected].

12




The circuit was implemented as shown but did not remedy the situation; it is however thought that it is still necessary. Further investigation is recommended to increase the power efficiency and reliability of the circuit. Likewise, it has been suggested that there are ICs that can perform the same task. Whether these are suitable also needs to be determined.

To conclude, further investigation is needed into the electronics of the EPS and MSP430 boards. It would be wise to firstly test the MSP430 with another I 2C device as while the outbound signal holds all the characteristics of I2C, there is no way to definitely know this. There is a possibility that something is preventing the EPS from acknowledging the transmission and this would become apparent if another slave device experienced the same issue.

5 References

MSP430x-1xx Family User Guide (Slau049f), 2006, Texas Instruments I²C-bus Specification and User Manual (UM102004 Rev. 03), 19th June 2007,

NXP Semiconductors EPS, Battery and Solar Panels For Cubesats (CS-RP-062M), 31st March 2008,

Clydespace CubeSat Power System User Manual (C1-USM-5003-CS-EPS, Issue K), 14th July

2008, Clydespace CubeSat Kit FM430 Flight Module Hardware Revision: C Datasheet

(DS_CSK_FM430_710-00252-C Rev J), June 2008, Pumpkin Technology The Art of Electronics (2nd Edition ), 1989, Horowitz, Paul

13


6 Appendices and Technical Details6.1 Current Revision I²C code

/* I²C-PSU test interface Updated by Gareth Douglas 29/07/10 [email protected]*/

#include <io.h>

void waitms(int time){//Imported from timing.c BCSCTL1=0x00; //Sets ACLK=LFXT1CLK TACCR0=time*4; //assumes one run of clock=0.25ms TACTL=0x01D2; //Resets timer, sources from ACLK/8, and sets to count up to TACCR0 while (!(TACTL & 1));}

void I2C_send(int *data, char address, int length){ int i; P3SEL |= 0x0A;/*Sets pins to use peripheral module, there is no need to set PDIR as this has been tested with both directions being set*/ I2CIE = 0xFF; // Stop watchdog timer to prevent time out reset WDTCTL = WDTPW + WDTHOLD;

BCSCTL2 |= SELS; //Set SMCLK to XT2 oscillator BCSCTL2 &= ~0x06; //Set clock divider to 1

U0CTL |= SYNC + I²C; //Set USART 0 to I2C U0CTL |= MST; //Make I²C master

U0CTL &= ~(I2CEN); //Clear I2C enable I2CTCTL |= 0x20; //Set I2C to use SMCLK I2CTCTL &= ~(I2CRM); //Set repeat mode to zero I2CTCTL &= ~(I2CWORD); //Set to byte mode

I2CPSC = 0x03; //Set prescalar multiplier to 4x I2CSCLH = 0X0A; //Set SCL high period to 12x prescalar period I2CSCLL = 0x0A; //Set SCL low period to 12x prescalar period I2COA = 0x02; //Set own address to 2 I2CSA = address; //Set slave address U0CTL |= I2CEN; //Renable I2C

I2CTCTL |= I2CTRX; //Set transmit mode I2CNDAT = length; //Set to transmit one byte

for(i=0; i<length; i++){//loop to repeat give command

14


// while ((I²CIFG & TXRDYIFG) == 0);{// }//wait for transmitter to be ready (currently not in use) I2CDRB = data[i]; //Gives a data byte waitms(1); } P1OUT = I2CIFG; //display register I2CTCTL |= I2CSTP; //Sets STOP condition bit I2CTCTL |= I2CSTT; //Initiates a start condition}

int main(){ char address; int interupt; int data[2]; int length;

address = 0x01; //set target address data[0] = 0x00; //set data bytes data[1] = 0x18; // Current command is to check Battery Voltage length = 2; //set number of data bytes I2C_send(data, address, length);}

6.2 MOSFET Based Switching Circuit

Figure 11 Switching Circuit Diagram15

15 From CubeSat Kit Design for Concurrent SPI + I2C Operation (Memo from Andrew E. Kalman, 14th June 2008)

15


NB As previously mentioned, the EPS already contains Pull-up resistors of 1k, therefore the circuit constructed need only go as far as the connection to the MOSFET

6.3 Master Transmit Flowchart

Figure 12 Flow Chart showing Process of a Master Transmit on the MSP43016

16 Figure 15-8 from MSP430 User Manual (Slau049f)

16


6.4 Master Receive Flowchart

Figure 13 Flow Chart Showing the Process of a Master Receive on the MSP43017

6.5 TTC Node Commands17 Figure 15-9 from MSP430 User Manual (Slau049f)

17


READ ADC CHANNELS

SIGNAL Byte SEQUENCE

CALIBRATION EQUATION UNITHexadecimal Binary

Panel Y1 Voltage 0x1 0000001V = (-0.009*ADC) + 8.703 V 0x0 00000000

0x0 00000000Panel Y1 Current 0x1 0000001

I = (-0.486*ADC) + 502.524 mA 0x0 00000000 0x1 00000001Panel Y1 Temp 0x1 0000001

T = (-0.1619*ADC) + 110.119 DegC 0x0 00000000 0x2 00000010Panel X2 Voltage 0x1 0000001

V = (-0.009*ADC) + 8.703 V 0x0 00000000 0x3 00000011Panel X2 Current 0x1 0000001

I = (-0.486*ADC) + 502.524 mA 0x0 00000000 0x4 00000100Panel X2 Temp 0x1 0000001

T = (-0.1619*ADC) + 110.119 DegC 0x0 00000000 0x5 00000101Panel X1 Voltage 0x1 0000001

V = (-0.009*ADC) + 8.703 V 0x0 00000000 0x6 00000110Panel X1 Current 0x1 0000001

I = (-0.486*ADC) + 502.524 mA 0x0 00000000 0x7 00000111Panel X1 Temp 0x1 0000001

T = (-0.1619*ADC) + 110.119 DegC 0x0 00000000 0x8 00001000Panel Z1 Voltage 0x1 0000001

V = (-0.009*ADC) + 8.703 V 0x0 00000000 0x9 00001001Panel Z1 Current 0x1 0000001

I = (-0.486*ADC) + 502.524 mA 0x0 00000000 0xA 00001010Panel Z1 Temp 0x1 0000001

T = (-0.1619*ADC) + 110.119 DegC 0x0 00000000 0xB 00001011Panel Y2 Voltage 0x1 0000001

V = (-0.009*ADC) + 8.703 V 0x0 00000000 0xC 00001100Panel Y2 Current 0x1 0000001

I = (-0.486*ADC) + 502.524 mA 0x0 00000000 0xD 00001101Panel Y2 Temp 0x1 0000001

T = (-0.1619*ADC) + 110.119 DegC 0x0 00000000 0xE 00001110Panel Z2 Voltage 0x1 0000001

V = (-0.009*ADC) + 8.703 V 0x0 00000000 0xF 00001111- (gnd) 0x1 0000001 0x0 00000000 0x10 00010000 - (gnd) 0x1 0000001 0x0 00000000 0x11 00010001 Battery 2 Temp 0x1 0000001

T = (-0.163*ADC) + 110.7 DegC 0x0 00000000 0x12 00010010Battery 2 Voltage 0x1 0000001 V = (-0.01*ADC) + 9.75 V

18


0x0 00000000 0x13 00010011Cell 2 Voltage 0x1 0000001

V = (0.00488*ADC) - 0.30256 V 0x0 00000000 0x14 00010100

Battery 2 Current Direction0x1 0000001 High - Bat Charging 0x0 00000000 Low - Bat Discharging

0x15 00010101 Battery 2 Current 0x1 0000001

I = (-3.473*ADC) + 3256.644 mA 0x0 00000000 0x16 00010110Battery 1 Temp 0x1 0000001

T = (-0.163*ADC) + 110.7 DegC 0x0 00000000 0x17 00010111Battery 1 Voltage 0x1 0000001

V = (-0.01*ADC) + 9.75 V 0x0 00000000 0x18 00011000Cell 1 Voltage 0x1 0000001

V = (0.00488*ADC) - 0.30256 V 0x0 00000000 0x19 00011001- (gnd) 0x1 0000001 0x0 00000000 0x1A 00011010 - (gnd) 0x1 0000001 0x0 00000000 0x1B 00011011

Battery 1 Current Direction0x1 0000001 High - Bat Charging 0x0 00000000 Low - Bat Discharging

0x1C 00011100 Battery 1 Current 0x1 0000001

I = 3/(1023*0.94) * ADC) mA

0x0 00000000 0x1D 00011101Panel Z2 Temp 0x1 0000001

T = (-0.1619*ADC + 110.119 mA 0x0 00000000 0x1E 00011110Panel Z2 Current 0x1 0000001

I = (-0.486 *ADC) + 502.524 mA 0x0 00000000 0x1F 00011111

Table 3 I²C Commands for Clydespace EPS

19

cubesat.wdfiles.comcubesat.wdfiles.com/local--files/obdh-psu-interface/PLM... · Web viewOBDH –...

Documents

Transcript of cubesat.wdfiles.comcubesat.wdfiles.com/local--files/obdh-psu-interface/PLM... · Web viewOBDH –...