WBS 6.2 Silicon Strip Tracker · 2019. 5. 3. · Silicon Strip Tracker Carl Haber Gabriella Sciolla...

WBS 6.2 Silicon Strip Tracker

Carl Haber Gabriella SciollaLevel-2 Manager Level-2 Deputy

Lawrence Berkeley National Lab Brandeis University

U.S. ATLAS HL-LHC Upgrade Project Director’s Review Brookhaven National Laboratory

Upton, New York May 14-16, 2019

Outline

• Overview System Overview Proposed U.S. HL-LHC Upgrade Scope Key Performance Parameters Ongoing: Plans, Decisions, Technical Readiness Reviews

• Construction Project Management Work Breakdown Structure and Contributing Institutes US Team Capabilities International Partners Dependencies ES&H

• Cost and Schedule Budget and Schedule Risk, Uncertainty, and Contingency Early Procurements and CD3a Quality Assurance and Project End-game

• Closing Remarks

C. Haber/G. Sciolla, Silicon Strips US ATLAS HL-LHC BNL Director's Review, May 15-17, 2019 2

Overview

Current Tracking System

US ATLAS HL-LHC BNL Director's Review, May 15-17, 2019 4C. Haber/G. Sciolla, Silicon Strips

• Pixels

• Position resolution in rΦ<15 μm. (400x50)

• 3 hits for |η|<2.5.

• 3 barrel layers: 1456 modules.

• 2 end-caps with 3 disks: 288 modules.

• 80x106 readout channels.

• Evaporative C3F8 cooling (-13C).

• n-in-n sensors, Radiation tolerance: 50 Mrad,1015 neq/cm2.

• Strips (+TRT)

• 4 barrel + 2x9 discs, (73/160 straw layers)

• 75 mm pitch, +/-20 mr stereo module

• 2112 barrel + 1976 disc modules

• 6,279,168 strip channels (175,424 straws)

• p-in-n sensors, ~1014 neq/cm2

Why a new tracker for HL-LHC ?

• The whole current Inner-Detector (ID) will be replaced by an all-Silicon tracker. Why ?

• A tracker to maintain Physics performance in the harsher environment of the HL-LHC.

• Current ID designed for: 10 years at Lpeak=1x1034 cm-2s-1 , μ~23, 100kHz L1 trigger rate.

• Main features of the new ITk:

• Integrated luminosity over 10 years 4000 fb-1.

• Lpeak=7.5x1034 cm-2s-1. μ~200. Detector occupancy.

• 1 MHz L0 trigger rate.

• Radiation damage: new sensor technologies, new front-end chips, lower temperature, higher voltage operation

• Occupancy: shorter strip length

• Higher data rate: new readout and data transmission technologies.

• Advanced power and signal distribution: more efficient, avoid mass increase

• Larger area: ~165 m2 of strips (current 68m2), 4x modules, >12 m2 of Pixel (current 2m2).

• Larger eta coverage, very forward tracking (actually better).

• 22 Countries, 101 Institutions.

US ATLAS HL-LHC BNL Director's Review, May 15-17, 2019 5C. Haber/G. Sciolla, Silicon Strips

CQ1

Modules and Staves/Petals


1 Sensor

+20(19) FE chips (ABC*)

+2(1) controllers (HCC*)

+2(1) hybrids

+1 Power board (incl. AMAC)

=1 SS(LS) Module

x 28 + + =

Proposed U.S. Scope

• US groups have been involved in silicon tracking at ATLAS since 1995. Played major roles in the R&D, design, construction, and operation of the present SCT.

• US groups played a major role in the development of the upgrade baseline including the stave concept, electronics architecture, and composite mechanics.

• US scope follows from areas of expertise and R&D experience.

• US will deliver 50% of the barrel tracking system. We are partners with the UK/China collaboration who deliver the rest

• US also makes unique contributions to the front end electronics and powering systems.


6.2.1 Stave Cores

• Jeff Ashenfelter, Yale, L3 Manager

• Yale, LBNL, Iowa State, U.Mass, (R&D at BNL)

• Laminated carbon fiber + electrical bus tape structure

• QC/inspection tools

• Provide 206/196 cores to the stave electrical assembly at BNL

• In partnership with the UK we provide 100% of a subset of the components Carbon fiber

Honeycomb

Carbon Foam

Bus tapes


6.2.2 Readout Electronics

• Evelyn Thompson, U Penn, L3 Manager

• Penn, UC Santa Cruz, BNL, LBNL, Yale

• ABC*: front end readout chip for strips – contribute to design

• HCC*: controller chip, 1/hybrid – complete design, fabricate, and test, deliver to entire strips project

• AMAC: monitor and control chip for powering – design, fabricate, and test, deliver to entire strips project, 1/module

• HV Mux: rad-hard HV switch to enable multiplexing of sensor bias – deliver to entire strips project, 1/module

• Power Board: provides DC-DC conversion, HV, monitor, and control, deliver to all barrel sites, 1/module, 14,395/10,976

• Cash contribution to power supplies


6.2.3 Barrel Hybrids

• Alessandra Ciocio, LBNL, L3 Manager

• BNL, LBNL, UC Santa Cruz

• Assemble and test all hybrids for US made modules

• SMD loading

• ASIC loading and wire-bonding

• Test and burn-in

• Deliver to local module assembly activities, 9736/7392 (/3)


6.2.4 Barrel Modules

• Gerrit van Nieuwenhuizen, BNL, L3 Manager

• BNL, LBNL, UC Santa Cruz; Duke, U Mass, U Iowa

• Develop fixtures and testing methods

• Mount hybrids and power boards on sensors

• Wire-bonding

• Test and inspection

• Deliver to stave electrical assembly at BNL, 6592/5762 (/3)


= module

6.2.5 Stave Assembly

• Gabriella Sciolla, Brandeis, L3 Manager

• BNL, Brandeis, Harvard, Penn

• Develop and commission precision tooling for module mounting

• Mount 2 x 14 modules (from BNL/LBNL/US Santa Cruz) on stave core (from Yale)

• Wire-bonding

• Test and inspection

• Deliver 196 staves to CERN for barrel loading


KPP’s


Threshold: (a) Fabricate, test and deliver to CERN thestaves for one half-barrel of the silicon strip detectorconsisting of long-strip modules, constructed to ATLASspecifications. (b) Prepare for the integration and testing ofthe silicon strip detector at CERN.

Objective: (a) Fabricate, test and deliver to CERN thestaves for one half barrel of the silicon strip detectorconsisting of both short-and long-strip modules,constructed to ATLAS specifications. (b) Participate in theintegration, testing, installation and commissioning of thesilicon strip detector at CERN.

Technical Specifications

• Technical Specifications and Interface Requirements The strips project is managed by the PL and the Activity Coordination

group – includes multiple US members.

Requirements documents with US authorship include: stave mechanical specs, sensor specs, HCC and AMAC, Power Board, bus tape, hybrids, and modules

The documents exist in a variety of forms and development continues

See also US ATLAS Technical Specifications Spreadsheet

Our technical specifications are under change control. We are not independent, ATLAS shares ownership, but we are embedded so completely linked to the development of specs and their evolution.


Example


ATLAS UPGRADE TECHNICAL SPECIFICATIONS

WBS Item Title Owner SpecificationsLevel 3 Approval

(initials, date)

6.2 Silicon Strip Tracker C.Haber (LBNL),

G.Sciolla (Brandeis)

6.2.1 Stave Cores J.Ashenfelter (Yale) Properties and Tolerances: Min/Nominal/Max

1)Length: 1360/1375/1390 mm

2) Width: 113/115/117 mm

3) Thickness: 5.8/5.9/6 mm

4) Deformation after co-cure <1 part in 1000

5) Bending stiffness 72 Nm^2

6) Stave Weight: 320/340/360 grams

7) Temperature range -56C – 70C

8) Local flatness <50 microns

9) Lock point collinearity <25 microns

10) Delamination – none over foam or under bond

pads, 11) <2 cells over honeycomb

12) Maximum pressure 130 bar

13) Wire bond pull strength >8 grams

14) Electrical Resistance (between all co-cured

copper strips): 2 ohms

15) Bus tape: all lines electrically connected 100%,

16) differential impedance 100+20-10 ohms,

JA 10/27/2017

6.2.2 Readout Electronics V.Fadeyev (UCSC) 1) All components must function in the radiation

environment of the HL-LHC with fluence and

ionization levels as specified in section 3.4 of the

strips TDR. 2) 6.2.2.3 and

6.2.2.4 ABC 130 nm blocks submitted to CERN

based ASIC design meeting ATLAS specifications

posted in EDMS.

3) Up to 4 MHz trigger rate;

4) 160 Mbps communication with HCC. Detailed

specifications exist.

5) 6.2.2.3 and 6.2.2.4: HCC complete design

meeting specifications set by ATLAS and posted in

EDMS.

6)Receive and decode stave side trigger, timing

and control, pass these to the hybrid side with 40

MHz beam clock.

7) Aggregate and pack data coming from the

hybrid side at up to 160 Mbs and transmit

VF 10/27/2017

Research & Development

• Ongoing R&D/Prototype to Pre-Production, ~99% complete

6.2.1 first 14-module layout of bus tape, and tooling complete, PDR 9/18

6.2.2 “STAR” versions of FE readout chips ABC* and HCC*, AMAC V3 all under test and largely functional

6.2.2 powerboard V3 produced and in distribution

6.2.3 final round of proto hybrids complete, UV glue process tuning

6.2.4 modules with V2 power boards tested, IPB placement tooling

6.2.5 “13-module” stave with proto modules completed

• Down-selects: HVMux use or not decision complete 3/2019

Committee has recommended that the HVMux be used in the powerboard

This is a ~$1M CORE US deliverable


Review History

• Project passed CD-1 review in July 2018 No recommendations

• Project passed scheduling baseline review at CERN in November of 2018

• Technical reviews at CERN include Preliminary Design Reviews: all passed, last was 9/2018

Final Design Reviews: beginning 7/2019 for ASICs, many are in Fall of 2019, these trigger the beginning of pre-production orders, sensors already complete

Production Readiness Review: roughly one year later, this triggers production orders, except for some special cases covered by CD-3a.


CQ.1

Technical Progress Since CD-1

• STAR chipset received and in test

• Core and bus tape PDR passed 9/18

• Common US/UK co-cure process adopted

• 14 module bus tape designs all fabricated with good results In process of identifying additional vendors

• V3 power boards fabricated and in distribution Noise studies continuing, shield etc.

• Power board industrialization started, one vendor identified

• All US sites have fabricated ABC130 hybrids and multiple modules

• STAR module fixtures and power board mounting fixtures have been produced

• Tape inspection robot being assembled

• We believe this level of progress, in the US, and internationally, justifies the proposed CD-3a approval to be requested this summer.


CQ.1

Pending Technical Issues

• Module scale tests with STAR chipsets

• Power board noise interference studies with V3 and STAR

• Irradiation program – TID and SEE studies scheduled for TRIUMF and Louvain

• Select power board industrial vendor (unofficially done)

• Develop second/multiple bus tape source


Master Schedule

• Prototype, pre-production, production refer to component designs

• FDR triggers pre-production orders: all of these can wait

• PRR triggers production orders and CORE credit, some need to be placed earlier


2019 2020 2021

Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr

ASIC FDR 15 PRR 18 available

Bus Tape FDR 15 PRR 18

Module FDR 15 PRR 27 1st prod

Hybrid PRR 27

PowerB PRR 27

Stave Core FDR 8 PRR 19

Loading FDR 22 PRR 10

Preproduction Plan

• The next round of parts, (sometimes referred to as pre-production 2 (PP2)), uses the STAR FEE and 14 module stave

• Real pre-production starts after the FDR’s this Summer/Fall and a new version of the STAR FEE will submitted addressing any issues found in the present round, referred as pre-production 3 (PP3)

• Preproduction will be at an unprecedented scale (~5%). For example we will build 1000 power boards, 9 staves, ~260 modules, and utilize some of the full industrial assembly and testing processes.


Production Plan

• From the ATLAS perspective, production begins after PRR’s at which time CORE credit is possible.

• Most PRR’s are in summer of 2020.

• Major orders for FEE and other components need to be placed at that time or earlier (in some cases)

• We will be in early phase of powerboard and stave core manufacture as soon as PRR’s are complete

• Hybrids and modules will be fabricated in early CY2021 once the other components are available.

• See discussion of CD-3a


Project Management

US Organization at L4


6.02 ITk StripsL2M: C. Haber (LBNL)

Deputy: G. Sciolla (Brandeis)

6.02.01 Stave CoreL3M: J. Ashenfelter (Yale)

6.02.04 ModulesL3M: G. van Nieuwenhuizen

(BNL)

6.02.01.01 Cores LBNL

IC: C. Haber (LBNL)

6.02.03 HybridsL3M: A. Ciocio (LBNL)


L3M: E.Thomson (Penn)


L3M: G. Sciolla (Brandeis)

6.02.01.05 Cores YaleIC: J. Ashenfelter (Yale)

6.02.01.06 Cores Iowa

IC: S. Prell (Iowa St)

6.02.02.01 DCS/LV/HV

IC: D. Lynn (BNL)

6.02.02.02 Power BrdIC: J. Joseph (LBNL)

6.02.02.03 ABC*,HCC*,AMAC

IC: J.Kroll (Penn)

6.02.03.01 Hbrd BNLIC: A. Tricoli (BNL)

6.02.03.02 Hbrd LBNLIC: A. Ciocio (LBNL)

6.02.03.04 HbrdUCSC

IC: A. Affolder (UCSC)

6.02.04.01 Mdls BNLIC: G. van Nieuwenhuizen

(BNL)

6.02.04.02 Mdls LBNLIC: A. Ciocio (LBNL)

6.02.04.04 MdlsUCSC

IC: A. Affolder (UCSC)

6.02.05.01 Stave BNLIC: D. Lynn (BNL)

6.02.05.03 Stave Penn

IC: M. Newcomer (Penn)

6.02.05.08 Stave Harvard

IC: M. Morii (Harvard)

6.02.05.09 Stave Brandeis

IC: G. Sciolla (Brandeis)

6.02.02.04 ABC*,HCC*

IC: A. Grillo (UCSC)

6.02.02.05 DC-DCIC: J. Ashenfelter (Yale)

6.02.01.10 Cores Mass

IC: C. DallaPiccola(U.Mass)

6.02.04.07 Test Duke IC: M. Kruse (Duke)

6.02.04.10 Test Mass IC: C. DallaPiccola

(U.Mass)

Many in this community have collaborated since mid-1990’s. The 11 institutions are now tightly linked since formalizing these specific roles and responsibilities beginning in 2015.

6.02.04.11 Test Iowa IC: U.Mallik

(U.Iowa)

CQ.3

Management Details

• L2 manager and deputy coordinate activities and reporting of L3’s, L4’s IC, and interact with PO. Internal costing and scrubbing, technical reviews

Profiles are included in the back up slides

• Interactions L3’s. L4’s, and teams

Weekly management meeting for L2 and L3’s, plus others if needed

Weekly technical meeting inclusive of all staff and students, workshops

Multi-yearly scrubbing, reviews, with US ATLAS

ATLAS ITk Weeks, Upgrade Weeks, and Reviews

• Roles within ATLAS – by appointment, this is a long term engagement and US members are deeply embedded at all levels

A. Affolder is strips Project Leader (PL) (as of 10/2017), UC Santa Cruz, relected

Eric Anderssen is Project Engineer, LBNL

Activity coordination board meets bi-weekly with PL

o J.Ashenfelder: stave cores (D.Lynn former, BNL) Yale

o V.Fadeyev: sensors, UC Santa Cruz

o P.Keener: front end electronics, Penn

o C. Haber: ex officio, LBNLC. Haber/G. Sciolla, Silicon Strips US ATLAS HL-LHC BNL Director's Review, May 15-17, 2019 25

CQ3

Staff Credentials examples

• Will Emmet, Yale, Mechanical Engineer, developed lamination

• Tom Johnson, LBNL, Mechanical Tech, co-cure expert

• David Lynn, BNL, Scientist: developed HV Mux

• Paul Keener, Penn, Electrical Engineer: HCC and AMAC design

• Timon Heim, LBNL, Scientist: design and develop powerboard

• Forest Martinez-McKinney, UCSC, Electronics/Bonding Tech

• BNL Tech

• Laura Bergstrom, Brandeis, Grad Student, programming of stave assembly system

• Vitaliy Fadeyev, UCSC, Scientist, technical lead, involved since SCT


CQ3

International Partners

• Fraction of deliverable within U.S.


WBS Design Production Partners

6.2 Silicon Strips

6.2.1 Stave Cores 50% 50% UK

Bus tapes 25% 100% UK

Core components 50% 50% UK

Cores 50% 50% UK


ABC 20% 38% CERN/UK

HCC 100% 100%

AMAC 100% 100%

HV Mux 90% 100% UK

Barrel Power Board 100% 100%

Coils 100% 100%

6.2.3 Barrel Hybrids 20% 50% UK/China

6.2.4 Barrel Modules 20% 50% UK/China

6.2.5 Barrel Staves 20% 50% UK/China

U.S. Fraction (%)

ES&H

• Safety is of the highest priority within the Project Work at each institute adheres strictly to its ES&H policies

Institute contacts are listed in the backup slides

The BNL ES&H Liaison provides oversight and advice

US ATLAS HL-LHC Institute Contacts act as interfaces between their institute and BNL and CERN

• Main Hazards in this System Ergo: Repetitive tasks are monitored and controlled by protocols

Radiation: test beams are in controlled areas

All work done compliant with safety policies at the institute or CERN


CQ6

Cost and Schedule

Cost & Schedule Estimates

• Basis of Estimate for RLS For all BOE’s a BOM is included with vendor quotes for the

procurements. These have been escalated for inflation in the RLS

For critical items vendors have been selected through a careful technology assessment and validation process (radiation, precision..), following institutional procurement rules.

Significant prototyping activity since 2007 with production capable vendors engaged extensively. Have used costing or labor models from SCT, prototyping, CMS, IceCube

Details are in the BOE’s

Labor costs are built from a bottoms up analysis of effort required to build and test hybrids, modules, and staves (cores and assembly)

See L3’s for explicit examples


CQ2,4

Changes Since CD-1

• Project evaluated and accepted three baseline change proposals (BCP) through the change control process

• BCP002: additional parts costs for tape inspection robot $30K

• BCP004: Revised IC design effort $490.7K

• BCP005: Revise RLS after CD-1 $535.7K

• BCP012: Revised vendor quotes: $175.7K

• Labor rate revisions between BCP005 and BCP012 reduced overall project cost by $288K


Total Cost Table


WBS 6.02 Strips

Sum of Value

FY17 FY18 FY19 FY20 FY21 FY22 FY23 FY24 FY25 Grand Total

6.02.01 Stave Core 256,220 498,904 525,340 1,175,188 1,169,638 1,153,440 617,062 22,695 5,418,487

6.02.02 Readout Electronics 781,776 979,167 1,230,998 941,067 1,368,820 164,259 64,986 5,531,073

6.02.03 Hybrid Assembly 136,305 587,271 804,523 689,086 1,061,278 1,346,491 1,381,842 594,974 6,601,769

6.02.04 Modules 193,603 803,606 1,720,391 862,505 1,410,289 1,990,816 2,077,967 1,338,557 10,397,734

6.02.05 Stave Assembly 218,915 584,919 779,815 658,241 996,197 999,764 1,049,353 864,761 6,151,965

6.02.07 US Contributions to CERN Procurements-BNL 339,556 664,731 2,431,568 789,225 4,225,080

Grand Total 1,586,818 3,793,423 5,725,798 6,757,655 6,006,222 5,654,770 5,191,210 2,820,986 789,225 38,326,108

Estimation Type


16%

30%

53%

0% 1%

6.02 StripsESTIMATION TYPE

Existing PO, Work Complete

Extrapolating from Actuals

Analogy

Expert Opinion

LOE

Cost per FY @L3


ASIC pre pro runs and engineers

ASIC procurements

Hybrid/Module /Stave labor

FY17 FY18 FY19 FY20 FY21 FY22 FY23 FY24 FY25

6.02.01 Stave Core 256,220 498,904 525,340 1,175,188 1,169,638 1,153,440 617,062 22,695

6.02.02 Readout Electronics 781,776 979,167 1,230,998 941,067 1,368,820 164,259 64,986

6.02.03 Hybrid Assembly 136,305 587,271 804,523 689,086 1,061,278 1,346,491 1,381,842 594,974

6.02.04 Modules 193,603 803,606 1,720,391 862,505 1,410,289 1,990,816 2,077,967 1,338,557

6.02.05 Stave Assembly 218,915 584,919 779,815 658,241 996,197 999,764 1,049,353 864,761

6.02.07 US Contributions to CERNProcurements-BNL

339,556 664,731 2,431,568 789,225

0

1,000,000

2,000,000

3,000,000

4,000,000

5,000,000

6,000,000

7,000,000

8,000,000

6.02 Strips Cost Profile

FTE per FY @L3



Y-FTE

6.02.01 2.03 4.45 5.47 3.30 5.69 5.06 4.38 0.13

6.02.02 0.92 7.44 9.71 4.57 3.58 2.19 1.06 0.20 0.21

6.02.03 5.41 4.66 6.05 7.40 8.94 8.91 4.14 0.20

6.02.04 6.39 9.79 9.33 11.82 14.32 14.26 7.48 0.20

6.02.05 2.48 5.75 3.43 3.70 5.48 6.40 7.95 5.29 0.20

6.02.90 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00 Total FTE by WBS

Cost by Category


59%

40%

1%

Labor, Material and Travel (%)

BCWS Labor

BCWS Material

BCWS Travel

Uncosted Effort

1. Averaged over the project ~40% of the FTE’s are uncosted –faculty, post-docs, grad students, lab research staff, considerable variation from task to task

2. The use of uncosted effort contributes to the overall efficiency of the project and to the benefit of US HEP A faculty person supervises students and post-docs

Students and post-docs create test code, run test systems, analyze results… things which techs are often not skilled at. Also obtain unique training in instrumentation here

Labs have invested heavily in scientists with instrumentation expertise

3. Our uncosted effort is key for the project and depends upon stable funding of the HEP research program


CQ2,3,4

Uncosted Effort Examples FY18-25

Item Inst FTE-YTotal

FTE-YUncost

%Uncost

Comments (from 2/19 RLS)

Cores LBNL 3.9 0.57 15 Scientist

Cores Yale 14.11 0.94 7 Engineer

Pwr Bd LBNL 7.68 5.19 67 Staff Scientist

FEE Penn 15.68 6.47 41 Post-doc, grad students, staff

Hybrid BNL 12.26 2.17 18 Post-doc

Hybrid LBNL 15.43 7.55 49 Staff Scientist, Post-doc

Hybrid UCSC 16.42 5.47 33 PL, post-doc, students

Module BNL 14.44 2.61 18 Post-doc

Module LBNL 19.62 9.11 46 Staff Scientist, Post-doc

Module UCSC 23.45 6.90 29 PL, post-doc, students

Stave BNL 13.17 0.89 7 Scientist

Stave Brandeis 16.62 9.58 58 Professor, grad students


Uncosted FTEs by Institution


Similar levels of effort across the university groups

OLD

Labor Types



Y-FTE

ENG 1.14 8.55 8.44 4.22 4.25 3.65 3.69 1.89

STU 0.41 0.50 0.44 0.99 1.61 1.61 0.89

TECH 1.95 5.78 7.92 8.59 15.00 17.97 17.01 8.13

UNCOST 2.34 15.21 16.69 14.20 14.23 14.17 14.75 6.83 1.31

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

Axi

s Ti

tle

FTE by Resource Category

Schedule

• Production duration PRR-July 2024

• Stave cores: delivered early, create inventory, efficiency

• Readout Electronics: ASICs delivered early and also required by a variety of downstream efforts

• Hybrid-Modules-Staves: highly linked and coordinated process across 3+ institutions working in parallel with same methods.

• Milestones are within each L3 and are addressed in the L3 presentations, some examples follow

• Schedule chart follows as well

• Certain procurements come early due to lead time and downstream dependency


CQ2

Production Milestone Examples

• 6.2.1 Cores

Jan 2021 1st cores at BNL

Nov 2023 Stave cores complete

• 6.2.2 Electronics

August 2021 HCC/AMAC production complete

April 2023 Powerboards complete

• 6.2.3 Hybrids

Feb 2021 production starts*

March 2024 production ends

• 6.2.4 Modules

March 2021 production starts

May 2024 production ends

• 6.2.5 Stave Assembly

April 2021 production starts

July 2024 production ends


Schedule

Staves are delivered continuously through production and therefore the 1st barrel is built and tested in FY22


WBS Deliverable Task FY 17 FY 18 FY 19 FY 20 FY 21 FY 22 FY 23 FY 24

RED=Critical Path

6.2.1 Stave Cores

prototypes

pre production

production


prototypes

pre production

production

6.2.3 Hybrids

prototypes

pre production

production

6.2.4 Modules

prototypes

pre production

production


prototypes

pre production

production

Need at CERN X

Early Production Procurements

• To meet production schedule would need to place certain procurements in FY2020

• Downstream fabrication efforts rely on front end electronics and stave cores being available

• Examples include Bus Tapes $663K

FE ASIC production orders $1244K

HV Mux: $897K

DCDC converters $211K

Honeycomb $488K

Carbon foam $199K


Justify Early Procurements

• Strip FDR’s are scheduled for July-Oct 2019

• However technology is very mature and is similar to what has been tested in prototyping phase.

• Newest aspect are the “star” chipset but we already know these basically work

• Expect that FDR’s, at most, result in small tweeks and will not change the costs significantly For example, we could change the design of the powerboard based

upon a recommendation from the FDR, but it is unlikely to have much impact on cost or schedule….

• Even with CD-3a approval, now, we would not be able to place production orders until after the PRR’s area all passed, which is summer of 2020.


CQ.5

Procurement Plan

• Procurements will be placed at a variety of sites within the US Strips project

• At each site we have established contact with the appropriate procurement professionals to a) alert them of our needs, b) establish what requirements we will need to prepare and follow

• BNL CERN procurements: funds can be transferred with little delay

• LBNL

• Penn

• Yale: 1-4 month lead times depending upon sole/multiple sources, can we accommodated in planning process


CD-3a list


Institution Item Task ID date PRR date delta Material K$

6.2.1 Cores Yale Bus Tapes SC200474M 8/19/2020 6/18/2020 62 32.7

Yale Bus Tapes SC200475M 8/20/2020 6/18/2020 63 444.7

LBNL CF Facing SC200510M 9/8/2020 8/19/2020 20 49.1

LBNL CF Facing SC200720M 12/21/2020 8/19/2020 124 52.2

Yale Tooling SC500890M 11/11/2019 8/19/2020 -282 76.4

Yale Honeycomb SC501204M 2/6/2020 8/19/2020 -195 162.8

Yale Foam SC501210M 2/21/2020 8/19/2020 -180 54.4

6.2.2 RE BNL HV MUX test RE140420M-RE140530M 1/17/2020 8/27/2020 -223 71.5

CERN HV MUX parts RE140190M 1/17/2020 8/27/2020 -223 895.4

LBNL PB RE261330M - RE261430M 8/20 - 12/20 8/27/2020 402.5

LBNL PB assembly RE261420M 2/19/2021 8/28/2020 175 877.5

CERN BPOL12V RE261405M 6/2/2020 8/27/2020 -86 210.4

CERN ABC RE310390M 6/18/2020 6/18/2020 0 853

CERN HCC AMAC RE321030M 7/8/2020 6/18/2020 20 472.8

Penn HCC AMAC 6/20/2020 6/18/2020 2 10Yale Coil RE530450M 2/6/2019 8/27/2020 -568 55.7

6.2.3 Hybrids LBNL Hybrid SMD HA24200M 11/7/2019 8/27/2020 -294 48.3

LBNL Hybrid SMD HA260298M 11/5/2020 8/27/2020 70 99.5

6.2.4 Modules BNL Gluing MA160080M, MA260534M, MA460590M 10/1/2020 8/27/2020 35 40

6.2.5 Staves BNL Gluing SA190004M 6/30/2020 12/10/2020 -163 206

total 5114.9

Risk and Uncertainty

Risk Register Summary


WBS Risk ID Expires

6.2.1 Cores Threat RD-06-02-01-001 Active 19-Dec-16 27-Apr-21 Bus tapes do not meet specifications

6.2.1 Cores Threat RD-06-02-01-002 Active 27-Oct-17 27-Sep-21 Carbon foam is unavailable

6.2.1 Cores Threat RD-06-02-01-003 Active 19-Dec-16 25-Sep-20 High volume, low cost electrical insulator breaks to be established

6.2.1 Cores Threat RD-06-02-01-004 Active 27-Feb-19 1-Sep-23 Cooling loops not available

6.2.1 Cores Threat RD-06-02-01-005 Active 27-Feb-19 1-Sep-23 Loss of key personnel

6.2.1. Cores Threat RD-06-02-01-006 Active 1-Mar-19 1-Jan-23 Exposure due to single bus tape vendor

6.2.2 Readout Electronics Threat RD-06-02-02-001 Active 17-Oct-17 1-May-19HV Mux does not converge' need to resort to making choices based on available cabling.

6.2.2 Readout Electronics Threat RD-06-02-02-002 Active 17-Oct-17 27-May-20Chip run fails or radiation effects cause concern for readout at high rate and we need to do another run.

6.2.2 Readout Electronics Threat RD-06-02-02-003 Active 17-Oct-17 27-May-20Chip set not compatible with lpGBT which won't be ready until just before or after production wafer orders for HCC are placed.

6.2.2 Readout Electronics Threat RD-06-02-02-004 Active 27-Feb-19 1-Sep-20 bPOL12V regulator is delayed

6.2.2 Readout Electronics Threat RD-06-02-02-005 Active 27-Feb-19 1-Sep-20 Loss of key personnel

6.2.3 Hybrids Threat RD-06-02-03-001 Active 25-Oct-17 1-Dec-22 Hybrids are delayed from non-US vendor

6.2.3 Hybrids Threat RD-06-02-03-002 Active 25-Oct-17 1-Dec-22 Wirebonding or parts attachment issues on metallization

6.2.3 Hybrids Threat RD-06-02-03-003 Active 25-Oct-17 17-Nov-20Problem with UV cure adhesives when applied as a high throughput process

6.2.3 Hybrids Threat RD-06-02-03-004 Active 27-Feb-19 1-Oct-23 Loss of key personnel

6.2.4 Modules Threat RD-06-02-04-001 Active 19-Dec-16 30-Sep-21 Problem with high throughput wirebonding of modules

6.2.4 Modules Threat RD-06-02-04-002 Active 19-Dec-16 31-Mar-24 Electrical performance of modules

6.2.4 Modules Threat RD-06-02-04-003 Active 19-Dec-16 8-Dec-20 Problem shipping modules

6.2.4 Modules Threat RD-06-02-04-004 Active 27-Feb-19 31-Mar-24 Delay in sensor shipments

6.2.4 Modules Threat RD-06-02-04-005 Active 27-Feb-19 31-Mar-24 Loss of key personnel

6.2.5 Staves Threat RD-06-02-05-001 Active 1-Sep-17 1-Jun-24 Problem with adhesive used to glue modules to stave.

6.2.5 Staves Threat RD-06-02-05-002 Active 1-Sep-17 1-Jun-24 Underestimation of yield of staves

6.2.5 Staves Threat RD-06-02-05-003 Active 1-Sep-17 1-Jun-24 Stave does not meet electrical specification due to bad modules

6.2.5 Staves Threat RD-06-02-05-004 Active 27-Feb-19 1-Jul-21 End of Stave (EOS) card is delayed

6.2.5 Staves Threat RD-06-02-05-005 Active 27-Feb-19 1-Jun-24 Loss of key personnel

Risk and Uncertainty

• Example of main risks from the Risk Register Addressed in detail in the L3 presentations

If chip design fails to meet specification, additional run required

Stave core cooling loops cannot be manufactured reliably

Risks associated with delays in hybrid or module assembly, either technical or supply, are best addressed by increasing build capacity at the 3 sites – run additional shifts

Bus tape single vendor

• List of main External Dependencies Cooling pipe loops: investigate second source in the USA

ABC* FE ASIC: major dependency, already contribute US design effort

Hybrid panels: investigate second source in the USA

Sensors: major dependency, would need to increase module and stave assembly by running additional shifts, but low probability

EOS card from DESY, also depends upon lpGBTC. Haber/G. Sciolla, Silicon Strips US ATLAS HL-LHC BNL Director's Review, May 15-17, 2019 50

Cost Impact and SA Analysis Tool

WBS risk Monthly Prod Burn Rate Delay Min Delay Max 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Cost Min Cost Max Cost Min NO-Dwn Cost Max NO-Dwn FAB Cost

6.2.1 $ 46,667

Tape Spec 2 6 1 0 0 0 1 $ 186,666.67 $ 560,000 $ 93,333 $ 280,000

C Foam 4 12 1 0 0 0 1 $ 373,333 $ 1,120,000 $ 186,667 $ 560,000

Cooling Breaks 0.5 5 1 0 0 0 1 $ 46,667 $ 466,667 $ 23,333 $ 233,333

Cooling Loops 1 9 1 0 0 0 1 $ 93,333 $ 840,000 $ 46,667 $ 420,000

Bus Tapes 1 4 1 0 0 0 1 $ 93,333 $ 373,333 $ 46,667 $ 686,667 $ 500,000.00

Key Staff 1 6 1 0 0 0 1 $ 93,333 $ 560,000 $ 46,667 $ 280,000

$ - $ -

6.2.2 $ - $ -

ABC/HCC 25667 9 15 0 1 1 1 1 $ 2,928,500 $ 4,667,500 $ 551,000 $ 705,000 $ 320,000.00

AMAC 21000 9 15 0 1 0 1 1 $ 2,039,000 $ 3,185,000 $ 509,000 $ 635,000 $ 320,000.00

HV Mux 3500 0.5 3 0 1 0 1 1 $ 86,750 $ 520,500 $ 1,750 $ 10,500

BPOL12V 1 5 0 1 0 1 1 $ 173,500 $ 867,500 $ 3,500 $ 17,500 $ 250,000.00

Key Staff 1 9 0 1 1 1 1 $ 267,667 $ 2,409,000 $ 3,500 $ 31,500

$ - $ -

6.2.3 $ 94,167 $ - $ -

Hybrid PCB 2 12 0 0 1 1 1 $ 528,333 $ 3,170,000 $ 188,333 $ 1,230,000 $ 100,000.00

Hybrid Glue 1 4 0 0 1 1 1 $ 264,167 $ 1,056,667 $ 94,167 $ 376,667

Hybrid Bond 1 6 0 0 1 1 1 $ 264,167 $ 1,585,000 $ 94,167 $ 565,000

Key Staff 1 3 0 0 1 1 1 $ 88,056 $ 264,167 $ 31,389 $ 94,167

$ - $ -

6.2.4 $ 123,333 $ - $ -

Module Bond 1 6 0 0 0 1 1 $ 170,000 $ 1,020,000 $ 123,333 $ 740,000

Module Electr 1 6 0 0 0 1 1 $ 170,000 $ 1,020,000 $ 123,333 $ 740,000

Module Ship 1 6 0 0 0 1 1 $ 170,000 $ 1,020,000 $ 123,333 $ 740,000

Sensors 1 6 0 0 0 1 1 $ 170,000 $ 1,020,000 $ 123,333 $ 740,000

Key Staff 1 3 0 0 0 1 1 $ 56,667 $ 170,000 $ 41,111 $ 123,333

$ - $ -

6.2.5 $ 46,667 $ - $ -

Glue Stave 1 4 0 0 0 0 1 $ 46,667 $ 186,667 $ 46,667 $ 186,667

Bond Stave 0.5 2 0 0 0 0 1 $ 23,333 $ 93,333 $ 23,333 $ 93,333

Stave Electr 1 2 0 0 0 0 1 $ 46,667 $ 93,333 $ 46,667 $ 93,333

LpGBT 6 15 0 0 0 0 1 $ 15,000 $ 15,000 $ 15,000 $ 15,000 $ 15,000.00

Key Staff 1 3 0 0 0 0 1 $ 46,667 $ 140,000 $ 46,667 $ 140,000


Risk Register


Risk-ID S Title Summary Post- Low High Low High Risk Mitigations Risk Responses

RD-06-02- ACarbon foam is Allcomp is only supplier of the very 10% 186 560 4.0 12.0 We will be monitoring the supplier We would move to a higher density RD-06-02- AHV Mux does not We plan an HV mux on the 10% 2 11,000 0.5 3.0 One of two alternative technologies If the technology fails we can use

RD-06-02-

02-002

A

c

t

i

v

e

Chip run fails or

radiation effects cause

concern for readout at

high rate and we need

to do another run.

Everything else is dependant on

chip fabrication and performance

both electrical and radiation. Chip

iterations can take nearly 1 year so

any failure of technical issues

propagates a delay

25% 550 705 9.0 15.0

A thorough program of chip

performance simulation during

design phase, ASIC design review,

and post-fabrication testing,

including irradiations.

Determine cause of the problem

through chip testing and its

performance simulations, revise

design, review with panel of

experienced ASIC experts, resubmit

for fabrication.

Probabili

tyCost Impact (k$)

Schedule Impact

(months)

6.2 Strips (DOE)

OLD Contingency Analysis

• Contingency estimate from @Risk MC (from PO)

• Schedule float = 22 working days

• Simulated schedule contingency @90%CL = 377 working days


Deliverable Base Cost [k$] 90% CL Cost Fraction [%] 90% CL Contingency [k$] 90% CL Cost [k$]

6.2 Strips $35,908 41.6% $14,934 $50,842

6.2.1 Stave Core $5,164 24.7% $1,276 $6,440

6.2.2 Readout Electronics $8,353 34.6% $2,890 $11,243

6.2.3 Hybrid Assembly $6,501 43.6% $2,834 $9,335

6.2.4 Modules $10,188 49.5% $5,043 $15,231

6.2.5 Stave Assembly $5,702 50.7% $2,891 $8,593

The Critical Path and Float

• The critical path has been extracted from P6 and is available as part of the documentation package

• From the PRR’s to Feb 2021, the distribution of the front end ASIC, HCCstar, determines the critical path

• After Feb 2021 the availability of modules briefly determines the critical path (3 parallel sites)

• For most of construction the critical path is due to stave assembly, the process of mounting hybrids on staves.

• Float: We will be delivering staves continuously to CERN during production: 50% are delivered 1.5 years before the need by date Current CERN schedule shows our last stave arrives 7/2/2024 and is

required 9/30/24, 62 working days of float


OLD Float Reduction Scheme

• How can we increase float?

• Hybrid/Module/Stave production is the main activity

• It consists of ramps and flat production periods and the profile is presently constrained by DOE funding guidance

• Reduce the ramp in FY21 by increasing the number of pre-production staves in FY20 (hit the ground running): 1-3 mo. Though not cost neutral, would reduce risk as well.

• Increase the build rate in FY21-22-23 by 15-20%: gains 7 mo. Relatively cost neutral to project, FY24 funds redistributed in earlier years

• Result: increase float to ~7-10 months

• Specific details can be addressed in the breakout sessions


Scope Contingency

• Comments – if we fail to produce hybrids/modules/ or staves at the required rate the obvious situation is that we reduce scope here. The stave cores and electronics both come too early to be considered scope contingency

• The strips tracker is composed of LS (long) and SS (short) strip modules which will be produced in that order. LS are built at a higher rate.

• Scope contingency would be to drop the SS modules and continue with LS

• (An entire LS tracker would function at higher occupancy)

• Rationally this needs to be considered more globally across the entire tracker community. Wider discussion initiated but not concluded.

• Others would have to pick up our deliverables.

• The UK/China cluster would be technically capable but not clear if they will have the resources

• The End Cap cluster would need to retool but then would have the required skills and experience, if they have resources


WBS Decision Date Savings (k$) Comments

6.2.4 Modules June 2022 $3000K$ Saving from less labor

Need total

Quality Assurance & End-Game

• Definition of successful end of project and metrics Mechanical and electrical performance specifications are defined

across the international project and are monitored and documented continuously. Others are doing the same work in parallel.

We deliver tapes, ASICs, and power boards to US and non-US sites early in production so early and continuous feedback and monitoring

Delivery rate of staves at CERN is known early in production

We only ship limited quantities per package

We will have reception team at CERN to test staves as they arrive and certify performance.

Quality assurance documents for each deliverable are created by the ATLAS strips project with our participation and provided to DOE

These deliverables are complete with the final stave shipment to CERN and immediate acceptance test


Closing Remarks

• This project has a natural scale – half the barrel tracker. We share this equally with the UK-China cluster

• Ramping to production readiness

• Key FDR’s upcoming this Summer and early Fall

• Significant technical and RLS progress since CD-1

• Clear list of CD-3a items

• Risk register and SA analysis has been expanded since CD-1


BACKUP

Charge

1. Is satisfactory progress being made for the current technical design to satisfy the performance

requirements? Do the key performance parameters provide a satisfactory indication of the

project’s completeness?

2. Is satisfactory progress being made in the development of the resource-loaded schedule in a

complete, consistent and credible way to serve as cost and schedule part of the project’s

performance baseline? It is compatible with the funding guidance provided by HEP? Have the

project’s risks been fully analyzed and accounted for in the contingency estimate?

3. Is the project team properly staffed with individuals that have the required skills to deliver the

proposed technical scope within the baseline budget and schedule?

4. Does the project understand its dependencies on outside resources such as international

collaborators, funding from other agencies, and participation by researchers with other

funding sources?

5. Is the need, technical justification and schedule justification sufficient to approve early

materials procurement?

6. Is ES&H being handled appropriately?

7. Has the project satisfactorily responded to the recommendations from previous reviews?

8. Are there any other significant issues that require management attention?


Bio Sketch of L2 Manager

• Carl Haber, Senior Scientist, Lawrence Berkeley National Laboratory

• Has been a member of ATLAS and the tracking collaboration since 1995, involved in silicon tracking at hadron colliders since 1986

• US ATLAS Level-2 Strips Tracker Upgrade Construction manager since 2015

Edited the original SCT TDR

Initiated the R&D leading to the development and adoption of the stave baseline design

Presented and defended baseline design during the 2008 technology down-select

Coordinated US R&D efforts on strip tracking 2008-2014

Member of the ATLAS strip tracker Activity Coordination group

• Leads the R&D and construction effort at LBNL to design and prototype stave core components. Oversees LBNL deliverables.

• Previous Experiments: CCFR (FNAL/Columbia), CDF (FNAL/LBNL)


CQ3

Bio Sketch of L2 Deputy

• Gabriella Sciolla, Professor of Physics, Brandeis University

• Has been a member of ATLAS since 2011

• US ATLAS Level-2 Strips Tracker Upgrade Construction deputy manager

L3 manager for stave assembly

Coordinates activities on stave assembly at BNL

• Other ATLAS roles

Muon Combined Performance Coordinator 2014-16

US Deputy Physics Advisor 2013-present

Tier 3 Task Force co-chair 2013

• Previous experiments: BaBar, DMTPC, DELPHI

• Member of HEPAP, SNOLab Board of Directors and Science and Technical Review Committee, FNAL PAC, member of CPAD


CQ3

Electronics Architecture


HV HV Mux AMC DCDC

Filter monitor

14

ES&H Contacts


Institute Institute ES&H Contact

BNL Lori Stiegler ([email protected]). HL-LHC US ES&H Liaison

BNL Achim Franz ([email protected]), local

LBNL Ingrid Peterson ([email protected])

Penn Kimi Bush ([email protected])

UCSC Max Wilder (https://ehs.ucsc.edu)

Yale Jeff Ashenfelter (https://ehs.yale.edu/

Duke Steve Palumbo (http://fmd.duke.edu/safety/)

Iowa State Paul Richmond (https://www.ehs.iastate.edu/about/staff/paul-richmond)

Brandeis Andrew Finn ([email protected])

Harvard Tiffany Lee ([email protected])

U Mass Christine Rogers (https://ehs.umass.edu/)

CQ6

mailto:[email protected]

mailto:[email protected]

Optimization of Resources

• Work and scope covering ten institutions was optimized

• Because there is so much commonality in the assembly and test of hybrids and modules it was decided to keep these at the same sites

• To meet the assembly throughput requirement and to be robust against problems that might occur at any one site, we distribute the hybrids and modules at three sites (BNL, LBNL, UCSC) running the same process

• All hybrid and module processes are identical across sites

• The stave assembly, which is centralized at BNL , (and hybrids and modules) are done in exactly the same way, with the same tools and equipment as in the UK/China sites. BNL became a central cluster for efforts for east coast universities (Brandeis, Harvard, U Mass, Duke, Penn).

• Front end ASIC work leverages expertise built up in the US since the late 1980’s at Penn and UCSC

• While basic composites R&D started at LBNL, the technology was transferred to BNL and then to Yale to make use of strong mechanical engineering capabilities there.


CQ4

Cost Driver Examples

• FY19: ASIC pre-pro runs, through CERN contract, ASIC engineering, pre-pro labor for modules, hybrids, and staves

• FY20: Electronics and other parts procurements, engineering labor, technical preparations

• FY21: Labor ramp for hybrid, module, stave production, consumables

• FY22-24: dominated by hybrid, module, stave production labor costs

• FY25: payment to CERN for power supplies


FTE by Resource Category


Averaged over the project ~44% of the FTE’s are uncosted=> Lab research staff, academic faculty and post-docs OLD

Cost By Resource Category


KPPs and Specifications


Threshold Objective

Scope 50% Barrel 50% Barrel

Module Placement 75 microns 50 microns

Good Channels 95% 99%

Noise <1000 e <900 e

Radiation Tolerance ATLAS spec ATLAS spec

Participate in I&C Yes Yes

Spares 0 5%

Uncosted Effort Examples

Item Inst FTE-YTotal

FTE-YUncost

%Uncost

Comments

Cores LBNL 3.23 0.21 6 Scientist

Cores Yale 10.09 0.31 3

Pwr Bd LBNL 9.41 4.46 47 Staff Scientist

HCC* Penn 9.28 5.25 57 Post-doc, grad students, staff

Hybrid BNL 8.63 1.76 20 Post-doc

Hybrid LBNL 12.97 4.30 33 Staff Scientist, Post-doc

Hybrid UCSC 11.63 3.20 28 PL, post-doc, students

Module BNL 10.41 2.57 25 Post-doc

Module LBNL 13.75 3.35 24 Staff Scientist, Post-doc

Module UCSC 15.53 3.83 25 PL, post-doc, students

Stave BNL 8.99 0.58 7 Post-doc

Stave Brandeis 9.33 5.63 60 Professor, grad students


Accelerated Profile


IncreasedPre-pro

15%-20% rate increase

Implications of Early Funding

• There are some scenarios where if some funds are distributed early we can impact risk and float.

• Risk can be reduced and/or retired earlier by (Risk ID) Ordering carbon foam as early as possible ($200K) (RD-06-02-01-002)

Developing a process to inspect and test cooling loops ($75K in FY19 and $60K/year in FY20,21) (RD-06-02-01-003)

Increasing engineering effort on ASICs during design phase (FY19) (RD-06-02-02-002)

• As indicated already, float can be increased by Starting the production ramp earlier and faster (gains 1-3 mo)

Increasing the build rate 15-20% during production years FY21-23 (gains 7 mo, ~$1M) by shifting FY24 funds into the earlier years


WBS 6.2 Silicon Strip Tracker · 2019. 5. 3. · Silicon Strip Tracker Carl Haber Gabriella Sciolla...

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