VLSI Research and Education in

the Present Scenario

Seminar organized

By

Ganapati Sengupta VLSI Laboratory

Bengal Engineering and Science University, Shibpur

May 13, 2005

FROM THE VICE-CHANCELLOR’S DESK

In this millennium VLSI happens to be one of the fastest growing cutting edge technology. We at BESUS have realized this trend. We have taken up building of the Ganapati Sengupta VLSI laboratory in right earnest and our team is working on this project with all sincerity and dedication. Our dream is to transform this laboratory into a formal VLSI School of the University. We are inaugurating the Ganapati Sengupta VLSI Laboratory on 13th May 2005 with a Seminar titled "VLSI Research and Education in the present scenario”. All the speakers who have consented to present talk at the seminar are eminent VLSI experts in our country. I hope this endeavour is a start of a long journey which BESUS will take to realize it’s long cherished dream. Dr. N. R. Banerjea Vice-Chancellor

IN MEMORY OF GANAPATI SENGUPTA

Elizabeth Sengupta On April 29, 1998, in early afternoon, my husband, Ganapati Sengupta, died instantaneously in a tragic vehicular accident on an interstate highway in Northwest Indiana in the United States while going from one site visit to another for his job as a consulting engineer. It is perhaps fitting that he died while on the job, because he had a passion for his work, more so at some times than others, but no doubt, a definite passion. His career as an engineer spanned almost four decades, with fourteen years as an engineer in the steel mills in Durgapur, West Bengal, India, and about 22 years in Inland Steel, East Chicago, Indiana, in the United States. I never saw him feel more satisfied and fulfilled, truly joyous, than when a project he had worked on was commissioned. His last year or two were spent with a consulting engineering firm which he had joined hoping to help open an office for the firm in India. He had the idea that by doing so he could give back something to India though his particular engineering expertise that had been enabled by the solid education he had received in India, especially at the Bengal Engineering College, Shibpur, West Bengal.

My husband’s strong belief that education was one of the most important keys to his success in life led him to search for opportunities to donate money to help young people have the funds to continue their education. Before he died, he ofttimes expressed a wish that he could fund scholarships for engineering students at Bengal Engineering College and was actively searching for a legitimate, monitored venue to channel such scholarship money to the College. After he died, I was grateful to find the website for the Bengal Engineering College Alumni Association of North America which offered opportunities to fund such scholarships. I had set aside a certain amount of money for the Bengal Engineering College to be given in my husband’s memory and thought that it should all go into the scholarship fund. However, I had several long talks with Sripati Bhattacharya from the Alumni Association who with several other BE College alumni both in North America and in India had been working on a project to develop a VLSI laboratory at the Bengal Engineering College which is now renamed the Bengal Engineering and Science University. After much discussion with Mr. Bhattacharya and some investigation by my husband’s engineer friends and relatives concerning the feasibility and viability of the project, I decided to give the money that I had earmarked for the BE College in my husband’s name as seed money for the VLSI Laboratory. Just yesterday, April 28, 2005, I received an e-mail message from Dr. N. R. Banerjea, Vice-Chancellor of Bengal Engineering and Science University, thanking me for the donation and informing me of the coming seminar on May 13, 2005, entitled “VLSI Research and Education in the Present Scenario” to inaugurate the Ganapati Sengupta VLSI Laboratory. I am most appreciative that the project is proceeding thanks to the dedicated efforts of many, including Dr. Banerjea. I know that the dream of Ganapati Sengupta to give back something to India and to his alma mater has been fulfilled.

FOREWORD BY THE CONVENORS The VLSI design is considered as one of the major fields of tremendous interest in industry & academics. It has interdisciplinary relevance. At present VLSI is the emerging area of interest among the researchers and engineers from Information Technology, Computer Science, Electrical and Electronics Engineering. It is reported that around 5000 Engineers per year would be appointed by the VLSI industry in India in the coming years. In order to cope up with this demand, we require at least 10 times as many engineers and researchers as India is producing now. The proposed activities of VLSI education at Bengal Engineering and Science University, Shibpur (BESUS) targets to cater to the needs of potential researchers and engineers in this field.

Bengal Engineering and Science University, Shibpur is going to present a VLSI education programme with modern technology, enhanced knowledge, a set of brilliant students and hi-tech research. The aim of this move is to produce researchers/engineers having world class expertise and put them to work with the best VLSI technology, innovated and indigenous, across a wide range. VLSI design industry is a fast growing industry, our aim is to take part actively in the process to make it even faster. There are two functional profiles of the proposed move of VLSI education and research at BESUS- (i) to develop a research team in the field of VLSI design for achieving excellence in

this field, (ii) to train potential VLSI design engineers for Indian VLSI industry as well as to satisfy

the global need.

Formal VLSI design methodology took off in USA/Europe in the late 1970's. Department of Electronics (DOE), Govt. of India, recognized its potentiality in mid 80's and formed a VLSI task force with nodal centers at IITs, IISc, CEERI, etc. However, the boost in this direction was received in mid 90's and the focus was directed towards VLSI design activities in industries and academia. During late 90's, the then Bengal Engineering College (DU) was acknowledged as one of the promising centers for VLSI education and research.

Although the progress in VLSI education at BESUS is having a plethora of constraints since inception, but the determination to build up a centre of excellence in VLSI had never lacking on the part of expertise in this area. During the last five years more than 70 research papers in VLSI design & test, authored by our faculty members, have been published in different international journals/conferences. Faculty members of this Institute are also running a number of research projects in VLSI related fields funded by different multinational agencies and MHRD, Govt. of India. A number of tools have been developed to carry on the VLSI research. About 6 PhD theses have been completed during the last five years in the field of VLSI design and test.

To achieve the goal of VLSI research and education at BESUS, we need to develop laboratories with the latest VLSI CAD tools, test equipments, and fabrication libraries. The establishment of Ganapati Sengupta VLSI Laboratory, primarily funded by the Alumni Association, is a step towards this direction. However, without active/direct support from the industry and the faculty members/trained staff our goal can not be achievable. We expect active participation from all corners in this endeavor. The

Management Committee's responsibility is to initiate new activities and provide an open platform to expedite the VLSI research activities at BESUS. The activities may include imparting VLSI training for the professional engineers and students, offering part/full time interdisciplinary degree/diploma programmes for EE/IT/ETC/CSE students, starting venture of collaboration with the industries, etc.

The laboratory in its present form, is the outcome of co-operation and help of a lot of people who have given their planning and time. First and foremost, we thank our Vice-Chancellor Dr. N. R. Banerjea and the former Vice-Chancellor Prof. A. Sengupta for their inspiration. Our sincere gratitude goes to the former members of the Management Committee. We have received uncountable support from the members of B. E. College Alumni Association of North California and Dr. Elizabeth Sengupta, wife of late Ganapati Sengupta in respect of fund, comments, criticism and suggestions. Thanks to Magma Design Automation for the generous support. We have received free synthesis tool from Magma. We also like to record our heartfelt thanks to our colleagues, Teachers, Officers and Staff of this University who have been of constant help.

Finally, we feel gratified by the presence of experts in the field of VLSI in this region who have assembled on this occasion to deliver their lectures in the seminar. We pledge to try our best to implement their valued suggestions.

Biplab K Sikdar Hafizur Rahaman Jt. Convenors

Contents P Pal Chaudhuri VLSI research and education in the next decade – an introspection 1-4 Indranil Sen Gupta VLSI Design: where we stand today? 5-10 Debesh Kumar Das VLSI Design and Test - Indian scenario 11-13 Bhargab B. Bhattacharya VLSI Design: An Interdisciplinary Challenge 14 Partha Pratim Das VLSI Education in India 15-26 Abhik Mukherjee A critical study of radio frequency radiations from VLSI circuits 27-30 Parthasarathi Dasgupta VLSI Physical Design in Deep Sub-Micron: Some Recent Issues 31-32 Susanta Sen VLSI education – the Indian scenario 33-36

VLSI RESEARCH AND EDUCATION IN THE NEXT DECADE - AN INTROSPECTION

P Pal Chaudhuri Introspection, as per Webster, refers “to examination of one’s mind and the thought process“. This brief write-up represents my thought process and traces the historical development of the VLSI technology in national and international level. A sketch is next depicted in respect of the current status prevalent in India in the background of the wind of globalization blowing around the globe. Finally considering the ground realities, a few suggestions have been enlisted for current and future activities of the newly established VLSI Research Centre at this University. I A HISTORICAL PERSPECTIVE Intel fabricated their first microprocessor in mid 1970’s exploiting the prevailing technology of Small Scale and Medium Scale Integration ( SSI/MSI ). In view of persistent demand of industry, SSI/MSI technology led the development of LSI – Large Scale Integration of circuits employing number of transistors touching a million. The subsequent developments of 1980’s paved the way for VLSI ( Very Large Scale Integration) with number of transistors one to two magnitude higher. As a result, fabrication of any complex digital system within feasible cost had become a reality. Further, mixed signal circuits involving both digital and analog devices had become possible. The low cost consumer electronic devices ( cell phone with camera, notepad, hand held low cost computing devices etc.) we enjoy today is the direct impact of such phenomenal development of this technology. While semiconductor fabrication technology did advance significantly, the systematic methodology to design a complex system/sub-system was not in place. As a result, progress of pervasive usage VLSI technology to design large scale systems/sub-systems on a chip got delayed. The very first step in formal VLSI design methodology can be traced to the publication of the book entitled “ VLSI System Design “ by Mead and Conway in late 1970’s. The R&D activities in semiconductor industries and leading academic institutions concentrated on developing design toolkit. Research in the field of VLSI CAD ( Computer Aided Design ) got a significant boost. VLSI chip design became a routine affair with the availability of sophisticated design tools. System On Chip ( SOC ) design methodology became matured over the last decade. Notwithstanding all the above developments, the design community of 21st century have to live with a few major problems such as :

(1) Design Verification , (2) efficient synthesis of Designer’s intent expressed in a suitable language

supporting verifiability; (3) an efficient CAD tool at high level to try out alternative designs with

desired trade off in silicon area, throughput, and cost; and (4) cost effective testing of a complex SOC.

No doubt, remarkable progress has been made to address each of these problems. However, I personally look forward for totally innovative solutions which should aim at

(a) exploring new models of computation; (b) supporting easy verifiability; while (c) solving a specific class of problems rather than generalization; and (d) finally, exploiting the regular, modular, local neighborhood cascade-able

structure efficiently supported by the VLSI fabrication technology. II SCENARIO AT THE NATIONAL LEVEL Recognizing its immense potentiality, Department of Electronics (DOE), Government of India formed a VLSI task force and Steering Committee in mid 1980’s at the national level with late Prof. B Nag ( Director, IIT Bombay) as its Chairman. As per the recommendation of this Committee, DOE established nodal centers in 5 IITs and a few other leading institutions like IISc., CEERI etc. IITs started offering VLSI courses from mid 1980’s. Two distinct directions emerged at the national level –

(i) innovative design of system/sub-system on a chip; and (ii) design of efficient CAD tools.

Fabrication of chips was supported by Govt of India public sector undertakings like Semiconductor Industry Ltd. of Chandigarh, and BEL of Bangalore. Since appropriate tie-up with industries was not established, the efforts of academic and research institutions did not yield the desired results. Nevertheless, looking back to the efforts put at the national level from mid 1980’s to mid 1990’s, I can confidently state the following inherent benefits derived out of this project :

1. a general awareness was developed in respect of high potentiality of the VLSI technology;

2. a large number of students were trained to take up the challenging job of VLSI chip design;

3. a number of start up companies took off with the faculties/researchers associated directly or indirectly with this project;

4. the discipline of VLSI Design and VLSI CAD took a firm root in academic and research program of different institutions.

Govt. of India project of one decade provided the desired launching pad for full thrust academic and research program in larger number of institutions throughout the country. In addition, chip design culture and associated entrepreneurial activities took off in a small scale. Even though academicians and researchers have been predicting merging of computer and communication technologies since late 1980’s, true integration of these two disciplines, in my view, got delayed by one decade. This merging of two disciplines paved the way for the next revolution triggered by “ Information Technology “. As a result, by late 1990’s VLSI design activities got a significant boost. With the blowing of the wind of Globalization, the skilled -labour intensive task of chip design got outsourced to India from USA and Europe. A number of MNCs initiated or expanded their work in India. With the high salary offered by such MNCs, all the design activities initiated in Govt undertakings came to a virtual grinding halt. Suddenly there was high demand of trained hands in the field of VLSI design.

In the above background by late 1990’s the Department of Electronics, Govt. of India was renamed as Department of Information Technology . This newly created department did recast the earlier program of VLSI Training/Design/Research with the inclusion of larger number of institutions as secondary centers attached to a primary centre. Under this new program, an attempt was made to establish a Primary VLSI design center in this University. However, that did not materialize. So two departments ( CST and ECE ) had to accept the status of a secondary VLSI Design center. Both the departments started offering VLSI courses at the UG and PG level. The CST Dept. also offered tailor made courses to industries like CMC to train their staff on VLSI Design. Even though VLSI courses were initiated in this university, VLSI design and associated research could not take off due to lack of interested faculties and research scholars/staffs. A full fledged R&D activities in this field demands dedicated research/design staffs along with teachers having active interest in this field. In late 1990’s a number of ex-students of Bengal Engg. College showed active interest to help their Alma Mater. They started collecting contributions to create a VLSI Design centre in this university. That dream, I believe, started getting materialized in last one year or so. With the establishment of the new VLSI Design Centre in this university funded by its Alumnai, a comprehensive plan can be made based on the past experience of prevailing scenario in this university. Such a plan should take into consideration the fact that the design of VLSI chips has become a routine affairs with the availability of sophisticated Design Toolkit. As a result a large number of VLSI design jobs are getting outsourced in Bangalore, Chennai and other regions in India. A large number of design centers have come up in those cities. No doubt, Kolkata and this region lagged behind. However, as per the current indication, Kolkata is likely to catch up soon. VLSI design jobs, that are routine in nature, are going to be outsourced directly or indirectly to Kolkata region. This demands availability of reasonably trained manpower in the field of VLSI design. Such manpower should have a first hand experience of running the currently available Design Toolkit – may be from Magma, may be from Cadence or Synopsis. They should have gone through two formal course in the field – preferably on system/circuit design and VLSI CAD. They should also take some design projects in the final year. III THE PROGRAM FOR THE NEWLY CREATED DESIGN CENTRE – A FEW SUGGESTIONS The above scenario establishes the fact that in order to establish a state-of-the-art inter-disciplinary center on VLSI Design in this university, it is essential to earmark at least two faculty posts and four research scholars for this center. These staffs should fully concentrate on the development of this center in respect of VLSI design activities along with offering part time and full time courses in the field of VLSI. The Alumnai Association may be requested to provide some financial support for this purpose.This should be adequately supported with the allotment of internal resources. This center should grow as an interdisciplinary platform with the active participation of faculties of Department of CST, Electronics, and Electrical Engg. While fund from Alumnai and internal resources of the university will be used for growth of this center, attempts should be made to generate fund for this center by offering

courses for industries and procuring sponsored research/consultancy projects from Govt. agencies and private industries. Help from ex-students of this university may be sought to realize this objective once the center is equipped to undertake design jobs. The short term and long term program of this center can be planned around following activities Short Term – one to two years :

1. The center will start offering tailor made courses for industry personnel and also for students of BECDU and other institutions. The fee structure will depend on the duration and type of the courses offered. Till the center is equipped with adequate staff, such courses can be offered during summer/winter vacations.

2. UG and PG students of BECDU will undertake their final year projects at this center.

3. The VLSI courses offered within BECDU should be strengthened through mini projects executed by the students enrolled for such courses.

4. The center will also offer new in-depth course for UG and PG students on VLSI Design Methodologies, Physical Design, VLSI CAD etc,, each of one semester duration while avoiding overlap of areas already covered by existing courses. The courses offered by this center should have a good flair for design assignments along with in depth study of the specific design functions that are currently not available in existing courses.

Note : Within one year the center should be able to demonstrate a few designs undertaken by students enrolled for the courses offered by this center. Long Term ( should be initiated within two years ) : 1. Offering specialization in the field of VLSI at the PG level with the introduction of 5 courses – Digital and Analog Circuit Design, VLSI Design Methodology, Physical Design, Semiconductor Technology, and VLSI CAD, followed by one semester project on VLSI system design.

2. Procuring sponsored research projects from Govt. agencies and industries. 3. Offering Design services to industries. 4. Offering PG Diploma on VLSI design ( two semester courses ) for engineers. 5. Tailor made courses for industry personnel.

VLSI Design: where we stand today?

Indranil Sen Gupta Department of Computer Science & Engineering

Indian Institute of Technology Kharagpur 721302, India

1. Evolution of Semiconductor Technology

• Small scale integration (SSI) – Gates, flip-flops • Medium scale integration (MSI) – Multiplexer, decoder, adder, register • Large scale integration (LSI) – IO processor, floating-point unit, memory • Very large scale integration (VLSI) – Processor, memory, ASIC • ………..

2. Basic Technology • CMOS – Forms the basis for almost all the chips that are manufactured today. – Consists of two types of MOS transistors:

• nMOS • pMOS

n-channel Transistor

p-channel MOS Transistor

CMOS NOT gate

CMOS Fabrication ….

Moore’s Law

Processor Type Year

Transistors

4004

1971

2,250

8008

1972

2,500

8080

1974 5,000

8086

1978

29,000

80286 1982

120,000

Intel386™ processor

1985

275,000

Intel486™ processor 1989

1,180,000

Intel® Pentium® processor 1993

3,100,000

Intel® Pentium® II processor 1997

7,500,000

Intel® Pentium® III processor 1999

24,000,000

Intel® Pentium® 4 processor 2000

42,000,000

Intel® Itanium® processor 2002

220,000,000

Intel® Itanium® 2 processor 2003

410,000,000

3. Typical VLSI Design Flow

• Behavioral specification • High-level synthesis • Logic synthesis • Floorplanning • Placement • Routing • Fabrication / Prototyping

4. Fabrication of VLSI Devices

• VLSI chips are typically based on CMOS technology. • How to fabricate these devices on the silicon floor? – Use masks. – A mask is a specification of geometric shapes that need to be created on a certain

layer. – Must be used in a well-defined sequence.

5. Parasitic Effects

• Circuit elements lie in close proximity. – Inter-component capacitances play a major role in the performance of these

circuits. • Interconnect capacitances. – Between wires across layers. – Between wires within the same layer.

6. Interconnect Delay

• Two types of delays in a circuit: – Gate delay – Interconnect delay • Both types of delay depend on :

• Width and length of the polysilicon • Thickness of oxide • Width and length of metal lines

7. Future of Fabrication Process

• Fabrication process is very costly to develop and deploy. • Semiconductor Industry Association (SIA) published the National Technology

Roadmap for semiconductors in 1977. – Provides a vision for the future. – Several manufacturers have released roadmaps, which are far more aggressive

than the SIA roadmap. 8. SIA Roadmap Feature size (micron)

0.25 0.18 0.13 0.10

Time frame 1997 1999 2003 2006 Transistors (millions/sq cm)

3.7 6.2 18 39

Frequency (MHz)

>500 >750 >1100 >1500

Chip size (sq mm)

300 360 430 520

Wiring levels 6 6-7 7 7-8 Package pins 512 512 768 768 9. Today’s Scenario

• Technology has overtaken SIA roadmap. • Today’s chip can: – Run at frequencies over 3 GHz. – Contain more than a billion transistors.

– Use basic feature size of as small as 80 nm. • Nanotechnology has emerged as a separate field with its unique challenges. – Feature size less than 100 nm. – Parasitics and interconnect delays dominate.

10. The Indian Scenario Fabrication Facilities

• Semiconductor Limited (SCL), Chandigarh – Provides 1 micron (1000 nm) technology. – Can be accessed under India Chip programme. • SITAR, Bangalore – Provides 1.2 micron(1200 nm) technology. • INTEL might set up a state-of-the-art fabrication facility in India. • Other options: – Look for a fabrication facility outside India. – Taiwan, Korea, Israel, Singapore, etc.

Initiative by DIT • VLSI laboratories have been set up in many institutions all over the country. – CAD tools from Cadence, Synopsys, Magma, etc. • Possible to design ASIC in these labs. – Create Verilog/VHDL design specification. – Perform simulation / front-end synthesis. – Using the technology library of the target fab, perform back-end design /

simulation. – Send the layout file to the fab lab for fabrication.

Any Alternative? • Use programmable devices. – Field programmable gate array (FPGA). • Today’s FPGA chips are extremely powerful. – More than a million gates. – May contain one or more built-in processors. – Can be reprogrammed on the fly. • In essence: – The fab can be set up in your lab. – Very low cost, yet reasonably powerful solution.

Even without fabrication ….

• One can develop designs that can be reused. – Basic concept behind system-on-chip (SoC) implementations. – Modules can be shared. • Possible to develop an intellectual property (IP) library of designs. – Modules are called IP cores.

VLSI Design and Test - Indian scenario

Debesh Kumar Das Computer Science and Engineering Department

Jadavpur University Present students with VLSI backgroundAbout 500,000 graduates pass every year with Electronics and Microelectronics background.Among them about 10000 graduates are specialized in VLSI, Microlectronics design related area. India has some advantages in VLSI Education Basic Education standard is good in comparison to International standard. Mathematical skills and English of the students are strong. Every year lots of students are making good scores in GRE, TOEFL, etc. Some faculties have the international experience. A lot of reputed scientists in the world, specialized in VLSI are India-born. VLSI Industry - Indian scenario 1980-81: Govt. of India set up a company Semiconductor Complex Limited. 1985-86: Texas Instruments opened a R & D centre in India. At present, a lot of Multinational companies on VLSI have opened their branches in India: Mentor-Graphics, Synopsys, Cadence, etc.Some Indian companies have grown up: Delsoft, Intera, HCL, TCS etc. What are these companies doing? - mostly design works - designing also front-end for the software tools, designed by their US counterpart Advantages for growth VLSI Industry in India Availability of talented students, capable of writing good software programs. Salaries are less in comparison to USA, Japan. Growing Research on VLSI in India A lot of change in last 15 years - International Conference on VLSI started by the initiative of Dr. Vishwani Agrawal and others, - The conference gathered the people and also created new generations, interested to do work in design and test. - The conference is now being attended by about 800 people every year - The conference in 1994 in Calcutta started the fellowship programme to sponsor the graduate students, research scholars and faculties, interested to do work in the area. - The conference in 2000 in Calcutta started an industry-day to achieve industry-academic interaction - 19th International conference on VLSI will be held in January, 2006. - Another workshop, namely VLSI Design and Test Workshop (VDAT) is now being held in every year in August Research and Education on VLSI 1987-88: Setting up of academic and R & D VLSI design centres at some leading Institutes (IITs) under major initiative from Government of India. 1997: M. Tech in VLSI, sponsored by companies started in a leading Institute (IIT-Delhi) , followed by other Institute (IIT-Bombay). Some leading Institutes started collaboration in joint projects with Industries

Corporate initiatives on VLSI education : More than ten companies are presently involved in providing 4-6 months diploma on VLSI 1998: Government came up with the project ‘Special Manpower Development Project for VLSI design and related software’ - to develop manpower in VLSI - About 3.3 M$ project for 5 years - to provide hardware and software tools to 19 Institutes - to train up people in academics of these institutes - to start new subjects in syllabus and also new courses based on VLSI Problems in VLSI Education in India - Not many properly trained people - Software are costly, according to Indian standard - Problems of installation, commissioning, periodic updating and technical support for professionally used tools - Long times involved in taming the tool Indian Position In Global scenario India’ s share in global VLSI design market is now around 0.5% The intention of the Government of India: - To raise this share up tp 5 % Indian needed a minimum of 660 well trained professionals per year in 1998. At present, about 4000 ME/Mtech needed per yea r in VLSI embedded system design. Current academic status Total core faculty pool size: 60-70 ME/MTech with knowledge in VLSI courses pass every year: 250-300 (19 Institutes) Undergraduate students being exposed to VLSI courses: 1000-1200 PhD: 8-12 Future Perspectives considering the present growth rate Required number of Institutions: 50-60 Required faculty pool size: 250-300 VLSI Lab set up: 15 M$ Book-journals: 2 M$ Problems for the growth in VLSI Industry in India- Being dependent on the orders from outside India - Completely dependent on the global market -.Lack of fabrication set-up India should design the chips of its own problems How do the other Asian countries advance? Japan’s Experience: Industry-Academic interaction VLSI Design and Education Center (VDEC) - An organization supported by many industries - aims at improving education on VLSI and supports VLSI chip fabrication for universities in Japan - more than 450 research groups from 158 universities in Japan are utilizing services and support from this Center - in 2000, 335 chips were fabricated by VDEC

Semiconductor Technology Academic Research Center (STARC) - An organization supported by 11 semiconductor companies of Japan aims to strengthen the country’s technological foundation concerning silicon semiconductors. - enhance international competitiveness by funding universities for research China’s Experience China is a late starter in VLSI, but there is a lot of change in recent past - In 2002, mainland China produced 9.6 billion chips (in comparison to 32 billion chips imported) – China is trying to produce all the chips it needs - Government has a strong initiative. A lot of investment were done by the Government in VLSI industry (more than 50%) - There are about 500 ASIC design design companies in mainland china Industry-academic interaction - Not as good as Japan (The condition is same as in India) What India should do – some suggestions - Should attempt to design and fabricate all the chips, we need in our internal market - Besides the designing chips for the foreign needs, try to find the needs of our country -Initially, a lot of investment is needed from the Government (as like as China) - May try to expertise on a particular production (example, South Korea on Memory Design, Thailand on IC Packaging)

What can be our responsibilities? Teaching -To change the syllabus of undergraduate course in electronics and computer to give more stress on VLSI - To start an M.Tech course on VLSI? Research - To start new projects (it is not the problem of money, but the human resource) - To encourage research groups (not an easy task) - To organize seminars, workshops, conferences (to make more awareness) - To start a center/Institute on VLSI? -To maintain and strengthen the international contact

VLSI Design: An Interdisciplinary Challenge

Bhargab B. Bhattacharya*

Department of Computer Science and Engineering

Indian Institute of Technology Kharagpur, India

www.isical.ac.in/~bhargab

Abstract A VLSI microchip encapsulates millions of transistors and their interconnections on a tiny piece of silicon. The social impact of microchips is all pervading and unfathomable. Design of such a complex system is an extremely complex task, and its fabrication requires the highest degree of precision. In this talk, we will walk through the amazing world of this intricate design flow, focus on the basic design goals, and elucidate their relationships with their classical mathematical counterparts. Expertise in VLSI is hard to acquire without vast interdisciplinary knowledge. Further, it is observed that the task of disseminating the theory and practice of ever changing VLSI education to the learners not only poses a challenge but also an enigma to a trainer.

---------------------------------- * On leave from the Indian Statistical Institute, Calcutta –700 108, India

VLSI Education in India Dr. Partha Pratim Das

Interra Systems (India) Pvt. Ltd. Agenda

• VLSI Chronology

• India Advantage

• Government Initiatives

• Jaipur Workshop on VLSI Education

• Actors for Change VLSI Education and R&D – A Chronology • 1979-80

– Start of VLSI Education in India with the publication of the path-breaking book, Introduction to VLSI System Design by Mead and Conway in 1980, and the introduction of “VLSI Design” courses based on it by some IITs.

– Adoption of the book’s methodology by TIFR and CEERI for their design R&D work. – Concurrently, MOS technology development related R&D work was being pur- sued at

TIFR, CEERI and IITs. • 1980-81

– Setting up of SCL and the “VLSI Task Force” by GoI. Big hopes! Big proposals and investment recommendations! Only realistic follow- ups.

• 1981-82 – First commercial interactive layout design system (among academic and R&D institutes)

installed at CEERI’s Delhi Centre under UNDP support. • Mid 1980s

– Evolution of focused integrated electronics and circuits oriented ME/MTech degree programmes at IITs.

• 1985-86 – First multinational company, TI, sets up its R&D Centre in India (for EDA tool development

and software verification). • 1986-87

– First real application of Mead-Conway methodology to design a full custom LSI processor – the PWM processor for variable frequency AC drives at CEERI, Pilani together with UCL, Belgium (under UNDP support).

• 1987-88 – Setting up of Academic and R&D VLSI Design Centres at IITs and CEERI under an

initiative of DoE. – Academic Centres equipped with

• Sun workstations • VTI tools (an integrated tool-set for full-custom and semi-custom logic, circuit and

layout design and verification) • Semi-custom design tool “Vinyas” developed by ITI that ran on a particular brand of PC

(the OMC PC-286 and PC-386). – 10 industrial VLSI Design Centres were also set up by DoE – 5 under the charge of SCL

and 5 under the charge of ITI.

• 1987-88

– Development of PLA-based FSM compiler at CEERI, Pilani.

– Development of a high-level synthesis tool under the Rachana project at IIT Delhi.

– Start of VLSI Design Workshop and International Conference.

• 1989

– VSI Formed to foster education and research in VLSI

• Early 1990s

– Successful chip design-developments by academic-R&D design centres : • CEERI (for C-DoT) using VTI tools and VTI foundry. • IIT-Kharagpur and Jadavpur University using Vinyas tools and ITI foundry.

• 1994

– Introduction of VHDL in the Indian academia and R&D.

• 1997 – Start of the first industry-sponsored MTech programme – “VLSI Design, Tools and

Technologies” (VDTT) programme at IIT-Delhi sponsored by Philips and co-sponsored by a number of other industries.

– Subsequently, TCS has supported a MTech degree programme at IIT-Bombay.

• 1998

– DoE/MIT project – “Special Manpower Development for VLSI Design and Related Software” (SMDP): 9th plan.

– Start of VLSI Design & Test Workshop (VDAT).

• Around 2000 & Beyond

– Literal boom in Design Industry with every major setting up or trying to setting up shops in India

• 2002

– Advanced VLSI Laboratory at IIT Kharagpur in collaboration with Natsem, Intel, Synopsys.

• 2004

– ISA Launched

• 2005

– Ganapati VLSI Laboratory at BESU, Kolkata

– VLSI Mtech Program at Radio Physics, CU, Kolkata Where are we today?

• Many major design companies (count the subsidiary industry as well) have an India Center

• Many more are working on a plan to setup

• Every India Center has a very aggressive growth plan Why India?

• India Operations were fuelled by

– Cost Advantages

– Availability of an English speaking, electron-aware technical community

• India Operations have been supported by

– Positive Policy adoption

– Improving service attitude Why not India?

• India Operations are being deterred by

– Spiraling Costs

– Weakening Infrastructure

– Aggressive poaching

• India is failing to deliver in

– Quality Man-Power

– Quantity Man-Power

VLSI Challenges – Evolution of VLSI Design Scenario

SMDP: Phase I

• Started 1998

• Goals

– Market share for VLSI design from 0.5% to 5%

• Salient Characteristics – 19 Participating Institutes

• 7 Resource Center (RC), 12 Participating Institutes (PI) – Rs. 15 Crores budget for 5 years – Training of Faculty at PI’s – Setting up VLSI Labs – Development of learning material – Teaching courses

SMDP I: Man-Power

• Type-I: PhD in Microelectronics.

• Type-II: MTech (VLSI Design / Microelectronics) graduate from PIs – 250-300 / yr.

• Type-III: MTech graduate of other electronics disciplines (communications, control, . . . ) with at least two relevant VLSI courses.

• Type-IV: BTech of EE/ECE/CS exposed to two basic VLSI design courses. SMDP I: RC & PI SMDP: Phase II

• Report prepared by TCS & IIT Bombay

• Promoting Microelectronic Education – The Indian Imperative

• 32 Institutes Identified in report

– 7 RC

– 25 PI

• Budget: Rs. 50 Crores / 5 Years

• Resource Centers (7) – IIT Chennai, Delhi, Kharagpur, Mumbai & Kanpur, IISc Bangalore, CEERI Pilani

• Participating Institutes (25) – IIT Roorkee & Guwahati, Warangal, Surathkal, Tiruchirapalli, Rourkela, Motilal Nehru REC,

Allahabad, B.R. Ambedkar REC, Jalandhar, Surat Nagpur, Hamirpur, Silchar, Kurukshetra, Calicut, Jaipur, Durgapur, Bhopal, Srinagar, Jamshedpur BEC, Jadavpur, G.S. I.T.S,

Indore, Thapar, Patiala BHU-IT, PSG, Coimbatore

• Salient Characteristics – Continued VLSI Lab setup support (EDA SW, HW) – Support for hiring 2 faculty members / institute – Travel support for presenting papers – Leverage SCL India Chip program – Model Course Curriculum – Access to IEEE Explore – Plan for national website for public domain EDA software

Academic Estimates

• Institutes offering ME/MTech degree in VLSI / Microelectronics discipline are the 6 (IITs and IISc) + 10 (NITs and Other) Institutes. – Total Core Faculty Pool Size : 60-70 – Type-I Manpower/year : 8-12 – Type-II Manpower/year : 250-300 – Type-III Manpower/year : 150-200 – Type-IV Manpower/year : 1,000-1,200

M.Tech Programs in VLSI in India • M.Tech in VLSI Design, Tools, and Technology (IIT Delhi) • M.Tech in Integrated Electronic Circuits (IIT Delhi) • M.Tech in Micro Electronics & VLSI Design, IIT Madras • M Tech (Electronic Design Technology), CEDT, IISc. • M.Tech in Microelectronics, VLSI and display technologies, IIT Kanpur • M.Tech in Microelectronics & VLSI, IIT Kharagpur • M.Tech in Microelectronics (IIT Bombay) • PG Program in VLSI, PSG College of Technology, Tamil Nadu • M.E. Program in VLSI, SJCE Mysore, VTU • M.E. Program in VLSI, Anna University, CE, Chennai • M.E. Program in VLSI, Govt. College of Technology and Engineering(GCT), Coimbatore,

Tamil Nadu • M.E. Program in VLSI, Amruta Institute of Technology (AIT-Deemed), Coimbatore, Tamil Nadu • M.E. Program in VLSI, SASTRA, TIFAC-CORE, Tanjavur, Tamil Nadu

VLSI Opinion Polls

• How many B.Tech/B.E. students with specialization in Semiconductors/VLSI do you think will be needed on an annual basis by 2010?

– Less than 5000

– 5000 – 7500

– 7500 – 10000

– 10,000 or more

• How many B.Tech/B.E. students with specialization in Semiconductors/VLSI do you think will be needed on an annual basis by 2010?

– Less than 5000: 23%

– 5000 – 7500: 35%

– 7500 – 10000: 16%

– 10,000 or more: 24%

• How many PG students with specialization in Semiconductors/VLSI do you think will be needed (annually) by 2010?

– Less than 500

– 500 – 1000

– 1000 – 2000

– 2000 – 3000

– More than 3000

• How many PG students with specialization in Semiconductors/VLSI do you think will be needed (annually) by 2010?

– Less than 500: 1%

– 500 – 1000: 12%

– 1000 – 2000: 26%

– 2000 – 3000: 16%

– More than 3000: 43%

• What is the number of B.Tech students graduating today with some specialization in Semiconductors/VLSI to take up a profession in the VLSI area?

– Less than 1000

– 1000 – 2000

– 2000 – 3000

– 3000 – 4000

– More than 4000

• What is the number of B.Tech students graduating today with some specialization in Semiconductors/VLSI to take up a profession in the VLSI area?

– Less than 1000: 52%

– 1000 – 2000: 13%

– 2000 – 3000: 23%

– 3000 – 4000: 2%

– More than 4000: 7%

• What is the number of M.Tech students graduating today with specialization in Semiconductors/VLSI to take up a profession in VLSI?

– Less than 500

– 500 – 1000

– More than 1000

• What is the number of M.Tech students graduating today with specialization in Semiconductors/VLSI to take up a profession in VLSI?

– Less than 500: 66%

– 500 – 1000: 27%

– More than 1000: 6%

What constitutes “Talent in VLSI” ? • Device Physics, VLSI Technology, Fabrication • Transistor-level Circuit Knowledge • Analog and mixed signal design, RF • Design Digital Design (HDL)

• Synthesis • Verification (Simulation, Formal Verification, …) • EDA • DFT • Applications

– Signal Processing – Networks – Embedded Systems

Goals of University – Industry Interaction

• Talent Pool Generation – growing the right kind of talent

– VLSI is a fast growing field and curriculum updates cannot keep pace

• Research Collaboration

– Funded projects

– Start-ups

– Papers

– Patents What is Industry saying?

• Insufficient talent pool – quality is lacking

– Graduating students are not “industry-ready”

– Productivity Issue

– Related to attrition

– Hiring experienced persons from outside India

– Motivation factor

– Should we rework the curriculum?

• Public-domain tools are enough Emphasize small projects and assignments in the course

• Placement is disorganized – students interested in electronics are getting placed in software jobs

– Target M.Tech and Ph.D. programs?

– Students graduating from M.Tech programs are not industry ready VSI Surveys

• Numbers – where are we today and where are we headed?

– Electronics and Communications

– Computer Science/Engineering

• Both B.Tech level and Specialized man power (M.Tech)

• Quality of man power

• Survey results available from vdat yahoogroups Projected Requirements

• 3000 persons required in 2006

– 500 experienced

– 2500 fresh engineers (100 companies)

• 150 M.Techs from IIT

• 150 B.Techs from IIT

What’s “Industry Ready”?

• Fundamentals

– Frequently not answered questions: setup and hold delay, RC circuit operation, …

• Ability to grasp concepts

– If the student has understood what was taught in the curriculum, (s)he can be trained

– Training is different from education

– Industry does not expect VHDL and Verilog knowledge from students! That would be a bonus.

• Applying concepts

• Basic computer skills

– At least one programming language, OS skills, …

– Bonus: Exposure to TCL/TK, Perl, etc.

• Soft skills (team work, …) What should be emphasized, what should not

• To be emphasized

– CMOS circuit design

– Electronic Design Flow

– Effect of Interconnects

– Design Timing

– Test and Verification

• Emphasize less

– BJT can be emphasized less

• Electives Debate “Talent that is coming out of the Universities is not industry-ready”

• Strongly Disagree

– The curriculum is already strong on fundamentals

• Strongly Agree – Curriculum cannot be changed too often – Less resources are available for faculty recruitment, lab infrastructure, tools – Exposure to circuit design and semiconductors lacking (both students and faculty) – Students see more glamour in software/There are more opportunities in software – “Readymade kits” – Less industry interaction (visits from industry and faculty internship programs) – Lack of motivation (device physics is less attractive) – Exams give too much choice of learning – Curriculum cannot be changed too often – Less resources are available for faculty recruitment, lab infrastructure, tools – Exposure to circuit design and semiconductors lacking (both students and faculty) – Students see more glamour in software/There are more opportunities in software – “Readymade kits” – Less industry interaction (visits from industry and faculty internship programs) – Lack of motivation (device physics is less attractive) – Exams give too much choice of learning

Academia’s Concerns

• If industry wants high quality, let them pay for it

• Indian semiconductor/VLSI industries are not coming forward for project training

• Project ideas, data, guidance

• Take faculty for deputation

• Need long-term projects

• Does any Indian semiconductor industry even want anything from the academia (other than students?)

• Make this a win-win situation for all concerned (students, industry AND faculty)

IT WB • VLSI Design Park

– Near Kharagpur IIT Campus, Kolkata – 100 to 150 acres of land – 20 to 30 million dollar in investment. – To house companies in development, manufacturing and assembly line. – Directly linked with R&D at IIT – Joint Proposer - Mr. Deb Gupta, CTO of APSTL advanced Packaging & System Technology

Laboratories, USA and an IIT Alumni. – The state government is facilitating for

• Funds - Meetings with Consul General of Japan, Kolkata and Embassy of Japan, Delhi (by APSTL, US, IIT, Kharagpur and IT WB) have been held.

• Land – considering favorably Academia-Industry JV • BITS-RIT APEX (Applied research and professional Excellence):

– BITS Pilani – New York based Rochester Institute of Technology (RIT) – Indian Semiconductor Association (ISA). – Applied research lab in Bangalore – Focus on cutting edge semi-conductor research and would also have basic and advanced

courses. – BITS is investing around Rs 1.5 crore into the center – Come up in July.

VSI: VLSI Society of India • The purpose of VSI is to contribute and promote the advancement of all aspects of VLSI technology,

primarily in India: – To promote all areas relating to VLSI field - materials, technology, process, design, application

CAD/Design Automation, VLSI architectures, education, policies, etc. – To bring wide class of professionals from process technologies to specialists in VLSI architectures

on one platform. – To provide impetus to infrastructural growth for technology development. – To provide impetus to human resources development. – Conduct periodic seminars/conferences/workshops in this area. – To bring out quality publications. – To continually formulate national goals for a sustained and vibrant VLSI industry. – To evolve standards and frameworks for achieving effective synergy. – To establish relations with other similar associations, national or international.

VSI Activities • Regular Activities

– VLSI Design Conference (every Jan) – VLSI Design and Test Symposium (every Aug) – VLSI Education Day (every Aug)

• Other Activities – Curriculum Discussions, Surveys

– Focused workshops (Low Power, Memory, DFT, ...) – VLSI Education Workshops

• Publications – VSI Newsletter – Journal of the VSI

VED: VLSI Education Day • Observed as a part of VDAT every year since 2000 • The intent of VED is to bring together VLSI professionals in academia and industry and promote

education, research and development in all aspects of VLSI in India. • VLSI Education Day includes programs such as:

– Keynote speeches from eminent personalities – Panel Discussion on topics related to VLSI Education – Invited talks from VLSI professionals – Short tutorials on current topics – Book Exhibition, IEEE/ACM booths, University Booth – Poster Paper presentations from Indian Colleges

ISA: India Semiconductor Association • Setup in Nov. 2004 at IT.com at Bangalore

• ISA is the premier national-level body for the semiconductor technology-driven industry in India. It’s a new entity and truly a global body with the active participation of semiconductor companies from the leading markets, including the US, EU and Asia.

• Vision – To establish India as the preferred global hub for excellence in creation of semiconductor products

through technology leadership ISA: Mission & Objectives • The primary objective of ISA is to act as a catalyst for the growth of the semiconductor industry in

India. Other objectives include: • Create global awareness for Indian semiconductor industry outside of the generic “IT” umbrella • Create a win-win interaction amongst Semiconductor product and services companies, Government,

Academia, VCs and Industry bodies • Create an enabling ecosystem that catalyzes industry’s growth and leadership • Enhance Operational Efficiency • Identification of Investment opportunities • Foster active collaboration between Industry and Universities to further expand the available world-

class Semiconductor talent pool • Drive technology vision for the Semiconductor industry�� ISA: University Gateway Initiative (UGI)

• Objectives

– Invigorate research in semiconductors • Technology Leadership

– Create sustainable tread-mill for talent generation • Growth of India Semiconductor Industry

ISA: UGI: Focus • Focus Areas

– Research – Design Support & Fab access – Student projects – Faculty training, support, exchange

– Placement – Curriculum / Course ware development – VSI, MCIT collaboration

• Membership • Mentorship • Other Items ISA: UGI: Research • Research papers in international conferences

– An award system to create incentives – Travel grants for international conferences

• Create a SRC like forum – Participation from Industry & Universities – Identify key thrust areas of research – Invite & fund research proposals

• Publish a list of interesting research problems – Similar to top 10 problems in Physical Design from ISPD

• Arrange visits / talks from leading researchers • Technnovation Initiative

– ‘ISA-Technnovation Shield’ • Awarded every year to an Academic Institution that excels in Technology Innovations in

semiconductors and related areas – ‘ISA-Technnomentor of the Year’

• Awarded every year to a faculty member for outstanding contribution in Technology Innovations in semiconductors and related areas

– ‘ISA-Technnovators of the Year’ • Awarded every year to top 5 students in the country with outstanding performance in

technology innovation in semiconductors and related areas • Patents and Research Publications as the yard sticks for technology innovation • Technnovation Initiative

– ‘ISA-Technnowhizkids of the Year’ • Semiconductor Industry aims to emerge as future for our nation and so are the young

children in the school • The idea is to catch them young • ISA will partner with leading assessment institutions to create a nationwide contest on

‘innovative thinking’ • Top 5 school children will be awarded ISA Technnowhizkids of the Year Award

– ‘ISA PhD Fellowships’ • An incentive program to support top talent to pursue research in India • Will help fund the core research and provide financial scholarships to PhD students and

their guides • Will facilitate research collaboration with other nations in the world

• Technnovation Initiative – Life Time Achievement Award for Technnovation

• Awarded to a distinguished academician / researcher for significant contribution to Technology Innovations in India in the field of semiconductors and related areas

ISA: UGI: Design Activity – Support • EDA Software

– Leverage Infrastructure created by SMDP/MCIT – Work with MCIT to create a web portal for public domain tools – ISA Facilitate EDA software acquisition for members – (60+ universities already have access to EDA tools)

• Design kits

– Cell Libraries, I/O’s, memory compilers, process models • Fabs (SCL, TSMC), I/P (Artisan, Virage)

– Design flows & Methodology – Training to use the infrastructure – Quarterly reviews

• Fab Access – SCL, India Chip Program – TSMC Shuttle

ISA: UGI: Academic Interaction

• Student Projects – One of the Most frequent request – Create a database of student projects topics

• Cover wide variety of topics of interest • Solicit Ideas from member companies / Universities • Short duration projects to support course curriculum • Long duration projects used for practical training

– Need mentoring from industry (Technical, Financial) – Active participation from faculty – Background material for the projects

• Faculty & Student exchange – Internship programs for students – Faculty exchange programs

• Sponsored Sabbatical for summer in industry • Visiting faculty from industry for short duration (1 week)

• Placement – Major key incentive for the universities – Lack of information about activities in universities – Advanced placement (1 year ahead) – Facilitate placement activities for member universities

• Curriculum / Courseware – SMDP/VSI/Univ. have put together a good curriculum – Need to support curriculum with courseware

• Augment with practical & Projects – Courseware available electronically for wider usage

• MCIT / VSI – MCIT & VSI have been doing a lot of work in this area – Create partnership with MCIT to leverage infrastructure – Partner & support VSI for conferences / workshops

ISA: UGI: Membership for Universities

• Awareness / Value Proposition – Create awareness for opportunities in semiconductors – Publicize benefits for ISA membership – Create criteria for becoming ISA member

• Membership – Category-B – Membership Fee – Rs. 10,000 / year

• Access to Design kits • Support for student projects • Possible mentoring relationship with ISA companies

• Membership – Category-A – Membership Fee – Rs. 25,000 / year – Additional Benefits

• Technovation Initiative • Possible access to Fab-Shuttle program (Future) • Summer Sabbatical program for faculty

ISA: UGI: Mentorship

• Facilitate Mentor Relationship – Enlist ISA Industry members with commitment for

• Faculty hosting at their site • Support & guidance of student projects • Providing expert visiting faculty (Short-term) • Help with course-work & curriculum • Providing placement support for eligible universities

– ISA Plays a role of Facilitator based on needs ISA: UGI: Other Items • Create & Maintain database of university activities in India • Survey to project talent generation requirements over next 5 years • Work with MCIT on

– Hiring & Supporting additional faculty under SMDP-II program (2 per institutes) – Extend IEEE-Explore facility to member universities – Work with publishers to provide Indian edition of books

Summary

• We have a strategic position that ‘happened’ to us

• The opportunity is immense

• We are ahead - yet, competition is fast catching up

• We need to deliver through the production of abundant quality man power Contributors

• Dr. C P Ravikumar, TI

– As Secy, VSI

• Dr. G D Gautama, IT Secretary, WB Govt.

• Dr. Pradip Dutta, Synopsys

• Ms. Reena Mishra, Interra Systems

• Dr. Uma Mahesh, Insilica

– As Secy, ISA

A critical study of radio frequency radiations from VLSI circuits

Abhik Mukherjee CST Department BESU, Shibpur

1. Introduction

Research in VLSI is one of the major success stories of science and technology .The expertise has come from diverse fields, which include Physics, Chemistry, Material science, Manufacturing science, Physical electronics, Mathematics, Computer science and other allied disciplines. Advantage of all these disciplines in parallel has made it possible to realize the dream of integrating millions of transistors into a chip measuring one square inch in area. The technology is still maturing, as this remains one of the most sought after area of research for various disciplines.

Miniaturization of integrated circuits has today reached a technological advancement where it can be embedded within every product that may require some processing in its lifetime. However, electromagnetic interference within the chip among its components as well as with other adjacent chips is a major hurdle to miniaturization. Electromagnetic radiation is therefore emerging as a major component of VLSI research. In this report, some frontier areas of this aspect of electromagnetic interference and compatibility are outlined.

With the advancement of technology, it has become possible to attach a radio frequency tag to an item so that it may be tracked continuously. At the same time, radiations from VLSI circuits have been captured to reveal the kind of processing that the circuit is undergoing. This has raised issues of both privacy and secrecy, which requires attention of the circuit designers. However, the most challenging of the issues confronting the research community is the pronounced biological effects of non-ionizing radiation being emitted by the circuits that need to operate and communicate at high frequencies.

In Section 2, the radiations emanated by VLSI circuits are briefly introduced. Section 3 deals with antenna-coupled VLSI circuits. In Section 4, we explain the biological hazards, with evidence mostly from the domain of mobile phones. In Section 5, we conclude with note of what needs to be worked out.

2. Emanations from the circuit In this report, we are interested in one aspect of VLSI research, that is, the electro magnetic field produced by circuits with or without antenna. Over the years, the size has grown smaller and the speed of the operation has become faster. When processor is working at a clock speed of 3 GHz, the corresponding wavelength becomes (3 * 10^8 m/s) / (3*10^9 m/s) = 0.1m = 10 cm. As current flows in the IC around a loop, it produces a magnetic field and the IC now emanates electromagnetic waves at the high frequency and its harmonics while it is operating. The field around the IC will now interfere with that of other adjacent electro magnetic fields (EMF). The field will attenuate at a distance obeying inverse square law in the far field region. Analysis of this radio frequency radiation (RFR) is important, because its effect on performance of the circuit is substantial.

The analysis of RFR at a distance reveals information about the processing undertaken. Studies show that it has been possible to correctly trace the processing of RSA algorithm in progress through RFR by a receiver placed 50 ft away in another room [1]. This means that the secrecy expected out of such systems involving smart cards is under serious threat. If the remedial measures are not undertaken now, the technology may not be able to fulfill the expectations and may fall apart.

Apart from this, as the number of transistors keeps on increasing, total length of interconnects required also increases. So, the heating of the circuit will be substantial. Along with RFR, this heat will also bother the advancement of technology. In fact, simple power analysis of the line through which the processor works is also able to reveal important operations being performed by the processor. These approaches, termed as side channel attack, can expose the limitations of any strongly mathematical cryptographic function without getting involved in any actual mathematics. 3. Embedded system applications In embedded system applications, the focus is now on antenna-coupled VLSI chips. Mobile communication using small handsets has been possible because of technological advancement to deal with

antenna coupled VLSI circuits. Similar attempts in the field of nano-technology have yielded the concept of radio frequency identification (RFID). RFID tags are microchips with antenna strips that are embedded into any product for continuous future tracking [2]. While mobile communication (MC) is meant for far field, RFID (passive tag) is essentially a near field application. But there is a privacy issue associated with such systems, which needs immediate attention. The major constraint being the extent of space available, adding features to address the privacy related issues is difficult.

Miniaturization has today reached a stage where the manufacturers are contemplating the use of microchips that will radiate their identity at radio frequencies, which will be captured by RFID readers for authentication. Radio Frequency IDentification (RFID) is an automatic data capture technology that uses tiny tracking chips affixed to products. These tiny chips can be used to track items at a distance--right through someone's purse, backpack, or wallet. Many of the world's largest manufacturing companies would like to replace the bar code with these, meaning that virtually every item on the planet--and the people wearing and carrying those items--could be remotely tracked.

However, items containing liquid or metal are especially hard to chip. Liquids tend to absorb the electromagnetic energy needed to power the chip, while metal tends to reflect it and bounce it around in unpredictable ways. Both problems can cause interference in the RFID signal sent by a chip to the reader. Traditional metal shelving has to be replaced with new-fangled plastic shelves, to prevent interference with RFID transmission.

There are two types of tags: passive ones with no independent power source and active ones containing a battery. Depending on a number of factors like antenna size, RF frequency, environmental conditions etc. a passive tag can have a range of anywhere from 1 inch to 40 feet. Active tags can have a read range of miles or more. Most tags being considered for use in consumer products are passive.

While intrusion into privacy is an important issue, devising some technology to prevent intruders from accessing information is challenging. Given the intended size of the tag, it is difficult to put too much processing into such a small space. Without strong encryption and authentication algorithm, secrecy or privacy cannot be guaranteed. This is one area where a lot of work is expected to be performed over the next few years.

4. Biological implications Far away from all the advancements, one major challenge faced by the researcher is to deal with

impact of RFR on biological tissues. Embedded systems have now established their all-pervading presence in our homes. The amount of RFR has also become substantial. If they interfere with the performance of another, there is no escaping the fact that this RFR will interfere with organism. After all what else is a biological organism but a complex electronic circuit? World Health Organization (WHO) has come up with safety standards for non-ionizing radiations. It is important to know the major effects on the tissue and critically analyze the present safety standards for adequacy. It is worthwhile to set higher safety standards and think in the lines of achieving them in the country. 4.1. Thermal effects of RFR

Microwave ovens work on the principle of breaking dipole moment of water and in the process they heat up the food inside the oven. Similar things can happen to biological living tissue. The heating effect will obviously be more pronounced in case of high power devices applications.

WHO has classified RFR as a non-ionizing radiation. In the literature, the major point of concern is the heat generated as the RFR gets absorbed in the tissues. The Specific energy Absorption Rate (SAR) is different for skin, muscle, fat types of tissue. If the conductivity of the tissue is S siemens (r^-1m^-1), the amount of electric field is E volt/m and density of the tissue is r kg/m^3, then the SAR is expressed as SAR = (S*E^2/r) watt/kg. The conductivity and density are properties of the tissue and depends on type of tissue. There, the absorption of RFR will depend on electric field. With rise of SAR, the tissue gets warmer – which in turn results in a series of reactions. The tissues of the reproductive organs like testes maintain a temperature 2-3 degrees C below the normal body temperature to protect the activities of sperm. Rise of temperature near these tissues will mean that the balance has to be restored through the blood circulation system which is poor in this region.

Localized heating of tissues near regions with limited blood circulation has dangerous consequences. Eye and brain also has this problem of heat absorption since it is not compensated with circulation of blood. There is no element of surprise in the fact that epidemiological studies [8] conducted

in developed countries over the years indicate an association between melanoma of the eye or brain tumour with excessive use of mobile phones. All biological organisms run the risk of absorbing RFR. So, for the ones with lightweight, the total heat absorbed is high. Further, when the wavelength of the RFR matches with the dimension of the organism, there is resonance. At resonance, the body becomes a receiving antenna and a surface current (charge) flows through the organism. One reason behind house sparrows getting extinct due to RFR or diminished cocoanuts is arguably this RFR absorption phenomenon. So far, animal experiments conducted over rats have shown that tumour can be formed in the brain through prolonged exposure to microwaves similar to that in use for mobile [4]. 4.2.Non-thermal effects

Unfortunately, there is both logic and evidence that RFR can affect at low power levels as well. The nervous system acts on the stimulus of potential difference caused by imbalance of sodium (Na) and potassium (K) ions inside and outside the neurone. Even a small electric field of RFR at high frequency is capable of disturbing this imbalance of ions. The brain has to overwork to restore the balance.

Permeability of substances in Blood Brain Barrier (BBB) significantly increases under the effect of high frequency RFR. These can happen at low power levels and this increased permeability is capable of damaging the BBB [3].

Another effect of low power RFR is the sleeplessness, which in turn results in reduced secretion of Melatonin. Melatonin is known to be a major immunological agent that prevents cancer. Epidemiological evidence of such effects is feeble [7], but the biological research community has enough reasons to backup the findings. Abnormal growth of nematode worms has been found in experiments and reported in [4]. This implies that the adverse effects of RFR cannot be ruled out in any way. The DNA molecule has weak bonds between Phosphate and hydroxyl ions. Such bonds can be easily broken in the presence of electric or magnetic field by detaching an electron involved in the bond. As far as repair of DNA is concerned, once again presence of EMF obstructs the process by exerting its share of force on molecules. This unnecessary breaking of DNA strands may trigger off uncontrolled multiplication of cells and thus malignancy.

RFR damage of tissues will invoke a repair mechanism that may go out of control and trigger cancer. RFR at low power level is capable of breaking DNA strands through ionization of tissues [3,8], distortion of chromosomes and delays in cell repair. This can increase genetic aberration that gets carried forward to next generation. Cells are surrounded by protective membranes consisting of proteins and fats. The lipid membrane become leaky in the presence of external magnetic field. This in turn distorts the protein configuration of the membrane. Now, proteins act as receptors and are responsible for controlling flow of substances in and out of the cell. So, once this gets distorted, the cell is susceptible to toxic substances. It has been experimentally verified in mice that the cells within breast cancer tissues grow faster than the normal cells in the presence of low frequency magnetic fields [4]. Maintenance of ionic equilibrium is one of the major tasks of the cell. EMF tends to destroy the equilibrium. It is known that ionizing radiation does this by putting unbalanced ions into the cell, thereby breaking molecular bonds. On the other hand, the non-ionizing radiation produces an electric field and magnetic field around the cell, to which the cell molecules respond under certain complex conditions. Interaction among the various tissues is complex and non-linear in nature and what has been verified on experimental animals may not occur in actual human scenario. Results of some detailed epidemiological studies are given in [7]. However, studies near the base station are yet to be conducted rigorously. 4.3.WHO standards and the national scenario WHO has formed International Commission for Non Ionizing Radiation Protection (ICNIRP) and has argued all countries to formulate regulations. United States has regulated SAR to 0.08 w/kg for general public and 0.2 w/kg for occupation [5]. China has even more stringent regulations and have fixed their standard at 0.02 w/kg for general public [3,5]. Detailed restrictions for E (electric field), H (magnetic field) intensities are imposed in the advanced countries [5]. Now there are similar restrictions to protect from the effects of EMI as well. However, there is so far no bar imposed on export of non-standard equipment to countries without such standards. India and Bangladesh are countries without any instrument to protect RFR and with unknown standards as per WHO document [3]. WHO has urged all countries to develop a uniform framework for harmonization of standards in the lines of GATT and WTO recommendations. Until that takes effect, these countries cannot stop importing equipment that poses serious health hazards.

We shall discuss the issue in the context of mobile phones, one important far field application of antenna-coupled embedded systems application. Let us consider the restriction posed by ICNIRP on mobile phone. As per norms, they can transmit only 2w at 900MHz frequency. When the tower is located at a distance 1km from the mobile, the tower gets RF signal of intensity around 2w/4π (1km)^2 = (2/4π )*10^-6 w/m^2 . Now, if the effective aperture of the antenna is Ae = Gλ^2 / 4π from antenna theory, the received power will be (taking gain = 1), P(1km)=(2/16π ^2)*10^-6*(1/3)^2 watt, Since λ = 3*10^8 m/s / 900MHz = 1/3m i.e. the wavelength of 900 MHz is 1/3m and hence P (1km) is order of nanowatts or – 90dB or – 60dBm. At a distance of 10 km, this power will become P (10km) of the order of 0.01nw or – 80dBm or –110dB. It requires very much sophisticated and costly device to receive such small power. Now, it is obvious that mobile phones are not designed to work with so small power. Even 1 microwatt or –30dBm is difficult to detect through the antenna. Hence, if the base station is 10km away, is order to produce 1microwatt at the mobile, it has to radiate at 1kw at least. This 1kw at a distance of 100m from the base station will produce a power of about 1w, which far exceeds the permissible exposure limit. So to maintain quality of service at a distance of 10km there is health hazard around the base station itself. Solution is either to restrict cell range to within 1km (then the exposure comes to 10mw at 100 m distance, permissible up to 40 mw) or resort to systems that can operate with signals at much lower power levels. In the vast rural areas of India, it is common to find towers spaced far apart and thereby radiating high power, because of low subscription. This practice must be put to proper perspective, given the hazards associated with such high power RFR. 5. Conclusion In this report, we have tried to highlight the electro-magnetic radiations from embedded VLSI circuits and their effects on biological organisms. So far, the approach taken to tackle RFR from circuits is inadequate. Circuits keep on revealing secret information to the outside world. In case of embedded antenna-coupled systems, working with higher signal strengths must be discontinued because of risks of privacy and secrecy. Given the emerging facts about adverse biological effects of RFR, which are not merely thermal, research has to shift its attention to find the new threshold below which it will remain harmless. Of course, the technology must advance to a stage where circuit activities can be kept below the new threshold as well. India is expected to lead in this venture, since they are yet to set any standards.

Acknowledgement The author acknowledges Durjoy Majumder, research scholar of Physiology and Bio-Physics at Saha Institute of Nuclear Physics, for fruitful discussion and supply of articles in biology. The services of Subhankar Dasgupta, ME student of CST Department of BESU is also acknowledged for providing useful reference and helping in the compilation of the article. Reference

1. D Agarwal, B Archambeault, Suresh Chari and J R Rao, Advances in Side-channel cryptanlysis: Electromagnetic analysis and template attacks; RSA Labs Cryptobytes Vo. 6 No. 1 pp. 20-32, 2003.

2. S. Weis, S Sarma, R Rivest and D Engels, Security and privacy aspects of low cost radio frequency identification systems, AutoID Lab MIT, 2004.

3. Abdullah AlOrainey, Recent research on mobile phone effects, Proceedings of the International Conference on Non-Ionizing Radiation, 2003.

4. Premalatha Das, Health effects of Radio frequency radiations, Proceedings of the International Conference on Non-Ionizing Radiation, 2003.

5. World Health Organization website http://www.who.int/docstore/peh-emf/EMFStandards/… 6. World Health Organization website http://www.who.int/peh-emf/standards/framework/en/ 7. M Kundi, KH Mild, L Hardell and M Mattson, Mobile telephones and cancer – a review of

epidemiological evidence, Journal of Toxicology and environmental health, Part B:7,pp. 351-384, 2004.

8. Omprakash Gandhi, Biological effects and applications of electromagnetic radiations, Prentice Hall, 1996.

9. A. Bhanu Labanya, Effects of EM radiations on biological systems: a short review of case studies, 8th International Conference of Electromagnetic interference and compatibility, pp. 87-90, 2003.

VLSI Physical Design in Deep Sub-Micron: Some Recent Issues

Parthasarathi Dasgupta

Indian Institute of Management Calcutta Joka, D. H. Road, Kolkata – 700 104

E-mail: partha@iimcal.ac.in The semiconductor industry has witnessed device size miniaturization as guided by Moore’s law for more than a quarter of a century. This has allowed dense packing of transistors while the improved transistor performance has resulted in significant increase in frequency. Design of high performance integrated circuits with process technologies at 0.18 micron or below is highly complex, and poses major challenges of recent times. This is primarily due to the finer geometries, design size, high clock frequency, and low voltage. We briefly discuss some of the recent challenges in physical design of VLSI circuits in deep sub-micron (DSM) regime. VLSI physical design starts from a gate-level description (I/O pads, RAMs, IP blocks, logical gates, and flip-flops), and ends up with a GDSII (or the recently proposed OASIS) file describing the layout. This entire process involves constraints on timing requirements, area, placement of logic modules and buffers, routes, power consumption, clock skew control, and technology constraints. Interconnection of a net comprises a set of wire segments, called interconnects, connecting all the pins of the net. With increased downsizing of geometries, interconnect delay, which depends on the capacitance and resistance of the nets dominates over the gate switching delay. Interconnect delay is also affected by the coupling capacitance between interconnects in the same layer placed in close proximity to each other. Recently, a 3-phase interconnect-centric design flow has been proposed, which includes interconnect planning, interconnect synthesis, and finally interconnect layout. Interconnect planning is important because it provides early assessments on the system performance, thereby enabling performance optimization. Additionally, it tends to reduce design uncertainty, and ensure that the planned results can actually be implemented in later design flow. Due to their distributed nature, interconnects have become much more difficult to model and optimize in the deep sub-micron domain. Interconnect delay is roughly determined by the driver or gate resistance, interconnect and loading capacitance, and the interconnect resistance. The most preferred delay estimator is the Elmore delay estimator, though linear and other estimators have also been used. One of the major concerns is the lack of a useful metric for measuring the performance of an interconnect architecture vis-à-vis electrical and material parameters. Routing of interconnects in VLSI use buffers (or repeaters) primarily for reducing the delay. Buffers are devices placed along interconnect, that also help control the attenuation of signal levels, increase the drive strength for a gate that is driving a large load, and are used to shield a critical path from a high-load off-critical path.

Floorplanning and Placement are classical problems of physical design with emphasis on layout area minimization. In recent times, they have to be aware of several design parameters. Unlike considering only area, there is a need of an open cost function, which can analyze timing, area, power, congestion, signal integrity, and others. Some recent works consider the integration of interconnect planning and buffer block planning with floorplanning. Design of a complex system, comprising a large number of components is difficult without partitioning, i.e., decomposing it into smaller subsystems. On decomposition in a recursive manner, each subsystem can be designed independently. This process is widely applicable in hierarchical design strategies for a VLSI, and is commonly referred to as partitioning. Partitioning of an electrical circuit depends on certain parameters like interconnection between the partitions, delay due to partitioning, number of terminals, area of each partition, and the number of partitions. The placement phase determines the exact locations of the circuit blocks and pins. Outcome of placement phase is a netlist, which defines the required interconnections. Space unoccupied by the blocks is a collection of regions to be used for routing. Global routing generates an approximate route for each net. On the other hand, detailed routing involves the actual assignment of the routing regions. Global routing algorithms are broadly classified as those using sequential approach, and concurrent approach. The classical objective function used for global routing algorithms is the total wire-length. In the context of DSM regime, several new objectives are used to improve the performance. These include delay minimization, satisfying the required arrival times at a source of a net for a pre-specified required arrival times at a set of sink terminals of the net, minimization delay for the critical sinks of a net, and so on. When there is too much current density through an interconnect for a prolonged interval of time, the resistance increases. This results in self-heating and metal disintegration, leading to an open or short in the circuit. This is called electromigration. It is defined as mass transport in solid-state metals under high current densities, resulting in a change in conductor dimensions. This effect is more acute for DSM circuits. Electromigration is often addressed much earlier in the design flow, by calculating the required width of an interconnect as placement and routing are refined. Design for Manufacturability (DFM) is a new buzzword in the VLSI design community. Below 0.13 micron, there is an interaction between design and manufacturing issues, leading to reduction in the yield. This results in new interesting challenges for the designers: factors related to manufacture have to be considered in the design solutions. In summary, with ever shrinking sizes of the chip geometries, design researchers and engineers are faced with more and more stringent performance requirements, and are facing new challenges, some of which are radically different from the classical problems, and hitherto unknown.

VLSI Education: The Indian Scenario

Susanta Sen Institute of Radio Physics & Electronics

University of Calcutta Late 70’s and Early 80’s • Analog Circuit Design

– Differential Amplifiers – Current Mirrors – Wide-band Amplifiers – Phase Locked Loops

• CMOS Design – Mead & Conway – Scalable Design Concept

• CAD Tools were few & expensive • VLSI Industry in India

– Virtually non-existent Late Eighties / Early Nineties • Digital Design (CMOS) Started Dominating • New Technologies/Concepts

– Programmable Logic Devices: FPGA, CPLD – Hardware Description Language: VHDL, Verilog – Free Tools appeared on the scenario

• VLSI Design Conf. Initiated in India in 1985 • More Institutes initiated the program • Computer Science & Engg. Depts. joined in

– Training in CAD Tool Design started Change of Industrial Scenario • Rising Engg. Costs in Advanced Countries • Global Recession • Performance of Indian Expatriates

Major Players in the Field considered India as a viable alternative Design Centre

•Started with Tool Design

• Migrating to Chip Design • Many fold increase in manpower requirement 18th International VLSI Design Conference, Kolkata, Jan. 2005 (Industry – Academia Panel) • Indian Human Resource Scenario

� Requirement – 10,000 trained personnel � Present training – a few hundred per year � Strong emphasis on training required

• Proposal for a Finishing School ������������������������������������������������������������������������

Whom are we going to finish? They are already finished ! - Dr. P.P. Das General Chair

Initiative at INRAPHEL • Proposal to start M. Tech in VLSI Design

� Industries agreed to provide active support � Xilinx donated software tools and hardware kits � DC meeting – Feb. 16, 2005 � BPGS – March 9, 2005

• Self Financed Course � Course Fee : Rs 24,000/- per semester � Proposed intake – 10 � To be increased to 20 later

• Active Industry Participation � Visiting/Adjunct faculty � Project work

Regulation changes • Admission on the basis of entrance test • Eligibility: B.Tech/B.E. in RPE/ECE/CSE/IT from CU or any

recognized University and also EE from IITs • Project : 1½ semester (9 months) in Industry • Continuous evaluation

� Assignments : 30% � Sessional assesssment : 30%

� Semester-end Exam : 40% Course Structure

Semester - I

Discrete Mathematics–Graph Theory & Combinatorics (50)

Data Structures and Algorithms – Graph algorithms relevant to VLSI Design (50)

Physics of VLSI devices (50)

Microelectronics Technology (50)

OO Programming and Language Translation (50)

CMOS VLSI Design (50)

CAD Techniques: I – Spice, VHDL/Verilog (design entry & simulation) (100)

Semester – II Design Verification and Testing (50) Low Power Design (50)

RF, Analog and Mixed Signal Design (50)

Processor Organization and Architecture (50)

Digital Signal Processing (50)

ASIC/Memory Design (50)

CAD Techniques : II – Physical Design, DRC, Parameter Extraction, Simulation (100)

Semester – IIIA (3 months) Design of VLSI CAD Tools (50)

System-on Chip/Embedded Systems (50)

FPGA Lab (100)

Semester – IIIB (3 months) Thesis Prelim (100)

General Viva Voce (100)

Semester - IV

Thesis (400)