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VLSI DESIGN AND FABRICATION FOR LIQUID CRYSTAL ON SILICONIan Underwood*

AbstractThis paper attempts a very brief review of the principles of, and some recent advances in, the designand custom fabrication of silicon chips for use with liquid crystals in spatial light modulators andmicrodisplaysIntroductionLiquid Crystal on Silicon (LCoS) is now well established as a generic technology' for theproduction of microdisplay engines (also known as Spatial Light Modulators or SLMs). A typicaldevice has a CMOS active backplane containing a rectangular array of square pixels in which eachpixel contains a storage element which is permanently electrically connected to a metal mirror onthe top surface of the chip above the pixel. The storage element may be analogue or digital innature. The pixels are generally addressed in an orderly fashion, e.g., row sequentially. A frontglass plate, coated on its inside surface with a transparent conductor such as indium tin oxide (ITTO),is bonded to the surface of the chip in such a way as to define a precisely set and constant (acrossthe pixel array) gap of typically one or two microns. The gap is filled with liquid crystal. Aschematic cross section of such a device is shown in Figure 1.

Fiswre 1 Schematic cross section of LCoS deviceThe principle of operation, as shown in Figure 2, is that a voltage applied between the mirror of apixel and the front electrode causes an incident beam of light to be modulated in reflection. (The* The author is with The University of Edinburgh, Department of Electronics and Electrical Engineering, The KingsBuildings, Mayfield Road, Edinburgh EH9 3JL. Telephone 0131 650 5652, email - i.underwood@ee.ed.ac.uk, homepage - http://www.ee.ed.ac.uk/-sld

7/1 0 2000 The Institution of Electrical Engineers.Printed and published by the IEE, Savoy Place, London WC2R OBL, UK.

mailto:i.underwood@ee.ed.ac.ukhttp://www.ee.ed.ac.uk/-sldhttp://www.ee.ed.ac.uk/-sldmailto:i.underwood@ee.ed.ac.uk

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pixel mirrors are, of course, individually programmable while the IT0 counter electrode iscommon.) The nature of the modulation depends upon the surrounding optical components; it canbe, for example, amplitude or phase. Typically, no voltage leads to a dark state while an appliedvoltage leads to a bright state. In the case of an analogue device, the brightness of the bright staterises with the applied voltage.

input modulatedlight light

polarizer I I I 3analyzercover

\ I alignment layerFigure 2. Cross section through a pixel showing ~ r i n c i ~ l ef oDeration

Nt

Fiaure 3. Outline schematic of MlNDlS backDianeOn the CMOS backplane, the pixel array (M rows by N columns, say) is surrounded by circuitrywhich allows the array to be addressed as required. Thus the row address circuit typically consistsof a Mxl bit shift register or decoder used activate the rows one by one so that data may be writteninto them. The column address circuit involves demultiplexing to allow the data (which is to betransmitted into a given row of pixels) to be assembled from a manageable number of bonding pads

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(e.g., 64) nd subsequently transmitted onto the (e.g., 1280) column bus lines. Figure 3 shows anoutline schematic of a recent backplane2.Analogue DevicesFigure 4 hows a typical circuit for a pixel driven by an analogue signal. It consists of a MOSswitch gating charge onto a MOS (illustrated) or poly-poly capacitor. The row and column buslines are also shown. As most liquid crystals are driven by a voltage or electric field, the charge onthe capacitor suffices to drive the LC.Some issues and limitations associated with this circuit include

the storage node is a soft nodethe storage node is a subject to charge leakagethe storage node is subject to noise from adjacent driven nodesthe storage node must store enough charge to fully switch the liquid crystal, especiallypertinent if the LC is ferroelectricthe dynamic range of the voltage stored is much less than the power supply voltage of thechip

column data busTI row address bus

Fiwre 4.Twical dvnamic Dixel circuitIn order to minimise the effects of the issues mentioned, the design and layout of this simple, inprinciple, circuit becomes involved. The solutions include the use of

light blocking metal layer(s)earthing metal layer@)guard rings and substrate ties to minimise leakage

additional designed in storage capacitor elementsboosted or separate supply voltages for the row and column drivers

This style of circuit performs perfectly adequately in a number of microdisplays aavailable today.In my opinion, the performance of this type of pixel could be improved by the use of stacked ortrench capacitor elements such as those used in custom dynamic random access memory (DRAM)chips. I am not currently aware of any SLM devices which are fabricated in a DRAM process.Digital DevicesThe circuit of Figure4 an, of course, be used to supply a digital signal to drive the LC, irrespectiveof whether the LC is itself inherently binary in operation. Digital drive to such a circuit has beenused extensively to drive binary or bistable ferroelectric liquid crystal ( FK) SLMs. Thesematerials have the advantage of much faster switching over the more common nematic materials.The combination of digital drive and fast switching is used to implement binary weighted bit-planesequential colour in micro display^^.

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Vpad

Figure 5. Buffered SRAMpixel drive

-In the case of FLC devices, the circuit of Figure 4 can be replaced by one based on static logic, suchas a 6-transistor static random access memory (SRAM) cell. In practice, the storage node is oftenbuffered from the SRAM as shown in Figure 5. This circuit overcomes all of the weaknesses of the DRAM circuitfor digital drive at the expense ofmore transistors. However, with currently available sub-micron CMOS technology, this level ofcircuit complexity is not a problem as it can easily fit within the 10 to 15pm pixel pitch of a typicalmicrodisplay. Light-blocking is still required to guard against latchup.SophisticatedDigitalPixelsThe design of additional functionality into the pixel can be used to boost the performance of thepixel. This is illustrated here for digital pixels.Consider Figure 6 which shows a typical time sequence for displaying a bit-plane of data on adigital microdisplay engine. It is necessary to load data into each of the rows sequentially (address1) then wait for the LC n the last row to switch (settle 1)prior to illuminating the display showingthe required pattern; it is then necessary to repeat the process, loading the inverse data withoutillumination in order to DC balance the material. The image may be valid for only a small fractionof the overall time thus imiting the brightness of the display.

data field inverse data field-mage validFimre 6. SimDle time seauence for disDlaying a bit-Dlane of data

A XNOR or XOR gate used as a buffer between SRAM storage node and LC drive node4: allowsthe data pattern to be transformed into the inverse data pattern in one clock cycle thus reducingAddress 2 time effectively to zero.The inclusion of two independent 1-bit storage nodes into the pixel allows the loading of the datafor bit-plane n+l to occur simultaneously (rather than sequentially) with the optical interrogation ofbit plane n.In the latter case, the need to load data into the array in a short intense burst during the addressphase (the so called data bottleneck) is eased; data can be sent virtually continuously. In both casesthe frame time is decreased and/or the illumination duty cycle is increased.

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Peripheral IssuesIn the past, the periphery of the array has often been much more sparsely populated than the pixelarray itself. However, an inherent advantage of CMOS is the potential absorption of interfacingand data processing components onto the SLM backplane - he display equivalent of System onChip (SOC). This is an area where individual companies may attempt to distinguish their products.Microdisplay Corporation, for example, offers a 640x480backplane with on-chip NTSC and VGAdecoders.Efficient planarisation is more easily achieved when the circuit and interconnect density is much thesame across the whole chip. One way of doing this is to place "dummy" pixels around the peripheryof the array. A more likely future way is the intelligent layout of on-chip decoders etc to give thesame average circuit density as the array thus offering a planarisation friendly approach to SOC.Wafer FabricationThe implementation of planarisation techniques for wafer fabrication has allowed the use of almostthe full pixel area for both circuitry and pixel-mirror. These have recently been reviewedelsewhere6. The newly developed Self-aligned Insulator Filled Trench (SIFT)7 process showsparticular promise. Figure 7 shows an AFM image of the comer of 4 djacent pixel mirrors from aSIFT processed wafer. The inter-mirror gap is almost exactly co-planar with he mirrors. While thetextures are different, the effect of this is largely masked by the universally applied alignment layer.

Firmre 7.AFM mage art of SIFT Drocessed backplaneThe use of multi-level metal has allowed the implementation of an effective strategy for preventinglight reaching the CMOS substrate. The use of customised post-processing (e.g., SET) has allowedthe deposition of mirrors whose surface is optimised for high reflectivity, low scattering and goodliquid crystal alignment. Microfabricated spacers have been demonstrated*, hus allowing one morestep of the cell assembly process to be carried out as part of the wafer fabrication post-processing.Wafer scale cell assembly techniques have been developedg for improved device manufacturability.Example MicrodisplayEnginesTo give some feel for the state of the art, IBM has published results on a research device with2048x2048 analogue-drive pixels on a 17pm pitch" and a frame rate of 74Hz.The state of the artin commercially available digital devices is around 1280x1024 (SXGA)with a pixel pitch ofaround 12pm and a bit-plane rate of more than 1kHz.

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Technology EvolutionSilicon is moving towards smaller geometries, larger wafers and the option of larger chips. SLMsand microdisplays will be able to shrink in pixel size, increase in pixel count and increase in pixelfunctionality. However, metal dimensions (crucial in determining fill factor) are shrinking moreslowly than other dimensions while silicon is also migrating towards lower voltages. Lowervoltages mean slower switching of the LC layer.The birefringence of current LC materials limits LC thickness to no less than about 0.8,um foroptimum modulation depth at which thickness pixel dimensions are unlikely to go much below,say, 5pm in order to prevent edge effects from becoming dominant. Smaller pixels will require thedevelopment of higher birefringence materials or have to accept lower modulation depth.In the near future I expect to see alignment layers and glue layers patterned as part of the postprocessing procedure. We may also see SLMs and microdisplays fabricated on processes other thanplain logic CMOS (or the microdisplay equivalent), such as BiCMOS processes for fasteraddressing and DRAM or SRAM processes for optimised pixel perfomance.We are currently carrying out research on manufacturability issues for LCoS (EPSRCGR/M13534), on CAD tools for the integrated optical and electronic design of LCoS devices(EPSRC GW39305) and the development of devices using novel antiferroelectric materials(ESPRIT LTR. 6300)AcknowledgementsI wish to thank Mark Newsam for Figures 1,2 and David Calton for Figure 7.

References . Underwood; Liquid crystal over silicon . .TOPSVol 14, Spatial Light Mods, pp76-88, 1997L. Chan et al; Miniature Information Display System, OSA Tech Dig on SLMs, ppl0-11, 1999N.A. Clark et al; FLC Microdisplays, Ferroelectrics, to be published. Currently downloadable fromhttp://w.disDlavtech.com/comtech.html

I-Underwood et al; Evaluation of annMOS VLSI array . , EEh o c J, pp77-82, 1986.D.C.Burns et al, A 256x256 S W - X O R pixel ...,Opt. Comm., pp 623-632, 1995.A.J. Walton et al; A review of the history and echnology . .,Proc SPIE 3891,25-38, 1999 .W. Calton et al: Liquid crystal flow control . , ubmitted for publication, 2000.*E.G. Colgan et al; On-chip metallization . IBM J Res Develop, pp339-346, 1998

C. Berliner et al, Wafer-scale manufacturing ofFLCMicrodisplays, Proc Displayworks 2000 Man Tech Co d.lo J.Sanford et al; Silicon light-valve array chip ..., BM J Res Develop, pp347-358, 1998

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