Text Book: Silicon VLSI TechnologySilicon VLSI Technology … · 2015-04-22 · Backend - Chapter...

Backend - Chapter 11

Text Book: Silicon VLSI TechnologySilicon VLSI Technology

Fundamentals, Practice and ModelingAuthors: J D Plummer M D DealAuthors: J. D. Plummer, M. D. Deal,

and P. B. Griffin

SILICON VLSI TECHNOLOGYFundamentals, Practice and ModelingBy Plummer, Deal & Griffin

© 2000 by Prentice HallUpper Saddle River NJ


Frontend vs. Backend

Backend

Frontend



2


Backend Technology

• Backend technology: fabrication of interconnects and the dielectrics that electrically isolate them.

• Early structures were simple by today's standards.Oxide

Sili

Aluminum

N+

Oxide

Silicon

• More metal interconnect levels increases circ it f nctionalitincreases circuit functionality and speed.

• Interconnects are separated into local interconnects (polysilicon, (p ysilicides, TiN) and intermediate-global interconnects (Cu or Al).

• Backend processing is becoming more importantbecoming more important.

• Larger fraction of total structure and processing.

• Starting to dominate total speed



3(From ITRS)

of circuit.


Interconnection Considerations

• Wire lengths– Intra-cell routing

I t ll ti

TI Presentations Slides:Impact of (Metal) Interconnect Scaling and Process Variation on Performance, Mayur Joshi, Nagaraj NS, Anthony Hill, Texas Instruments (http://www cmoset com/uploads/Joshi pdf)– Inter-cell routing

– Local intra-block routing– Global inter-block routing, clock, power

Si ifi C

(http://www.cmoset.com/uploads/Joshi.pdf)

• Significant Concerns– Wire resistance– Wire capacitance– Signal skew (interconnect variation)– Wire delays vs. gate delays (wire beginning to dominate)

• Inherent Considerations– Planarization– Vias vs. lines– Local interconnect



– Connection to gates

4


ITRS ProjectionsMETAL 2

METAL 1METAL 1

W VIA

W CONTACT

POLYCIDE

Year of Production 1998 2000 2002 2004 2007 2010 2013 2016 2018

Technology Node (half pitch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm

MPU Printed Gate Length 100 nm 70 nm 53 nm 35 nm 25 nm 18 nm 13 nm 10 nm

Min Metal 1 Pitch (nm) 214 152 108 76 54 42

Wiring Levels - Logic 10 11 12 12 14 14

Metal 1 Aspect Ratio (Cu) 1.7 1.7 1.8 1.9 2.0 2.0

Contact Aspect Ratio (DRAM) 15 16 >20 >20 >20 >20

STI Trench Aspect Ratio 4.8 5.9 7.9 10.3 14 16.4

Metal Resistivity (µohm-cm) 3.3, 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2



5

Interlevel Dielectric Constant 3.9 3.7 3.7 <2.7 <2.4 <2.1 <1.9 <1.7 <1.7


Interconnect Structure• The speed limitations of interconnects can be estimated .

CI • The time delay (rise time) due to global interconnects is:

L

to global interconnects is:

HWLR⋅

⋅= ρ

HWLSCS

R

SiO2xox

HW

OxOx

IS

LHLWCCC

⋅⋅⋅+

⋅⋅⋅=

+=

00 εκεκSi

⎟⎞

⎜⎛

⋅=L RC

11

89.0τ(1)

SOx Lx

⎟⎟⎠

⎞⎜⎜⎝

⎛+⋅⋅⋅⋅⋅⋅=

SoxooxFringe WLHx

LKK 1189.0 2ρε

where Kox is the dielectric constant of the oxide, KI accounts for fringing



6

ox I g gfields and ρ is the resistivity of the interconnect line.


Analysis of Relationships

• Assumptions: Ls and W close to minimum feature size (Fmin), xox and H scale with Fmin (xox =0.35 Fmin and H=0.25 Fmin), keeping the aspect ratio H/W constant K =2 L related to chipkeeping the aspect ratio H/W constant, KI=2, L related to chip area (sqrt(A)/2).

( )2min

89.0F

AK ooxL ⋅⋅⋅⋅= ρετ

W

Poly

10-9

10-8

Poly

(ρ= 5 0 0

μΩcm )

c) i 2WSi 2

W

τg10-10 Al

W τg

Poly (ρ

W Si2 (ρ

= 3 0 μΩ

c m )

W(ρ

= 1 0 μ Ω

c m )

ρ= 3μΩ

c m )

τg

y Ti

me

(sec

Cuτ L

WSi 2W

Al

1 10 100

Fmin = 0.25 μm10

10

-12

-11

1 10 100

Fmin = 0.5 μm

W Si W (

A l (ρ

= 3

1 10 100

Fmin = 1 μm

Del

ay τ L

τ L



7

1 10 1001 10 1001 10 100Chip Area (mm2)


Reviewing Projections

• 9-12 level wiring• Cu interconnect metal

i h i• High aspect ratios contacts, vias, and trenches

• Small dielectric constant• Metal Line > Gate Lengthg• Metal >50% circuit delay


Technology Node (half pitch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm


Min Metal 1 Pitch (nm) 214 152 108 76 54 42 ( )

Wiring Levels - Logic 10 11 12 12 14 14


Contact Aspect Ratio (DRAM) 15 16 >20 >20 >20 >20

STI Trench Aspect Ratio 4 8 5 9 7 9 10 3 14 16 4



8

STI Trench Aspect Ratio 4.8 5.9 7.9 10.3 14 16.4

Metal Resistivity (µohm-cm) 3.3, 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2



Historical Basis

• Aluminum– Used for contacts and interconnect

R bl i ti it– Reasonable resistivity– Adheres well to Si and SiO2

– Good contact to doped SiI t t ith SiO t f Al O d ill f ilit t t t th h– Interacts with SiO2 to for Al2O3 and will facilitate a contact through the inherent oxide barrier layers that naturally grow on silicon

– Can reduce other oxidesCan be etched and deposited easily– Can be etched and deposited easily

• Concerns– Contact resistance - Silicides

S iki i ti th h h ll j ti ( itt f )– Spiking or migration through shallow junctions (emitter of npn)– Metal migration in regions of high current– … and more



9


Material Resistivity



10


Contacts

• Early structures were simple Al/Si contacts.• Metal-semiconductor junctions form Schottky contacts

• Depending upon the properties they may be ohmic or diode like• Highly doped silicon regions are necessary to insure ohmic, low

resistance contacts. • For highly doped regions ND, NA > 1020 cm-3

Aluminum

OxideN+

Oxide

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛=

D

sBcoc N

mh

εφρρ

*2exp (2)

Silicon⎠⎝ DNh

in ohms-cm2



11


Contacts - Energy Bandsthermionic emission

Contact resistance definition

Schottky = rectifying

Tunneling thermionic emission

Contact resistance definition

tunneling

Tunneling contact

xd is approx. 2.5 nmresults from Nd=6. 1019 cm-3



12contact area


Contact Resistivity (ohm cm2)

ρc|1019cm-3=5.9•10-2Ωcm2ρc| c .9 c

ρc|1020cm-3=6.7•10-6Ωcm2

ρc≈10-9Ωcm2 will be needed



13


Contact Evolution• Another practical issue is that Si is soluble in Al (≈ 0 5% at 450˚C)• Another practical issue is that Si is soluble in Al (≈ 0.5% at 450 C).

This can lead to "spiking" problems.

Aluminum • Si diffuses into Al, voids form, Al fills

OxideN+

Oxidevoids ⇒ shorts!

• 1st solution - add 1-2% Si in Al to satisfy solubility. Widely used, but Si can precipitate when cooling down

Siliconcan precipitate when cooling down and increase ρc.

Aluminum

Oxide

TiN• Better solution: use barrier layer(s).

Ti or TiSi2 for good contact and Oxide

Silicon

N+

Oxide

TiSi2

2 gadhesion, TiN for barrier. (See Table 11.3 in text for various barrier options.)



14


Barrier Layers

• Passive – inert to both Si and Al ( TiN)• Stuffed – Physical and chemical stop (Ti-W with N)• Sacrificial – chemical interacts forming secondary compounds

(Ti to TiS and TiAl)



• Refractory metal silicides – form barrier compounds at process temps15


Interconnects And Vias• Aluminum problems:

– relatively low melting point and soft– need a higher melting point material for gate electrode and local

i t t t l iliinterconnect to polysilicon. – hillocks and voids easily formed in Al.

• Hillocks and voids form

Compressive

Al hillock

Grain Compressive

• Hillocks and voids form because of stress and diffusion in Al films.

• Heating places Al under Compressive stress in Al

(due to thermalexpansiondifference

between film and

Al Al Grainboundary

Grain

Al film

SiO2 film

Compressive stress in Al

σ σ

Si substrate

compression causing hillocks.

• Cooling back down can place Al under tension resulting inbetween film and

substrate) Si substrate Al under tension resulting in

voids.• Adding a few % Cu stabilizes

grain boundaries and



16

minimizes hillock formation.


Interconnects And ViasA l t d bl ith Al

HillockVoid

Al

• A related problem with Al interconnects is “electromigration.” High current density (0.1-0.5 MegaA/cm2) causes movement of Al

Al film

Electron flowCathode Anode

SiO2 film

Alg )

atoms in direction of electron flow. • Can cause hillocks and voids, leading

to shorts or opens in the circuit. • Adding Cu (0 5 4 weight %) can also2 • Adding Cu (0.5-4 weight %) can also

inhibit electromigration.• Thus Al is commonly deposited with

1-2 wt % Si and 0.5-4 wt % Cu.

Al

OxidePoly Si

1TiSi2• Next development was use of other

materials with lower resistivity as local Oxide

Si

N+OxidePoly Si

2 3TiSi2 TiSi2

yinterconnects, like TiN and silicides.

• Silicides used to 1. strap polysilicon, 2 strap junctions



17

Si 2. strap junctions, 3. as a local interconnect.


Inherent TiN-Al Multilayer Interconnect

• Ti deposition was also recognized to reduce a problem with Al migration and voids.

• Construct the interconnect as a multilayer structures.Ti

Void in Al line

Oxidestructures.

• Shunting the Al helps mitigate electro-migration and can provide mechanical

t th b tt dh i d b i i lti

AlTi

I

strength, better adhesion and barriers in multi-level structures.

• TiN on top also acts as antireflection coating p gfor lithography.



18


Silicides

• Decrease sheet resistance, maintain integrity of interfaces, good contact characteristics, stable at high temperatures, easy to



19

, g p , yplasma etch, do not exhibit much electromigration


Silicide Deposition

OxideN+ OxidePoly SiN+ SiO2

A high temperature step is required so that the metal

reacts with Si

SiMSi2

Sidewall spacerOxideOxide

Form oxide spacer

Anneal

• Self-aligned silicideOxideOxide

p

Deposit metal

Remove anyunreacted metaland byproducts

• Self-aligned silicide (“salicide”) process.

• Also, recall TiN, TiSi2

OxideOxide

M OxideOxide

Deposit metalsimultaneous formation in CMOS process in Chapter 2.



20


Multilevel Metal

Intermetal • Early two-level metal structure

Al - Metal 1

OxideAl - Metal 2 (early 1980’s). Non-planar

topography leads to lithography, deposition, filling issues.

OxideN+

Oxideissues.

• These issues get worse with additional levels of i t t d i dSilicon interconnect and required change in structure.

• Therefore, there is a need to ,planarize.



21


Degree of Planarization

x ti

xstepf

xstepf

x tixstep

DOP = 0

x = 0f

DOP = 0.5

xstep

DOP = 1

xstepi

xstep= 0f

Degree of planarization is

DOP = 1−

xstepf

xstepi (3)



22


First Step, Tungsten Plugs

• Damascene method

Oxide

– Blanket W deposition (CVD), filling contacts and vias.

– Etchback to remove excess Silicon or Al

TiN

Etchback WW back to the original surface

– DOP approaches 1

W plug

Blanket W 1.5

2.0

2.5

0.0

0.5

1.0

mic

rons



23

-0.5-1.00 1.000.0

microns-2.00 2.00


Dual Damascene Process

Al or Cu

Metal 1

Silicon

1st Level Dielectric Deposit TiNand thick metal

• More advanced version of the damascene process provides both the via/contact andAl or Cu

Deposit thickIMD

Thin Si 3N4layer foretch stop

both the via/contact and interconnect levels simultaneously.

In this “d al damascene”

Etch via holesand interconnecttrenches

Etchback(plasma etch or

CMP) metaland TiN

Via

• In this “dual damascene” process, both the openings in the intermetal dielectric (IMD) for the metal interconnect and

Metal 2

Metal 1

for the contact or viasunderneath are opened, one after the other.

• Metal is then deposited into both layers at once followed by a CMP etchback.



24


More Current BackendTh bi t h th t h d i th t 5 i th id d• The biggest change that has occurred in the past 5 years is the widespread introduction of Cu, replacing aluminum.

• Cu cannot be easily etched since the byproducts, copper halides are not volatile at room temperature.p

• Electroplating (see text section 9.3.10) plus a damascene process (single or dual) is the obvious solution and is widely used today.

• Cu is the dominant material in logic chips today (µp, ASICs), but not in most memory chips

TiNOxide

memory chips.

TiN

TiN TiAl(Cu) - Metal 2

W • Typical modern interconnect structure incorporating allAl(Cu) - Metal 1

TiTiNN

W

structure incorporating all these new features.



25

Silicon TiSi2TiN

N+


Dielectrics

L l

GlobalInterconnects

Vias

Contacts IntermetalDielectricFirst Level

• Dielectrics electrically and physically separate interconnects from each

th d f tiLocalInterconnects

First LevelDielectric other and from active

regions. • Two types:

o First level dielectrico Intermetal dielectric (IMD)

• First level dielectric is usually SiO2 “doped” with P orFirst level dielectric is usually SiO2 doped with P or B or both (2-8 wt. %) to enhance reflow properties.

• PSG: phosphosilicate glass, reflows at 950-1100˚C• BPSG: borophosphosilicate glass, reflows at 800˚C.

BPSG• SEM shows BPSG oxide layer after 800˚C reflow step,

showing smooth topography over step.

• Undoped SiO2 often used above and below PSG or



26

Undoped SiO2 often used above and below PSG or BPSG to prevent corrosion of Al .


Material for Intermetal Dielectric (IMD) Layers



27


Intermetal Dielectric (IMD) Layers

• Intermetal dielectrics also made primarily of SiO2 today, but cannot do reflow or densification anneals on pure SiO2 because of T limitations.anneals on pure SiO2 because of T limitations.

• Two common problems occur, cusping and voids, which can be minimized using appropriate deposition techniq esappropriate deposition techniques.

2 0

2.5

2 0

2.5• SPEEDIE simulations of

0.5

1.0

1.5

2.0

m i c r o n s 0.5

1.0

1.5

2.0

m i c r o n s

silicon dioxide depositions over a step for silane deposition (Sc = 0.4) and TEOS deposition (S = 0 1)

-0.5

0.0

-1.00 1.000.0microns

-2.00 2.00-0.5

0.0

-1.00 1.000.0microns

-2.00 2.00

TEOS deposition (Sc = 0.1) showing less cusping in the latter case.



28


Planarization MethodsPhotoresist

Etchback tohereOxide

• One simple process involves planarizing with photoresist and then etching back with no selectivity.

SOG

ViaAl - Metal 2

Via SOG

CVD Oxide

• Spin-on-glass (SOG) is another option:o Fills like liquid photoresist, but becomes SiO2

after bake and cure. D ith ith t t hb k

Silicon

Al Metal 1 CVD

Oxide

o Done with or without etchback(with etchback to prevent poisoned via - no SOG contact with metal).

o Can also use low-K SOD’s. without etchback

CVDOxide

AlMetal 1

Al - Metal 2

SOGSOG

CVD Oxide

Via

(spin-on-dielectrics)o SOG oxides not as good quality as thermal or

CVD oxides o Use sandwich layers

without etchback

xide

Silicon

CVD Oxide

Al Metal 1

o Use sandwich layers.

• A final deposition option is HDPCVD which provides angle dependent sputtering during with etchback



29

deposition which helps to planarize. (see chapter 9)

with etchback


Chemical-Mechanical PolishingWafer carrier

WaferPolishing pad

Polishing table

Slurry(facing down)• The most common solution for

planarization today is CMP, which works very well

Close-up of wafer/pad interface:

Silicon

works very well.

• It is capable of forming very flat surfaces as shown in the example.

Polishing pad(semi-rigid)

Oxideslurry

Deposit thick oxide

Plasma etchback CMP



30Locally planarized topography remains Globally planarized topography remains


Backend Structure Schematic

PECVD SiO2

With PECVD oxide/PECVD nitride passivation bilayeron top of final metal level

PECVD SiO2

Metal 2

W PECVD SiO2

PECVD SiO2

PECVD SiO2

SOG or SOD

SOG or SOD Metal 1

Field OxideN+

W CVD SiO2BPSG

CVD SiO2

SOG or SOD

N+

Silicon

• One possible dielectric multi structure scheme• One possible dielectric multi-structure scheme.

• Other variations include HDP oxide or the use of CMP.



31


Backend Structure SEM

• Two backend structures.Two backend structures. o Left: three metal levels and encapsulated BPSG for the first level

dielectric; SOG (encapsulated top and bottom with PECVD oxide) and CMP in the intermetal dielectrics. The multilayer metal layers and W

l l l lplugs are also clearly seen. o Right: five metal levels, HDP oxide (with PECVD oxide on top) and CMP

in the intermetal dielectrics.



32


Measurement Methods

• Resistance and Resistivity– Metals and silicides

C R i

Hsρρ =

WHLR

⋅⋅

=ρ

⎟⎠⎞

⎜⎝⎛⋅=WLR sρ

• Contact Resistance– Cross-bridge Kelvin Probed Structure

ρ

– Multiple contacts in series

WLR c

c ⋅=

ρ

2211 RmRmRnR cTotal ⋅+⋅+⋅=



8


Electrical Measurements of Contactsl ρ

Low resistanceSiliconS

ctl

−

=ρ

ρ

Representative of a complex seriescomplex series

resistance computation

WlR c

c ⋅=

ρ

i

KELVIN BRIDGE

Wlt

gives overestimation( RC ) of thecontact properties



9


Models and Simulation

• Backend process simulation obviously relies heavily on the deposition and etching simulation tools discussed in Chapters 9 and 10.

• Thin Film Deposition and Etching are key to processing.SPEEDIE ATHENA d TAURUS i l i d ll d• SPEEDIE, ATHENA and TAURUS previously mentioned are all used

o Silicide Formation

o Chemical Mechanical Polishing

o Reflow

o Grain Growth

o Electromigrationg



10


Titanium Silicide FormationN

newlyformed TiSi2

Ti

TiSi2

Si + Ti → TiSi2Ti

TiSi2

Si + Ti → TiSi2

TiNN

N+ Ti → TiN

a) b)formed TiSi2

Si or N diffusion

through the

SiliconSi

SiliconSi

• Silicide formation is often modeling using the Deal-Grove linear-

material

S c de o at o s o te ode g us g t e ea G o e eaparabolic model.

• Titanium Silicide growth based on a selective “salicide” formation.• 1 nm of TI consumes 2.27 nm of Si producing 2.51 nm of TiSi2

/

2

τ+=+ tAB

xBx ss

⎭⎬⎫

⎩⎨⎧

−+

+= 14/

12 2 BA

tAxsτ



11


Alternate Silicide FormationsCoSi2Model

TiSi2Model

• Concern shorting of source-gate or gate-drain• One solution: simultaneously grow TiN during the anneal

– TiN is may also be used as a local interconnect if not removed– TiN is also a diffusion barrier for most dopants



12


From Dr. Saraswat



13


Titanium Silicide Modeling• Simulation of TiSi2 formation using FLOOPS [11.32] on a 0.35 μm wide

gate structure. Left: before formation anneal step. Right: after formation anneal step: 30 sec at 650˚C in a nitrogen atmosphere

-0.4

-0.2

Titanium

Polysilicon

Oxide spacer

TitaniumTitanium silicide

Titaniumnitride

Pinning point-0.4

-0.2

0

0.2

x in

mic

rons

Silicon

Polysilicon

Silicon dioxide in

mic

rons

SiliconTitaniumsilicide

Silicon dioxide

0

0.2

-0.8 -0.4 0.0 0.4 0.8 y in microns

0.4

x x

-0.8 -0.4 0.0 0.4 0.8 y in microns

0.4

Titanium Deposition After Anneal in Nitrogen

TiSi2 forms over silicon and polysilicon, not over SiO2.



14


Salicide: Table 11-5 p. 700



15


Chemical Mechanical PolishingCMP d l h l b i t d i i l t• CMP models have also been incorporated in process simulators.

• Models for CMP attempt to determine the relative pressure at each point and then calculate the relative removal rate at each point assuming that it is linearly proportional to the local pressure (see text). y p p p ( )

ATHENA simulation of

1

ons

a) b) c)chemical-mechanical polishing of SiO2 over Al lines:

a before polishing;0

0 20microns

mic

ro

0 20microns 0 20microns

a. before polishing; b. after 3 minutes of

polishing; c. after 6 minutes of

li hipolishing



16


Chemical Mechanical Polishing

0 5 0 5

0

0.5m

icro

ns SiO2 W

0

0.5SiO2 W

0 10microns 0 10microns

• ATHENA simulation of chemical-mechanical polishing of a tungsten via structure:

o Left: before polishing; o Right: after polishingo Right: after polishing.

• Due to the faster polishing of tungsten compared to silicon dioxide and the semi-rigid pad, “dishing” of the tungsten plug can result.



17


Reflow

• Reflow occurs to minimize the total energy of the system. In this case, the surface energy of the structure is reduced by minimizing the curvature.

S f diff i i fl h i ( l hi h T)• Surface diffusion is one reflow mechanism (metals at high T).

• Atoms will move to regions of lower chemical potential, µ, which is a function of the curvature.of the curvature.

• where is the per-area surface energy, is the atomic volume of the atom, K i th t d i th l th l th f

sK

sForce s ∂

∂γ∂∂μ

⋅Ω⋅−=−=

γs ΩK is the curvature, and s is the length along the surface.

• The curvature, K, is equal to the inverse of the radius of curvature, R, at that point: 1p

• The force acting upon an atom is in the direction away from a point of higher curvature to a point of lower curvature A smoothing of the topography

RK 1

=



18

curvature to a point of lower curvature. A smoothing of the topography results.


Reflow (2)R1 Force

1

2R2

• The surface flux of atoms, Fs then equals:

2

2

sK

kTDF s

ss ∂

∂υγ ⋅⋅Ω⋅⋅−=

where is the number of atoms per unit area, and Ds is the surface diffusivity of the atoms.

skT ∂υ

initial profile15 min., 800K30 min.60 min.

2.0

1.5

1.0

0.5

ht (m

icro

ns)

(a) initial profile3 min., 800K9 min.18 min.

2.0

1.5

1.0

0.5

ht (m

icro

ns)

(b) • Simulations of R. Brain, for reflow of Cu at 800K for different trench sizes:

0.0

-0.5

-1.03 4 5 6 7

Width (microns)

Hei

gh 0.0

-0.5

-1.03 4 5 6 7

Width (microns)

Hei

gh o a. 1 x 1 µm; o b. 0.5 x 1 µm; o c. 0.33 x 1 µm; and o d three 0 5 x 1 µm trenches

initial profile2 min., 800K4 min.8 min.

2.0

1.5

1.0

0.5

0 0ht (m

icro

ns)

(c) initial profile3 min., 800K12 min.18 min.24 min.

3.0

2.0

1.0

ht (m

icro

ns)

(d)o d. three 0.5 x 1 µm trenches

spaced 0.5 µm apart. • (parameters given in Table 11.8, p.

751, in text.)



19

0.0

-0.5

-1.03 4 5 6 7

Width (microns)

Hei

gh 0.0

-1.0

2 4 6 8Width (microns)

Hei

gh • Note filling of trenches and smoothing of topography.


Grain Growth

• All materials used for interconnections are polycrystalline. That is, they are made up of regions of single crystalmade up of regions of single crystal material where atoms are lined up perfectly that contact irregularly at crystal grain boundaries.

• Grain boundaries may have significantly different properties than the grains. (traps, density, etc.)

• With heating average grain size• With heating, average grain size grows.

• Grain growth is similar to reflow.• Grain growth occurs along existingGrain growth occurs along existing

boundaries, with growth occurring where another grain is losing material.



20


Grain Growth Simulations

“Normal” grain growth with time. Based k b F t d ll f d

Grain growth within a strip in time.on work by Frost and colleagues referenced in the text.

In steady state, average grain size

The limit to grain growth is related to the structure. For polycrystalline films growth proceeds until the average grain diameter is



21

y , g gdetermined by sqrt(t).

p g gapproximately 2 to 3 times the film thickness.


The Future of Backend Technologyτ 0 89RC 0 89 K K ε ρL2 1

+1⎛

⎜ ⎞ ⎟ R b τL = 0.89RC = 0.89 ⋅ KIKoxεoρL

Hxox+

WLS⎝ ⎜

⎠ ⎟ • Remember:


Technology N ode (half pi tch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nmTechnology N ode (half pi tch) 250 nm 180 nm 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm 18 nm


Min Meta l 1 Pitch (nm) 214 152 108 76 54 42

Wiring Levels - Logic 10 11 12 12 14 14Wiring Levels Logic 10 11 12 12 14 14


Contact As pec t Ratio (DRAM) 15 16 >20 >20 >20 >20

STI T h A t R ti 4 8 5 9 7 9 10 3 14 16 4STI Trenc h As pec t Ratio 4.8 5.9 7.9 10.3 14 16.4

Metal Res istivi ty (µohm-cm) 3.3, 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2


• Reduce metal resistivity - use Cu instead of Al.• Aspect ratio - advanced deposition, etching and planarization methods.

R d di l t i t t l K t i l



22

• Reduce dielectric constant - use low-K materials.


Summary of Key Ideas• Backend processing (interconnects and dielectrics) have taken on increased

importance in recent years.

• Interconnect delays now contribute a significant component to overall circuitInterconnect delays now contribute a significant component to overall circuit performance in many applications.

• Early backend structures utilized simple aluminum to silicon contacts.

R li bilit i th d f l l f i t t d l i ti• Reliability issues, the need for many levels of interconnect and planarization issues have led to much more complex structures today involving multilayer metals and dielectrics.

CMP i th t l i ti t h i t d• CMP is the most common planarization technique today.

• Copper and low-K dielectrics are now found in some advanced chips and their use will likely be common in the future.

• Beyond these materials changes, interconnect options in the future include architectural (design) approaches to minimizing wire lengths, optical interconnects, electrical repeaters and RF broadcasting. All of these areas will

i ifi t h i th t f



see significant research in the next few years.

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