Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical...
Transcript of Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical...
![Page 1: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/1.jpg)
Virtual MemoryKevin Webb
Swarthmore College
February 27, 2020
![Page 2: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/2.jpg)
Today’s Goals
• Describe the mechanisms behind address translation.
• Analyze the performance of address translation alternatives.
• Explore page replacement policies for disk swapping.
![Page 3: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/3.jpg)
Address Translation: Wish List
• Map virtual addresses to physical addresses.
• Allow multiple processes to be in memory at once, but isolate them from each other.
• Determine which subset of data to keep in memory / move to disk.
• Allow the same physical memory to be mapped in multiple process VASes.
• Make it easier to perform placement in a way that reduces fragmentation.
• Map addresses quickly with a little HW help.
Process 1
Process 3
OS
Process 2
Process 1
Text
Data
Stack
OS
Heap
libc code
Combination of hardware and OS, working together.
In hardware, MMU:Memory Management Unit
![Page 4: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/4.jpg)
Simple (Unrealistic) Translation Example
P3
P1
P2
P2
0
P2max
0
Phymax
Base +
• Process P2’s virtual addresses don’t align withphysical memory’s addresses.
• Determine offset from physical address 0to start of P2, store in base.
![Page 5: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/5.jpg)
Generalizing
P2
0
P2max
0
Phymax
Base? +
P2
P2
P2
…
…
Base? +
Base? +
?
• Problem: process may not fit in one contiguous region
![Page 6: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/6.jpg)
Generalizing
• Problem: process may not fit in one contiguous region
• Solution: keep a table (one for each process)• Keep details for each region in a row
• Store additional metadata (ex. permissions)
• Interesting questions:• How many regions should there be (and what size)?
• How to determine which row we should use?
P2
0
P2max
0
Phymax
P2
P2
P2
…
…?
Perm Base
R, X
R
R, W
![Page 7: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/7.jpg)
Defining Regions - Two Approaches
• Segmentation:• Partition address space and memory into segments
• Segments have varying sizes
• Paging:• Partition address space and memory into pages
• Pages are a constant, fixed size
![Page 8: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/8.jpg)
FragmentationInternal
• Process asks for memory, doesn’t use it all.
• Possible reasons:• Process was wrong about needs
• OS gave it more than it asked for
• internal: within an allocation
External
• Over time, we end up with these smallgaps that become more difficult to use (eventually, wasted).
• external: unused memory between allocations
OS
Used
Memory allocated to process
Unused
![Page 9: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/9.jpg)
Which scheme is better for reducing internal and external fragmentation. Why?A. Segmentation is better than paging for both forms of
fragmentation.
B. Segmentation is better for internal fragmentation, and paging is better for external fragmentation.
C. Paging is better for internal fragmentation, and segmentation is better for external fragmentation.
D. Paging is better than segmentation for both forms of fragmentation.
![Page 10: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/10.jpg)
Segmentation vs. Paging
• A segment is good logical unit of information• Can be sized to fit any contents
• Easy to share large regions (e.g., code, data)
• Protection requirements correspond to logical data segment
• A page is good physical unit of information• Simple physical memory placement
• No external fragmentation
• Constant sizes make it easier for hardware to help
![Page 11: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/11.jpg)
Generalizing
• Problem: process may not fit in one contiguous region
• Solution: keep a table (one for each process)• Keep details for each region in a row
• Store additional metadata (ex. permissions)
• Interesting questions:• How many regions should there be (and what size)?
• How to determine which row we should use?
P2
0
P2max
0
Phymax
P2
P2
P2
…
…?
Perm Base
R, X
R
R, W
![Page 12: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/12.jpg)
For both segmentation and paging…
• Each process gets a table to track memory address translations.
• When a process attempts to read/write to memory:• It attempts to access a virtual address from its virtual address space
![Page 13: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/13.jpg)
Address Translation
• Userspace process accesses memory by supplying an address:• movl (%eax), %ecx
• Send the bits held in register %eax to memory to retrieve contents.
Virtual Address
Address bits
![Page 14: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/14.jpg)
Address Translation
• Insight: we can use the address itself to make translation easier• Break the address into two (or more) regions
• Interpret one (or more) regions as an index into the table
Virtual Address
Upper bits Lower bits
![Page 15: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/15.jpg)
Address TranslationVirtual Address
Upper bits Lower bits
Physical Address
Phy LocMeta Perm …
Physical Memory
Table
![Page 16: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/16.jpg)
Performance ImplicationsVirtual Address
Upper bits Lower bits
Physical Address
Phy LocMeta Perm …
Physical Memory
Table
Without VM:
Go directly to address in memory.
With VM:
Do a lookup in memory to determine which address to use.
Concept: level of indirection
![Page 17: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/17.jpg)
Defining Regions - Two Approaches
• Segmentation:• Partition address space and memory into segments
• Segments have varying sizes
• Paging:• Partition address space and memory into pages
• Pages are a constant, fixed size
![Page 18: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/18.jpg)
Segment Table
• One table per process
• Where is the table located in memory?• Segment table base register (STBR)
• Segment table size register (STSR)
• Table entry elements• V: valid bit (does it contain a mapping?)
• Base: segment location in physical memory
• Bound: segment size in physical memory
• Permissions
BoundBaseV Perm …STBR
STSR
![Page 19: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/19.jpg)
Address Translation
• Physical address = base of s + i
• First, do a series of checks…
Virtual Address
Segment s
BoundBaseV Perm …
Offset i
Physical Address
![Page 20: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/20.jpg)
Check if Segment s is within RangeVirtual Address
Segment s
BoundBaseV Perm …
STBR
STSR
s < STSR
Offset i
Physical Address
![Page 21: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/21.jpg)
Check if Segment Entry s is ValidVirtual Address
Segment s
BoundBaseV Perm …
STBR
STSR
V == 1
Offset i
Physical Address
![Page 22: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/22.jpg)
Check if Offset i is within BoundsVirtual Address
Segment s
BoundBaseV Perm …
STBR
STSR
i < Bound
Offset i
Physical Address
![Page 23: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/23.jpg)
Check if Operation is PermittedVirtual Address
Segment s
BoundBaseV Perm …
STBR
STSR
Perm (op)
Offset i
Physical Address
![Page 24: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/24.jpg)
Translate AddressVirtual Address
Segment s
BoundBaseV Perm …
STBR
STSR
Offset i
+
Physical Address
![Page 25: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/25.jpg)
Sizing the Segment Table
Virtual Address
Segment s
BoundBaseV Perm …
Offset i
Number of bits nspecifies max sizeof table, wherenumber of entries = 2n
Number of bitsneeded to addressphysical memory
Number of bitsneeded to specifymax segment size
Number of bits nspecifies max sizeof segment
Helpful reminder:
210 => Kilobyte220 => Megabyte230 => Gigabyte
![Page 26: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/26.jpg)
Example of Sizing the Segment Table
• Given 32-bit virtual address space, 1 GB physical memory (max)• 5 bit segment number, 27 bit offset
Segment s: 5 bits
BoundBaseV Perm …
Offset i: 27 bits
…
![Page 27: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/27.jpg)
5 bit segment address, 32 bit logical address, 1 GB Physical memory.How many entries (rows) will we have in our segment table?
A. 32: The logical address size is 32 bits
B. 32: The segment address is five bits
C. 30: We need to address 1 GB of physical memory
D. 27: We need to address up to the maximum offset
![Page 28: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/28.jpg)
Example of Sizing the Segment Table
Segment s: 5 bits
BoundBaseV Perm …
Offset i: 27 bits
5 bits to address 25 = 32 entries
…
• Given 32-bit virtual address space, 1 GB physical memory (max)• 5 bit segment number, 27 bit offset
![Page 29: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/29.jpg)
How many bits do we need for the base?
A. 30 bits, to address 1 GB of physical memory.
B. 5 bits, because we have 32 rows in the segment table.
C. 27 bits, to address any potential offset value.
Segment s: 5 bits
BoundBaseV Perm …
Offset i: 27 bits
5 bits to address 25
= 32 entries
?…
![Page 30: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/30.jpg)
How many bits do we need for the base?
A. 30 bits, to address 1 GB of physical memory.
B. 5 bits, because we have 32 rows in the segment table.
C. 27 bits, to address any potential offset value.
Segment s: 5 bits
BoundBaseV Perm …
Offset i: 27 bits
5 bits to address 25
= 32 entries
?…
1 GB
![Page 31: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/31.jpg)
Example of Sizing the Segment Table
Segment s: 5 bits
BoundBaseV Perm …
Offset i: 27 bits
5 bits to address 25 = 32 entries
30 bits needed to address 1 GB …
• Given 32-bit virtual address space, 1 GB physical memory (max)• 5 bit segment number, 27 bit offset
![Page 32: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/32.jpg)
How many bits do we need for the bound?
A. 5 bits: the size of the segment portion of the virtual address.
B. 27 bits: the size of the offset portion of the virtual address.
C. 32 bits: the size of the virtual address.
Segment s: 5 bits
BoundBaseV Perm …
Offset i: 27 bits
5 bits to address 25
= 32 entries
30 bits needed to address 1 GB
?…
![Page 33: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/33.jpg)
How many bits do we need for the bound?
A. 5 bits: the size of the segment portion of the virtual address.
B. 27 bits: the size of the offset portion of the virtual address.
C. 32 bits: the size of the virtual address.
Segment s: 5 bits
BoundBaseV Perm …
Offset i: 27 bits
5 bits to address 25
= 32 entries
30 bits needed to address 1 GB
?…
128 MB(max)
![Page 34: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/34.jpg)
Example of Sizing the Segment Table
• Given 32 bit logical, 1 GB physical memory (max)• 5 bit segment number, 27 bit offset
Segment s: 5 bits
BoundBaseV Perm …
Offset i: 27 bits
5 bits to address 25 = 32 entries
30 bits needed to address 1 GB
27 bits needed tosize up to 128 MB…
?
![Page 35: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/35.jpg)
Example of Sizing the Segment Table
• Given 32 bit logical, 1 GB physical memory (max)• 5 bit segment number, 27 bit offset
Segment s: 5 bits
BoundBaseV Perm …
Offset i: 27 bits
5 bits to address 25 = 32 entries
30 bits needed to address 1 GB
27 bits needed tosize up to 128 MB…
8 bytes needed to contain61 (1+30+27+3+…) bits
Total table size?
![Page 36: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/36.jpg)
Example of Sizing the Segment Table
• Given 32 bit logical, 1 GB physical memory (max)• 5 bit segment number, 27 bit offset
Segment s: 5 bits
BoundBaseV Perm …
Offset i: 27 bits
5 bits to address 25 = 32 entries
30 bits needed to address 1 GB
27 bits needed tosize up to 128 MB…
8 bytes needed to contain61 (1+30+27+3+…) bits
Table size =32 x 8 = 256 bytes
![Page 37: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/37.jpg)
Pros and Cons of Segmentation
• Pro: Each segment can be• located independently• separately protected• grown/shrunk independently
• Pro: Small segment table size
• Con: Variable-size allocation• Difficult to find large enough gaps (or “best” gap) in physical memory• External fragmentation
![Page 38: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/38.jpg)
Defining Regions - Two Approaches
• Segmentation:• Partition address space and memory into segments
• Segments have varying sizes
• Paging:• Partition address space and memory into pages
• Pages are a constant, fixed size
![Page 39: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/39.jpg)
Paging Vocabulary
• For each process, the virtual address space is divided into fixed-size pages.
• For the system, the physical memory is divided into fixed-size frames.
• The size of a page is equal to that of a frame.• Often 4 KB in practice.
• Some CPUs allow for small and large pages at the same time.
![Page 40: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/40.jpg)
Page Table
• One table per process
• Table parameters in memory• Page table base register
• Page table size register
• Table entry elements• V: valid bit
• R: referenced bit
• D: dirty bit
• Frame: location in phy mem
• Perm: access permissions
FrameV Perm …PTBR
PTSR
R D
![Page 41: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/41.jpg)
Address Translation
• Physical address = frame of p + offset i
• First, do a series of checks…
Virtual Address
Page p Offset i
Physical Address
FrameV Perm …R D
![Page 42: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/42.jpg)
Check if Page p is Within RangeVirtual Address
Page p
PTBR
PTSR
p < PTSR
Offset i
Physical Address
FrameV Perm …R D
![Page 43: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/43.jpg)
Check if Page Table Entry p is ValidVirtual Address
Page p
PTBR
PTSR
V == 1
Offset i
Physical Address
FrameV Perm …R D
![Page 44: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/44.jpg)
Check if Operation is PermittedVirtual Address
Page p
PTBR
PTSR
Perm (op)
Offset i
Physical Address
FrameV Perm …R D
![Page 45: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/45.jpg)
Translate AddressVirtual Address
Page p
PTBR
PTSR
Offset i
Physical Address
FrameV Perm …R D
concat
![Page 46: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/46.jpg)
Physical Address by ConcatenationVirtual Address
Page p
PTBR
PTSR
Offset i
FrameV Perm …R D
Physical Address
Frame f Offset i
concat
Frames are all the same size. Only need to store the frame number in the table, not exact address!
![Page 47: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/47.jpg)
Sizing the Page TableVirtual Address
Page p Offset i
Number of bits nspecifies max sizeof table, wherenumber of entries = 2n
Number of bits needed to addressphysical memory in units of frames
Number of bitsspecifies page size
FrameV Perm …R D
![Page 48: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/48.jpg)
Example of Sizing the Page Table
• Given: 32 bit virtual addresses, 1 GB physical memory• Address partition: 20 bit page number, 12 bit offset
Page p: 20 bits Offset i: 12 bits
…
FrameV Perm …R D
![Page 49: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/49.jpg)
Example of Sizing the Page Table
• Given: 32 bit virtual addresses, 1 GB physical memory• Address partition: 20 bit page number, 12 bit offset
Page p: 20 bits Offset i: 12 bits
?
…
FrameV Perm …R D
![Page 50: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/50.jpg)
How many entries (rows) will there be in this page table?
A. 212, because that’s how many the offset field can address
B. 220, because that’s how many the page field can address
C. 230, because that’s how many we need to address 1 GB
D. 232, because that’s the size of the entire address space
• Given: 32 bit virtual addresses, 1 GB physical memory• Address partition: 20 bit page number, 12 bit offset
![Page 51: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/51.jpg)
Example of Sizing the Page Table
Page p: 20 bits Offset i: 12 bits
20 bits to address 220
= 1 M entries
…
FrameV Perm …R D
• Given: 32 bit virtual addresses, 1 GB physical memory– Address partition: 20 bit page number, 12 bit offset
![Page 52: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/52.jpg)
Example of Sizing the Page Table
Page p: 20 bits Offset i: 12 bits
20 bits to address 220
= 1 M entriesHow big is a frame?
…
FrameV Perm …R D
• Given: 32 bit virtual addresses, 1 GB physical memory– Address partition: 20 bit page number, 12 bit offset
![Page 53: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/53.jpg)
What will be the frame size, in bytes?
A. 212, because that’s how many bytes the offset field can address
B. 220, because that’s how many bytes the page field can address
C. 230, because that’s how many bytes we need to address 1 GB
D. 232, because that’s the size of the entire address space
• Given: 32 bit virtual addresses, 1 GB physical memory• Address partition: 20 bit page number, 12 bit offset
![Page 54: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/54.jpg)
Example of Sizing the Page Table
Page p: 20 bits Offset i: 12 bits
20 bits to address 220
= 1 M entriesPage size =frame size =212 = 4096 bytes
…
FrameV Perm …R D
• Given: 32 bit virtual addresses, 1 GB physical memory– Address partition: 20 bit page number, 12 bit offset
![Page 55: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/55.jpg)
How many bits do we need to store the frame number?
• Given: 32 bit virtual addresses, 1 GB physical memory• Address partition: 20 bit page number, 12 bit offset
• A: 12 B: 18 C: 20 D: 30 E: 32
Page p: 20 bits Offset i: 12 bits
20 bits to address 220
= 1 M entries
?
Page size =frame size =212 = 4096 bytes
…
FrameV Perm …R D
![Page 56: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/56.jpg)
Example of Sizing the Page Table
• Given: 32 bit virtual addresses, 1 GB physical memory• Address partition: 20 bit page number, 12 bit offset
Page p: 20 bits Offset i: 12 bits
20 bits to address 220
= 1 M entries
18 bits to address 230/212 frames
Page size =frame size =212 = 4096 bytes
…
Size of an entry?
FrameV Perm …R D
![Page 57: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/57.jpg)
Example of Sizing the Page Table
• Given: 32 bit virtual addresses, 1 GB physical memory• Address partition: 20 bit page number, 12 bit offset
Page p: 20 bits Offset i: 12 bits
20 bits to address 220
= 1 M entries
18 bits to address 230/212 frames
Page size =frame size =212 = 4096 bytes
…
4 bytes needed to contain24 (1+1+1+18+3+…) bits
FrameV Perm …R D
Total table size?
![Page 58: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/58.jpg)
Example of Sizing the Page Table
• 4 MB of bookkeeping for every process?• 200 processes -> 800 MB just to store page tables…
Page p: 20 bits Offset i: 12 bits
20 bits to address 220
= 1 M entries
18 bits to address 230/212 frames
Page size =frame size =212 = 4096 bytes
…
4 bytes needed to contain24 (1+1+1+18+3+…) bits
Table size =1 M x 4 = 4 MB
FrameV Perm …R D
![Page 59: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/59.jpg)
Pros and Cons of Paging
• Pro: Fixed-size pages and frames• No external fragmentation
• No difficult placement decisions
• Con: large table size
• Con: maybe internal fragmentation
![Page 60: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/60.jpg)
Which would you use? Why? Pros/Cons?
A. Segmentation:• Partition address space and memory into segments
• Segments have varying sizes
B. Paging:• Partition address space and memory into pages
• Pages are a constant, fixed size
C. Something else (what?)
![Page 61: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/61.jpg)
x86: Hybrid Approach
• Design:• Multiple lookups: first in segment table, which
points to a page table.
• Extra level of indirection.
• Reality:• All segments are max physical memory size
• Segments effectively unused, available for “legacy” reasons.
• (Mostly) disappeared in x86-64
VM PMPage
TablesSegment
Table
![Page 62: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/62.jpg)
Outstanding Problems
• Mostly considering paging from here on.
1. Page tables are way too big. Most processes don’t need that many pages, can’t justify a huge table.
2. Adding indirection hurts performance.
![Page 63: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/63.jpg)
Outstanding Problems
• Mostly considering paging from here on.
1. Page tables are way too big. Most processes don’t need that many pages, can’t justify a huge table.
2. Adding indirection hurts performance.
Solution:MORE indirection!
![Page 64: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/64.jpg)
Multi-Level Page Tables
Virtual Address
1st-level Page d Offset i
FrameV …R M
2nd-level Page p
FrameV …R MPoints to (base) frame containing 2nd-level page table
concat
Physical Address
How can using two (or more) page table levels like this reduce the table size?
![Page 65: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/65.jpg)
Multi-Level Page Tables
Virtual Address
1st-level Page d Offset i
FrameV …R M
2nd-level Page p
FrameV …R MPoints to (base) frame containing 2nd-level page table
concat
Physical Address
Text
Data
Stack
OS
Heap
![Page 66: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/66.jpg)
Multi-Level Page Tables
Virtual Address
1st-level Page d Offset i
FrameV …R M
2nd-level Page p
FrameV …R MPoints to (base) frame containing 2nd-level page table
concat
Physical Address
Insight: VAS is typically sparsely populated.
Idea: every process gets a page directory (1st-level table)
Only allocate 2nd-level tables when the process is using that VAS region!
![Page 67: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/67.jpg)
Multi-Level Page Tables
• With only a single level, the page table must be large enough for the largest processes.
• Multi-level table => extra level of indirection:• WORSE performance – more memory accesses• Much better memory efficiency – process’s page table is proportional to how
much of the VAS it’s using.
• Small process -> low page table storage
• Large process -> high page table storage, needed it anyway
![Page 68: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/68.jpg)
Outstanding Problems
• Mostly considering paging from here on.
1. Page tables are way too big. Most processes don’t need that many pages, can’t justify a huge table.
2. Adding indirection hurts performance.
![Page 69: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/69.jpg)
How might these table registers help with performance?
BoundBaseV Perm …STBR
STSR
FrameV Perm …PTBR
PTSR
R D
![Page 70: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/70.jpg)
Memory Management Unit
• When a process tries to use memory, send the address to MMU.
• MMU will do as much work as it can. If it knows the answer, great!
• If it doesn’t, trigger exception (OS gets control), consult software table.
Process 1
Process 3
OS
Process 2
Process 1
Text
Data
Stack
OS
Heap
libc code
Combination of hardware and OS, working together.
In hardware, MMU:Memory Management Unit
![Page 71: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/71.jpg)
Memory Management Unit (MMU)
• By knowing where the page table is for the running process:
1. The MMU can (sometimes) translate addresses on it's own, without help from the OS! (more on this next time)
2. The MMU can cache translation info for frequently used pages
![Page 72: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/72.jpg)
Translation Cost
• Each application memory access now requires multiple accesses!
• Suppose memory takes 100 ns to access.• one-level paging: 200 ns
• two-level paging: 300 ns
• Solution: Add hardware, take advantage of locality…• Most references are to a small number of pages
• Keep translations of these in high-speed memory
![Page 73: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/73.jpg)
Translation Look-aside Buffer (TLB)
• Fast memory mapping cache inside MMU keeps most recent translations• If key matches, get frame number quickly
• otherwise, wait for normal translation (in parallel)
“key”
Page p or or [page d, page p] or [segment s, page p] Offset i
Matchkey
frame
Frame f Offset i
![Page 74: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/74.jpg)
Recall: Context Switching Performance
• Even though it’s fast, context switching is expensive:1. time spent is 100% overhead
2. must invalidate other processes’ resources (caches, memory mappings)
3. kernel must execute – it must be accessible in memory
• Also recall: Advantage of threads• Threads all share one process VAS
0x0
0xFFFFFFFF
Operating system
Stack
TextData
Heap
![Page 75: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/75.jpg)
Translation Cost with TLB
• Cost is determined by• Speed of memory: ~ 100 nsec
• Speed of TLB: ~ 10 nsec
• Hit ratio: fraction of memory references satisfied by TLB, ~95%
• Speed to access memory with no address translation: 100 nsec
• Speed to access memory with address translation (2-level paging):• TLB miss: 300 nsec (200% slowdown)
• TLB hit: 110 nsec (10% slowdown)
• Average: 110 x 0.95 + 300 x 0.05 = 119.5 nsec
![Page 76: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/76.jpg)
TLB Design Issues
• The larger the TLB…• the higher the hit rate
• the slower the response
• the greater the expense
• the larger the space (in MMU, on chip)
• TLB has a major effect on performance!• Must be flushed on context switches
• Alternative: tagging entries with PIDs
![Page 77: Virtual Memory - cs.swarthmore.edukwebb/cs45/s20/07... · •Map virtual addresses to physical addresses. •Allow multiple processes to be in memory at once, but isolate them from](https://reader033.fdocuments.in/reader033/viewer/2022060510/5f2728f76179480baa18e3fc/html5/thumbnails/77.jpg)
Summary
• Many options for translation mechanism: segmentation, paging, hybrid, multi-level paging. All of them: level(s) of indirection.
• Simplicity of paging makes it most common today.
• Multi-level page tables improve memory efficiency – page table bookkeeping scales with process VAS usage.
• TLB in hardware MMU exploits locality to improve performance