Tema 2. Lenguajes de Descripción de Hardware...

Tema 2. Lenguajes de Descripcin de Hardware (VHDL)

http://www.unoweb-s.uji.es/IS36

Germn Len Navarro

Octubre, 2003

VHDL

Tema 2. Lenguajes de Descripcin de Hardware (VHDL) 2

VHDL: VHSIC Hardware Descripcin Language

VHSIC: Very High Speed Integrated Circuit

Desarrollado a mediados de los 80 por el Departamento de Defensa

USA. (subset de ADA).

Usado para modelado, simulacin y sistemas de sistemas digitales.

Slo un subconjunto del lenguaje es sintetizable.

Flujo de Diseo


Flujo de Diseo CPLD


Flujo de Diseo- Herramientas


Ejemplo: Sumador Completo


Ejemplo: Sumador Completo(VHDL)


ent i ty FULL_ADDER is

Port ( A ,B, CIN : in BIT ;

SUM,COUT: out BIT ) ;

end FULL_ADDER;

archi tecture FA_MIXED of FULL_ADDER is

component XOR2

port (P1 , P2 : in BIT ; PZ : out b i t ) ;

end component ;

signal S1 : BIT ;

begin

Ejemplo: Sumador Completo(VHDL)


X1 : XOR2 port map ( A,B, S1 ) ; e s t r u c t u r a lprocess ( A,B, CIN ) a l g o r i t m i c o

var iable T1 , T2 , T3 : BIT ;

begin

T1:=A and B; T2 : = B and CIN ;

T3 : = A and CIN ;

COUT

Tipos


Tipos Elementales.

Boolean,Character,Integer,Reat

bit

Definidos por el usuario

Array (bit_vector),subtipo (Natural)

Enumeracin.

Estndar lgico (std_logic,std_ulogic)

Constantes


constant CONST_NAME: < type_spec > := < value >;

Examples :constant CONST_NAME: BOOLEAN : = TRUE;

constant CONST_NAME: INTEGER : = 3 1 ;

constant CONST_NAME: BIT_VECTOR ( 3 downto 0 ) : = " 0000 " ;

constant CONST_NAME: STD_LOGIC : = Z ;

constant CONST:STD_LOGIC_VECTOR( 3 downto 0 ) : = "00" ;

Arrays


signal A_BUS,Z_BUS : b i t _ v e c t o r ( 3 downto 0 ) ;

signal B_BUS : b i t _ v e c t o r ( 0 to 3 ) ;

Z_BUS

Agregar y concatenar arrays


signal A_BUS,B_BUS,Z_BUS : b i t _ v e c t o r ( 3 downto 0 ) ;

signal A_BIT , B_BIT , C_BIT , D_BIT : b i t ;

signal BYTE: b i t _ v e c t o r ( 7 downto 0 ) ; AgregarZ_BUS 1 ,6= >B_BIT , others = > 0 ) ; ConcatenarZ_BUS

Particionar arrays


BYTE ( 5 downto 2 ) < = A_BUS;

Z_BUS ( 1 downto 0 ) < = 0 & B_BIT ;

B_BIT

Estndar lgico


type STD_ULOGIC is ( U , N o i n i c i a l i z a d o

X , O o 1 1 , 1 dominante 0 , O dominanteZ , A l ta impendanciaW , L , O d e b i lH , 1 d e b i l no importa ) ;

std_logic: Es correcto Res

Librera


Definicin : Una librera es un conjunto de elementos de VHDL.

Dentro de las librerias se incluyen package que es un conjunto de

funciones y tipos.

Se utilizan:l i l b a r y LIB_NAME ;

use LIB_NAME .PACKAGE_NAME. a l l ; Para trabajar con el tipo std_logic se utiliza el siguiente package

l i b r a r y IEEE ;

use IEEE . std_ log ic_1164 . a l l ;

Descripcin estructural


component COMPONENT_NAME port ( < po r t_dec la ra t i on > ) ;

end component ;

LABEL1 : COMPONENT_NAME port map

( PORT_NAME = > SIG_NAME,PORT_NAME = > SIG_NAME ) ;

for I in < l o w e r _ l i m i t > to < upper_ l im i t > generate

end generate ;

i f < cond i t i on > generate

end generate ;

Ejemplo sumador


G0 : for I in 0 to 3 generate

G1 : i f I = 0 generate

HA : HALF_ADDER port map (

A = > X( I ) , B = > Y( I ) ,

S = > Z( I ) , Co = > TMP( I + 1 ) ) ;

end generate ;

G2 : i f I >= 1 and I X( I ) , B = > Y( I ) , C = > TMP( I ) ,

S = > Z( I ) , Co = > TMP( I + 1 ) ) ;

end generate ; end generate ;

Genericidad


ent i ty ENTITY_NAME is

generic ( parametro : t i p o := va lo rporde fec to , . . . )

port ( < po r t_dec la ra t i ons > ) ;

end ENTITY_NAME;

component COMPONENT_NAME generic ( < gener i c_dec la ra t ion >)

port ( < po r t_dec la ra t i on > ) ;

end component ;

LABEL1 : COMPONENT_NAME generic map ( parametro = > va lor , . . . )

port map ( PORT_NAME = > SIG_NAME,PORT_NAME = > SIG_NAME ) ;

Descripcin Dataflow


SIG_NAME ;

LABEL1 : o p t i o n a l l a b e lSIG_NAME when < cond i t i on > else

when < cond i t i on > else

;

LABEL1 : o p t i o n a l l a b e lwith < choice_expression > select

SIG_NAME when < choices > ,

when < choices > ,

when others ;

Ejemplos: Triestado y Multiplexor


Driver Triestado.

Sa l ida Z ) ;

Multiplexor 4:1

with se l select

s1

Expresiones RTL


Expesiones normales: and ,or,xor,not



use IEEE . s t d _ l o g i c _ a r i t h . a l l ;

use IEEE . s td_ log ic_uns igned . a l l ;

Tipos: Signed,Unsigned Nuevos operaciones:+,-,=,>,

Tipos: Signed, Unsigned



use IEEE . STD_LOGIC_1164 .ALL ;

use IEEE . STD_LOGIC_ARITH .ALL ;

ent i ty vadd is

Port ( A ,B : in UNSIGNED( 7 downto 0 ) ;

C : in SIGNED( 7 downto 0 ) ;

D : in s td _ l o g i c _ v ec t o r ( 7 downto 0 ) ;

S : out UNSIGNED( 8 downto 0 ) ;

T : out SIGNED( 8 downto 0 ) ;

U : out SIGNED( 7 downto 0 ) ;

V : out s td _ l o g i c _ v e c t o r ( 8 downto 0 ) ) ;

end vadd ;

archi tecture Behav iora l of vadd is

begin

S< = ( 0 & A) + ( 0 & B ) ;

T

Descripcin algoritmica


Process: Especifica el comportamiento

siguiendo de un algoritmo secuencial.

Lista de sensibilidad: Cuando cambia uno

elemento de la lista se evualar el process.

Sern las entradas del circuito especificado.

[ label ] : process ( l i s t a de s e n s i b i l i d a d )

begin process [ l a b e l ]end process [ label ] ;

if y case


case < expression > is

when < choices > =>

when < choices > =>

when others = >

end case ;

i f < cond i t i on > then

e l s i f < cond i t i on > then

else

end i f ;

for


LABEL1 :

for I in < l o w e r _ l i m i t > to < upper_ l im i t > loop

end loop ;

Variables vs signals


Variables: Slo se pueden referencia dentro

del process. Las modificaciones son

inmediata.

Signal: Slo puede cambiar el valor al final

del process. Se puede referenciar en toda la

arquitectura.

Variables vs signals (cont)


signal A, B,C,Y, Z :UNSIGNED( 7 downto 0 ) ;

begin

process ( A, B,C)

var iable M,N:UNSIGNED( 7 downto 0 ) ;

begin

M:=A;

N:=B;

Z

Inferir memoria


process ( GATE, DIN )

begin

i f GATE= 1 then

DOUT

Ejemplo propuestos


Decodificador 1x2.

Decodificador 2x4 (estructural).

Codificador 4:2.

Codificador Gray 4:2 (estructural).

Codificador genrico.

Comparador genrico.

Decodificador




ent i ty dec1x2 is

port (

I : in STD_LOGIC ;E : in STD_LOGIC ;

s0 : out STD_LOGIC ; s1 : out STD_LOGIC ) ;

end dec1x2 ;

archi tecture dec1x2_arch of dec1x2 is

begin

s0

Decodificador


archi tecture dec1x2_beh of dec1x2 is

begin

s0 < = 0 when ( e = 0 ) else not ( I ) ;

s1 < = 0 when ( e = 0 ) else I ;

end dec1x2_beh ;

archi tecture dec1x2_beh2 of dec1x2 is

begin

pro : process ( i , e )

begin

s1

Decodificador


i f ( i = 0 ) then s0 < = 0 ;

else s1

Decodificador




ent i ty dec2x4 is

port (

A : in STD_LOGIC_VECTOR ( 1 downto 0 ) ;

S : out STD_LOGIC_VECTOR ( 3 downto 0 ) ; E : in STD_LOGIC

) ;

end dec2x4 ;

archi tecture dec2x4_arch of dec2x4 is

signal h a b i l i t a c i o n : s t d _ l og i c _v e c t o r ( 1 downto 0 ) ;

component dec1x2 port ( a , e : in s t d _ l o g i c ; s0 , s1 : out s t d _ l o g i c ) ;

Decodificador


end component ;

begin

DecEnt : dec1x2 port map

(A( 1 ) ,E, h a b i l i t a c i o n ( 0 ) , h a b i l i t a c i o n ( 1 ) ) ;

S a l i : for I in 0 to 1 generate

DecSal : dec1x2 port map

(A( 0 ) , h a b i l i t a c i o n ( I ) ,S(2 I ) ,S(2 I + 1 ) ) ;end generate ;

end dec2x4_arch ;

Codificador




ent i ty code4a2 is

port (

pe t i c i ones : in STD_LOGIC_VECTOR ( 3 downto 0 ) ;

codigo : out STD_LOGIC_VECTOR ( 1 downto 0 ) ;

enable : in STD_LOGIC ; alguno : out STD_LOGIC

) ;

end code4a2 ;

archi tecture code4a2_arch of code4a2 is

begin

x : process ( pe t i c iones , enable )

begin

Codificador


alguno < = 0 ;

codigo

Codificador Gray




ent i ty codegray is

port (



alguno : out STD_LOGIC

) ;

end codegray ;

archi tecture codegray_arch of codegray is

signal uno : s t d _ l o g i c ;

signal code_tmp : s td _ l og i c _ v e c t o r ( 1 downto 0 ) ;

component code4a2 port (

Codificador Gray




enable : in STD_LOGIC ;

alguno : out STD_LOGIC

) ; end component ;

begin

uno < = 1 ;

cd : code4a2 port map( pe t i c iones , code_tmp , uno , alguno ) ;

with code_tmp select

codigo

Codificador Genrico





use IEEE .STD_LOGIC_UNSIGNED.ALL ;

ent i ty coden is

generic (ANCHO: i n t e g e r : = 4 ) ;

Port (

s o l i c i t u d : in s td _ l o g i c _ v e c t o r ( (2ANCHO)1 downto 0 ) ;codigo : out s td _ l o g i c _ v e c t o r (ANCHO downto 0 ) ) ;

end coden ;

archi tecture Behav iora l of coden is

begin

ab : process ( s o l i c i t u d )

Codificador Genrico


begin

codigo 0 ) ;

for i in 0 to ( ( 2ANCHO)1) loopi f ( s o l i c i t u d ( i ) = 1 ) then

codigo

Latchs y Biestables


l a t c h : process ( GATE, DIN )

begin

i f GATE= 1 then

DOUT

Biestable


< label > : process ( < clock > , < reset >)

begin process < labe l >i f < reset > = 0 then asynchronous rese t

( a c t i v e low )

e l s i f < clock > event and < clock > = 1 then

i f < enable > = 1 then synchronous load

end i f ;

end i f ;

end process < label >;

Registro de desplazamiento




ent i ty regds l is

port (

Entrada : in STD_LOGIC ;

r e l o j : in STD_LOGIC ;

Sa l ida : out STD_LOGIC

) ;

end regds l ;

archi tecture regds l_arch of regds l is

signal estado , f u t u r o : s t d _ l o g i c _ v e c to r ( 1 5 downto 0 ) ;



begin

>s a l i d a

DECodificador BCD a 7 segmentos






ent i ty regdesf is

port (

c l k : in STD_LOGIC ;

D i r : in STD_LOGIC ;

ent : in STD_LOGIC ;

s a l i d a : out STD_LOGIC_VECTOR ( 1 2 downto 0 )

) ;

end regdesf ;



archi tecture regdesbid_arch of regdesf is

signal i n fo , in fo_tmp : s td _ l o g i c_ v e c t o r (12 downto 0 ) ;

begin

>ddcc : process ( d i r , ent )

begin

i f ( d i r = 1 ) then in fo_tmp



dd : process ( c l k )

begin

i f ( c lk event and c l k = 1 )

then

i n fo





ent i ty regdslpa is

port (

Entrada : in STD_LOGIC ;

r e l o j : in STD_LOGIC ;

pa ra l e l a : in s td _ l o g i c_ v ec t o r ( 1 5 downto 0 ) ;

load : in s t d _ l o g i c ;

Sa l ida : out STD_LOGIC ) ;

end regdslpa ;



archi tecture regds l_arch of regdslpa is

signal estado , f u t u r o : s t d _ l o g i c _ ve c to r ( 1 5 downto 0 ) ;

begin

>s a l i d a

Contador hasta 5




ent i ty c5 is

port (

c lk , rese t : in STD_LOGIC ;

Q: out STD_LOGIC_VECTOR ( 2 downto 0 )

) ;

end c5 ;

archi tecture c5_arch of c5 is

signal cuenta , masuno : s t d _ l o g i c _ ve c t o r ( 2 downto 0 ) ;

begin

q

Contador hasta 5


process ( cuenta )

begin

masuno masuno masuno masuno masuno masuno masuno NULL ;

end case ;

end process ;

Contador hasta 5


process ( c lk , rese t )

begin

i f ( rese t = 1 ) then cuenta 0 ) ;

e l s i f ( c lk event and c l k = 1 ) then

cuenta

Contador gnerico






ent i ty contador is

generic (ANCHO: n a t u r a l : = 8 ) ;

Port ( enable : in s t d _ l o g i c ;

c l k : in s t d _ l o g i c ;

rese tz : in s t d _ l o g i c ;

rese ts : in s t d _ l o g i c ;

q : out s td _ l o g i c _ v ec t o r (ANCHO1 downto 0 ) ) ;end contador ;

archi tecture Behav iora l of contador is

Contador gnerico


signal cuenta , masuno : s t d _ l o g i c _ v e c t o r (ANCHO1 downto 0 ) ;begin

masuno

Comparador






ent i ty comparador is

generic (ANCHO: i n t e g e r : = 8 ;EOS: i n t e g e r :=200;

SOB: i n t e g e r :=210;EOB: i n t e g e r :=220;EOL: i n t e g e r :=230

) ;

Port ( data : in s td _ l o g i c_ v ec t o r (ANCHO1 downto 0 ) ;c l k : in s t d _ l o g i c ;

rese tz : in s t d _ l o g i c ;

o : out s td _ l o g i c _ v e c t o r ( 1 to 3 ) ) ;

end comparador ;

Comparador


archi tecture Behav iora l of comparador is

signal f_o : s t d_ l og i c_ v ec t o r ( 1 to 3 ) ;

begin

f_o ( 1 ) < = 1 when ( data > EOS) else 0 ;

f_o ( 2 ) < = 1 when ( data > SOB) and ( data < EOB) else 0 ;

f_o ( 3 ) < = 1 when ( data=EOL ) else 0 ;

reg : process ( c lk , resetz , f_o )

begin

i f ( rese tz = 1 ) then o 0 ) ;

e l s i f ( c lk event and c l k = 1 ) then o

Mquina de estados


type STATE_TYPE is ( S1 , S2 , S3 , S4 ) ;

Borrar estas dos lneas para p e r m i t i r a l Expressdeterminar l a c o d i f i c a c i o na t t r i b u t e ENUM_ENCODING: STRING;

a t t r i b u t e ENUM_ENCODING of STATE_TYPE: type is " 0001 0010 0100 1000 " ;

signal CS, NS : STATE_TYPE;

Otra opcion elimando los comentar ios se r i a . s i g n a l CS, NS : STD_LOGIC_VECTOR ( 1 downto 0 ) ; constant S1 : s t d_ l og i c_ v ec t o r ( 1 downto 0 ) : = " 0 0 " I n s e r t a r l os s i g u i e n t e despues de l a palabra c lave begin

SYNC_PROC: process (CLOCK, RESET)

begin

i f ( RESET= 1 ) then

Mquina de estados


CS

i f ( < condic iones > ) then

end i f ;

Mquina de estados


r e p e t i r para todos los estados .end case ;

end process ;

Sumador serie




ent i ty SS is

port (

A : in STD_LOGIC ;

B : in STD_LOGIC ;

s : out STD_LOGIC ;

rese t : in s t d _ l o g i c ;

c l k : in STD_LOGIC

) ;

end SS;

archi tecture SS_arch of SS is

constant SINACARREO : STD_LOGIC : = 0 ;

Sumador serie


constant CONACARREO: STD_LOGIC : = 1 ;s i g n a l estado , sgte_estado : s t d _ l o g i c ;type t ipodeestado is ( SINACARREO,CONACARREO) ;

signal estado , sgte_estado : t ipodeestado ;

signal clock , clock_tmp , d_s , tmp_S : s t d _ l o g i c ;

component i b u f port ( I : in s t d _ l o g i c ; O: out s t d _ l o g i c ) ; end component ;

component bufg port ( I : in s t d _ l o g i c ; O: out s t d _ l o g i c ) ; end component ;

begin

u0 : i b u f port map ( c lk , clock_tmp ) ;

u1 : bufg port map ( clock_tmp , c lock ) ;

CC: process ( estado ,A,B)

begin

case estado is

Sumador serie


when SINACARREO=>

sgte_estado

Sumador serie


end i f ;

when others = > NULL ;

end case ;

end process cc ;

r e l o j : process ( c lock , rese t )

begin

i f ( rese t = 1 ) then

estado

RAM 1x1




ent i ty ram1x1 is

port (

Enable : in STD_LOGIC ; Read : in STD_LOGIC ;


Reset : in STD_LOGIC ; Dato : in STD_LOGIC ;

Sal : out STD_LOGIC

) ;

end ram1x1 ;

archi tecture ram1x1_arch of ram1x1 is

signal estado , sig_estado , s_temp :STD_LOGIC ;

begin

RAM 1x1


op : process ( Enable , Read , Dato )

begin

i f ( Enable = 0 ) then

s_temp

RAM 1x1


estado

RAM 1x1




ent i ty ram1x1 is

port (

Enable : in STD_LOGIC ;

Read : in STD_LOGIC ;


Reset : in STD_LOGIC ;

Dato : in STD_LOGIC ;

Sal : out STD_LOGIC

) ;

end ram1x1 ;

RAM 1x1



signal estado , sig_estado , s_temp :STD_LOGIC ;

begin

op : process ( Enable , Read , Dato , estado )

begin

sig_estado

RAM 1x1


s_temp




ent i ty ram16x2 is

port (

D i r : in STD_LOGIC_VECTOR( 3 downto 0 ) ;

Read : in STD_LOGIC ;


Reset : in STD_LOGIC ;

Dato : in STD_LOGIC_VECTOR( 0 to 1 ) ;

Sal : out STD_LOGIC_VECTOR( 0 to 1 )

) ;

end ram16x2 ;



component ram1x1 port ( Enable : in STD_LOGIC ;R: in STD_LOGIC ; c lock : in STD_LOGIC ;

Res : in STD_LOGIC ; Dat : in STD_LOGIC ;S : out STD_LOGIC ) ;

end component ;

component dec4x16 port (E : in STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; S : out STD_LOGIC_VECTOR ( 0 to 1 5 ) ) ;

end component ;

signal v e c t o r _ d i r :STD_LOGIC_VECTOR ( 0 to 1 5 ) ;

begin

u0 : dec4x16 port map( d i r , v e c t o r _ d i r ) ;

l abe l1 : for a in 0 to 1 5 generate

wa: ram1x1 port map ( v e c t o r _ d i r ( a ) , Read , c lk , Reset , Dato ( 0 ) , Sal ( 0 ) ) ;

va : ram1x1 port map ( v e c t o r _ d i r ( a ) , Read , c lk , Reset , Dato ( 1 ) , Sal ( 1 ) ) ;

end generate ;


end ram16x2_arch ;

The End

Copyright c 2003 Germn Len Navarro

Made with the ujislides document class c 2002-3 Sergio Barrachina ([email protected])

Tema 2. Lenguajes de Descripción de Hardware...

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