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E&C-ENGR 5535Verilog HDL
Lecture 02Chapter 02
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8/30/15 Chaudhry-Lecture 02, Ch. 02 2
Course Overview
! Introduction
! Language Elements! Language Expressions!
Gate-Level Modeling! User-Defined Primitives! Dataflow Modeling! Behavioral Modeling!
Structural modeling! Task and Functions
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8/30/15 Chaudhry-Lecture 02, Ch. 02 3
Chapter Overview
! Design Methodologies
! Verilog Modules and Ports
! Styles of Verilog Modeling
! Dataflow Modeling
! Behavioral Modeling
!
Structural Modeling
! Mixed-Design Modeling
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8/30/15 Chaudhry-Lecture 02, Ch. 02 4
Design Abstractions in VLSI Circuits
STRUCTURAL
CPUs
RAM, ROM, UART
PARALLEL PORT
REGISTERS, ALUs COUNTERS, MUXES
GATES, FLIP-FLOPS
TRANSISTORS, RLC
LEVEL
CHIP
REGISTER
GATE
CIRCUIT
SILICON GEOMETRICAL OBJECTS
BEHAVIORAL
PERFORMANCE I/O RESPONSE
ALGORITHMS
OPERATIONS
TRUTH TABLES STATE TABLES OPERATIONS
BOOLEAN EQUATIONS
DIFFERENTIAL EQUATIONS
--- I N C R E A
S I N G A
B S T R A C T I O
N
I N C R E A S I N G
D E T A I L
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8/30/15 Chaudhry-Lecture 02, Ch. 02 5
Verilog Built-In Primitives
!
Verilog has 26 built-in Primitives
!
Propagation delay can be assigned on instance base
andnand
ornorxorxnorbufnot
bufif0bufif1
notif0notif1
nmospmos
rnmosrpmos
Combinational Logic
Three State
MOS Gates
CMOS Gates
cmosrcmos
Bi-Directional Gates
trantranif0
tranif1rtranrtranif0rtranif1
Pull Gates
pulluppulldown
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8/30/15 Chaudhry-Lecture 02, Ch. 02 6
Schematic Design
sum = a ! b
c_out = a • b
•
Schematics display the structure of a design.
• Main focus on structural details of the design.
• Efficient at small design level.
Sum
C_out
a
b
Add_half
ab sum
C_out
C_out_bar
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8/30/15 Chaudhry-Lecture 02, Ch. 02 7
Verilog HDL: Design of a Flip-Flop
data_in q
rst
clk
module flip_flop ( q, data_in, clk, rst );input data_in, clk, rst;output q;reg q;
always @ ( posedge clk )begin
if ( rst == 1) q = 0;
else q = data_in;end
endmodule
Declaration of synchronous behavior
Procedural statement
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8/30/15 Chaudhry-Lecture 02, Ch. 02 8
Design Methodologies
! Two main types of designmethodologies:
! Top-Down Design
!
Bottom-Up Design
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Design Methodologies: Top-Down
! The top level block is identified, then the blocks in
the next lower level until all levels in the structurehave been defined.
8/30/15 Chaudhry-Lecture 02, Ch. 02 9
Top-Level Block
2nd Level Block
Bottom-LevelBlock: Leaf
Bottom-LevelBlock: Leaf
Bottom-LevelBlock: Leaf
Bottom-LevelBlock: Leaf
Bottom-LevelBlock: Leaf
Bottom-LevelBlock: Leaf
2nd Level Block 2nd Level Block
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Design Methodologies: Bottom-Up
! The lowest level contains the leaf cells, is definedfirst and considered as building blocks to designnext higher level.
8/30/15 Chaudhry-Lecture 02, Ch. 02 10
Top-Level Block
2nd Level Block
Bottom-LevelBlock: Leaf
Bottom-LevelBlock: Leaf
Bottom-LevelBlock: Leaf
Bottom-LevelBlock: Leaf
Bottom-LevelBlock: Leaf
Bottom-LevelBlock: Leaf
2nd Level Block 2nd Level Block
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8/30/15 Chaudhry-Lecture 02, Ch. 02 11
Example 01: Modulo-16Synchronous Counter (Top-Down)
! Modulo-16 synchronous counter using D flip-flops
! An Illustration of top-down design approach
! The counting sequence is:
y3y2y1y0 = 0000, 0001, 0010, 0011, 0100, 0101, 0110,
0111, 1000, 1001, 1010, 1011, 1100, 1101,1110, 1111, 0000, ….
where yi is the name of the flip-flop.
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8/30/15 Chaudhry-Lecture 02, Ch. 02 12
Example 01: Modulo-16Synchronous Counter: Schematic
!
It contain four D flip-flops, y3y2y1y0
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Example 01:Modulo-16 SynchronousCounter: Excitation Tables
! After developing thetruth table out ofcounter sequence,0000, 0001, 0010,.. ,
! We draw theexcitation tables foreach flip-flop to getthe function controlling
equation, usuallycalled as logicequations for each Dflip-flop.
8/30/15 Chaudhry-Lecture 02, Ch. 02 13
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8/30/15 Chaudhry-Lecture 02, Ch. 02 14
Example 01 : Modulo-16 SynchronousCounter: Logical Equations
!
Logical Equations:
Dy3 = y3y2’ + y3y1’ + y3y0’
+ y3’y2y1y0
Dy2 = y2y1’ + y2y0’ + y2’y1y0
Dy1 = y1’y0 + y1y0’
Dy0 = y0’
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Example 02: 4-Bit Ripple Adder:Top-Down !
An other top-down design example, in which carryripples from one adder to the next adder.
!
Sum = a’b’cin + a’bcin’
+ ab’cin’ + abcin
= a ! b ! cin
!
Cout = ab + (a!
b)cin
8/30/15 Chaudhry-Lecture 02, Ch. 02 15
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8/30/15 Chaudhry-Lecture 02, Ch. 02 16
What Verilog Modules Show?
!
Description of internalstructure/function!
Implicit semantic of timeassociated with each dataobject/signal
! Implementation is hidden tooutside world
!
Communicate withoutside through ports! Output ports at the left
!
Port list is optional!
Achieve hardwareencapsulation
module Add_half (sum, c_out, a, b);
input a, b;
output sum, c_out;
wire c_out_bar;
xor (sum, a, b);nand (c_out_bar, a, b);
not (c_out, c_out_bar);
endmodule
c_out
a
b sum
c_out_bar
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8/30/15 Chaudhry-Lecture 02, Ch. 02 17
Modules and Ports
! General Structure of a Verilog modulemodule <module name> (port list);
reg, wire, parameter //declarations
input ...;
output …;
<module internals> // other statements
initial, always,
module instantiations,..…………….
endmodule
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8/30/15 Chaudhry-Lecture 02, Ch. 02 18
Module Instantiation
! Accomplished by entering:! Module name as a module item within a parent
module
! Signal identifiers at appropriate ports
! Module instantiation needs a module identifier
! A module is never declared within anothermodule
! The order of ports in instantiation usuallymatches the order in module declaration
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8/30/15 Chaudhry-Lecture 02, Ch. 02 19
Modeling with Primitives
! Helps to model pre-defined hardware-based behavior;!
Built-in Primitives or Pre-Defined Primitives
! All Pre-Defined Primitives are Combinational
! The output of Combinational Primitives mustbe of type “net”
! The input of any Primitive can be of type“net” or “register ”
! Verilog supports Combinational andSequential User-Defined Primitive (UDP)
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8/30/15 Chaudhry-Lecture 02, Ch. 02 20
Characteristics of Verilog Primitives
! Basic element to build a module, such asnand, nor , buf and not gates
! Never used stand-alone in design, mustbe within a module
!
They may be Pre-defined or User-defined
!
Identifier (instance name) is optional
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8/30/15 Chaudhry-Lecture 02, Ch. 02 21
Smart Primitives
module nand3 (O, A1, A2, A3);
input A1, A2, A3;
output O;
nand (O, A1, A2, A3);
endmodule
Smart Primitives: Same primitive can be used todescribe for any number of inputs
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8/30/15 Chaudhry-Lecture 02, Ch. 02 22
Types of Delays and Times
! Delays can be defined in variety of ways:! Symmetrical Delays
!
All the delays are uniform
!
Default Delay = 0
! Asymmetrical Delays
!
Min Delay
! Typical Delay
!
Max Delay
! Times! Rising Time (T01)
!
Falling Time (T10)
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8/30/15 Chaudhry-Lecture 02, Ch. 02 23
Symmetric Delay Assignment
module AOI_4 (y, x1, x2, x3, x4);
input x1, x2, x3, x4;
output y;
wire y1, y2;
and #1 (y1, x1, x2);
and #1 (y2, x3, x4);
nor #1 (y, y1, y2);endmodule
x1
x2
x3
x4
y1
y2
y
AOI => And OR Invert
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8/30/15 Chaudhry-Lecture 02, Ch. 02 24
Asymmetric Delay Assignment
module nand1 (O, A, B);
input A, B;
output O;
nand (O, A, B);
specifyspecparam
T01 = 1.13:3.09:7.75;
T10 = 0.93:2.50:7.34;
(A=>O) = (T01, T10);
(B=>O) = (T01, T10);
endspecify
endmoduleFalling time
Rising time
Min delay
Typical delay
Max delay
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8/30/15 Chaudhry-Lecture 02, Ch. 02 25
Construct Definitions
! Continuous Assignment:
To describe combinational logic where the output of the circuit isevaluated whenever an input changes:
assign [delay] lhs_net = rhs_expression; (lhs = left hand side)!
Procedural Continuous Assignment:
Made within a behavioral construct (initial or always) and
creates a dynamic binding to a variable.! Blocking Statement (=):
The assignment to LHS variable takes place before the followingstatement in the sequential block.
!
Nonblocking Statement (=>):
Allows scheduling of assignments without blocking execution of thestatements that follow in a sequential block.
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Example: Verilog module for2-input AND Gate
! Dataflow and 2 input and gate
module and2 (x1, x2, z1);
input x1, x2;
output z1;
wire x1, x2;
wire z1;
assign z1 = x1 & x2;
endmodule
8/30/15 Chaudhry-Lecture 02, Ch. 02 26
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8/30/15 Chaudhry-Lecture 02, Ch. 02 27
Example: TBfor 2-inputand Gate(Cont…)
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8/30/15 Chaudhry-Lecture 02, Ch. 02 28
Example: Output and Waveforms for2-Input AND Gate (Cont…)
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8/30/15 Chaudhry-Lecture 02, Ch. 02 29
Styles of Verilog Modeling
!
Dataflow Modeling: ! Used to design combinational logic only.
!
It implements logical function at a high level ofabstraction using built-in primitives
! Example: assign z1 = x1 & x2;
! Behavioral Modeling:
!
Build a behavioral module by:
1. Writing continuous assignment statements, or
2. Declaring Verilog behaviors
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8/30/15 Chaudhry-Lecture 02, Ch. 02 30
Styles for Modeling (Cont…)
! Structural Modeling:!
Build a structural model by instantiating primitivesand/or other modules within a module declaration,and interconnect with nets.
! Mixed-Design Modeling: !
Incorporates different modeling styles in the samemodule.
!
This includes gate and module instantiations aswell as continuous assignments and behavioralconstructs.
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8/30/15 Chaudhry-Lecture 02, Ch. 02 31
Examples: Dataflow Modeling1.
Two-input Exclusive-OR gate
2. Four 2-Input AND Gates with scalar input and avector output
!
Example 1:
+X1
+X2
+Z1
module xor2 (x1, x2, z1);input x1, x2;output z1;wire x1, x2;wire z
1;
assign z1 = x1 ^ x2; endmodule
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8/30/15 Chaudhry-Lecture 02, Ch. 02 32
Example 1: TB for 2-input XOR Gate(Cont…)
Prints the argument
values withinquotation marks
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8/30/15 Chaudhry-Lecture 02, Ch. 02 33
Example 1: Outputs and Waveformsfor 2-Input XOR Gate (Cont…)
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Time Units
! Timescale: The actual unit of time is specifiedby the ‘timescale’ compiler directive.
! For example, the statement
timescale 10ns /100psindicates that one time unit is specified as 10ns with a precision of 100ps.
!
This property is called inertial delay.
8/30/15 Chaudhry-Lecture 02, Ch. 02 34
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Example 2: Four 2-Input AND Gates withScalar Input and a Vector Output
! //dataflow modeling
timescale 10ns/1nsmodule four_and_delay (z1, x1, x2);
input x1, x2; output z1;
wire x1, x2; wire [3:0] z1;
assign #2 z1[0] = ~x1 & ~x2 ;assign #2 z1[1] = ~x1 & x2 ;
assign #2 z1[2] = x1 & ~x2 ;assign #2 z1[3] = x1 & x2 ;
endmodule
8/30/15 Chaudhry-Lecture 02, Ch. 02 35
-X1
-X2
+Z1[0]
-X1
+X2
+Z1[1]
+X1
-X2
+Z1[2]
+X1
+X2
+Z1[3]
When input x1 or x2
changes value, the valueof right-hand statement isassigned to the left-handafter a delay of 20ns.
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Example 2: TB for Four 2-Input AND Gates (Cont…)
module four_and_delay (z1,x1,x2);wire x1, x2; wire [3:0] z1;
initial
$monitor (“x1, x2 = %b, z1 =%b”, {x
1, x
2}, z
1);
initial begin
#0 x1 = 1’b 0;
x2 = 1’b 0;
#5 x1 = 1’b1;
x2 = 1’b 0;
#5 x1 = 1’b1;
x2 = 1’b1;
#5 x1 = 1’b 0;x2 = 1’b 1;
#5 x1 = 1’b 0;
x2 = 1’b 1;
#5 x1 = 1’b 0;x2 = 1’b 0;
#5 $stop;
end
four_and_delay Inst1 (
. x1 (x1), . x2 (x2), . z1 (z1), );
endmodule
8/30/15 Chaudhry-Lecture 02, Ch. 02 36
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8/30/15 Chaudhry-Lecture 02, Ch. 02 37
Example 2: Waveforms for Four 2-Input AND Gates (Cont…)
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Summary! What we discussed today;
!
Types of Verilog modeling
! Types of design approaches
!
Top-down
!
Bottom-up
! Modules and Ports
! Types of Delays & Times
! Time Units
! Data Flow Modeling
8/30/15 Chaudhry-Lecture 02, Ch. 02 38
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Questions?
8/30/15 Chaudhry-Lecture 02, Ch. 02 39