2-System Specifications Using Verilog HDL

7/30/2019 2-System Specifications Using Verilog HDL

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SYSTEMSPECIFICATIONS USINGVERILOG HDL

Dr. Mohammed Morsy


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Faculty of Engineering - Alexandria University 2013aculty of Engineering - Alexandria University 2013

IntroductionBasic ConceptsModules and PortsGate-Level ModelingDataflow ModelingBehavioral ModelingTasks and Functions

Textbook: Verilog HDL: A Guide to Digital Designand Synthesis, Second Edition By Samir Palnitkar

Outline

EE 432 VLSI Modeling and Design 2


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Better be standard than be proprietaryCan describe a design at some levels of abstractionCan be interpreted at many level of abstraction

Cross functional, statistical behavioral, multi-cyclesbehavioral, RTL

Can be used to document the complete system

design tasksTesting, simulation, ..., related activitiesUser define types, functions and packages

Comprehensive and easy to learn

Hardware Description Language



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Top-Down DesignStart with system specificationDecompose into subsystems, components, untilindivisibleRealize the components

Bottom-up DesignStart with available building blocksInterconnect building blocks into subsystems, then

system Achieve a system with desired specificationMeet in the middle

A combination of both

Design Methodologies



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Designs can be described at very abstractlevels without predefining the fabricationtechnologyFunctional verification of the design can bedone early in the design cycleDesigners can optimize and modify the RTLdescription until it meets the desiredfunctionality

Designing with HDLs is analogous to computer programmingWith rapidly increasing complexities of digitalcircuits and increasingly sophisticated EDAtools, HDLs are now the dominant method for

Importance of HDLs



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Gateway Design AutomationPhil Moorbr in 1984 and 1985

Verilog- XL, XL algorithm, 1986 Gate-level simulation

Verilog logic synthesizer, Synopsis, 1988Top-down design methodology

Cadence Design Systems acquired Gateway

December 1989a proprietary HDL

Verilog History



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Open Verilog International (OVI), 1991Language Reference Manual (LRM)

The IEEE 1364 working group, 1994Verilog become an IEEE standard (1364-1995)

December, 19952001, IEEE standard 1364-2001

Verilog History



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Verilog HDL is a general-purpose hardwaredescription language that is easy to learn and easyto use

It is similar in syntax to the C programming language

Verilog HDL allows different levels of abstraction tobe mixed in the same modelMost popular logic synthesis tools support VerilogHDL

All fabrication vendors provide Verilog HDL libraries for post logic synthesis simulation

The Programming Language Interface (PLI) is apowerful feature that allows the user to writecustom C code to interact with the internal data

Popularity of Verilog HDL



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The speed and complexity of digital circuitshave increased rapidlyDesigners have responded by designing athigher levels of abstraction

Designers have to think only in terms of functionality.EDA tools take care of the implementation

details and optimizationThe most popular trend currently is to design inHDL at an RTL level, because logic synthesistools can create gate-level netlists from RTLlevel design

Trends in HDLs



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Behavioral synthesis allowed engineers todesign directly in terms of algorithms and thebehavior of the circuitHowever, behavioral synthesis did not gain

widespread acceptanceToday, RTL design continues to be very popular Designers often mix gate-level description

directly into the RTL description to achieveoptimum results Another technique that is used for system-leveldesign is a mixed bottom-up methodology

Trends in HDLs (2)



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Faculty of Engineering - Alexandria University 2013

Hierarchical Modeling Concepts



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Top-down design methodology

Bottom-up design methodology

Design Methodologies



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Typically, a combination of top-down andbottom-up flows is usedDesign architects define the specifications of thetop-level block

Logic designers decide how the design shouldbe structured by breaking up the functionalityinto blocks and sub-blocks

At the same time, circuit designers aredesigning optimized circuits for leaf-level cellsThe flow meets at an intermediate point

Design Methodologies (2)



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Example: 4-bit Ripple Carry Counter


Design Hierarchy


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A module is the basic building block in Verilog A module can be an element or a collection of lower-level design blocksTypically, elements are grouped into modules toprovide common functionality that is used atmany places in the design

A module provides the necessary functionality to

the higher-level block through its port interface,but hides the internal implementationThis allows the designer to modify moduleinternals without affecting the rest of the design

Modules



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In Verilog, a module is declared by the keywordmoduleIn Verilog, a module is declared by the keywordmodule

Each module must have a module_name, whichis the identifier for the module, and amodule_terminal_list, which describes the inputand output terminals of the module

Module Declaration


module ();......endmodule

l f l d 2013l f l d 2013


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The T-flip flop could be defined as a module asfollows

Example


module T_FF (q, clock, reset);.

.

.

.endmodule


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F l f E i i Al d i U i i 2013l f E i i Al d i U i i 2013


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Dataflow levelThe module is designed by specifying the data flowThe designer is aware of how data flows betweenhardware registers and how the data is processed in thedesign

Gate levelThe module is implemented in terms of logic gates andinterconnections between these gatesDesign at this level is similar to describing a logic design

Switch levelThis is the lowest level of abstraction provided byVerilog

A module can be implemented in terms of switches,storage nodes, and the interconnections between them

Verilog Abstraction Levels (2)


F lt f E gi i g Al d i U i it 2013lt f E gi i g Al d i U i it 2013


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Verilog allows the designer to mix and match allfour levels of abstractions in a designThe term register transfer level (RTL)isfrequently used for a Verilog description that

uses a combination of behavioral and dataflowconstructsNormally, the higher the level of abstraction, themore flexible and technology-independent thedesignHowever, at this level, the designer does nothave the control over low-level details which are

automatically generated by the synthesis tool

Verilog Abstraction Levels (3)


Faculty of Engineering Alexandria University 2013aculty of Engineering Alexandria University 2013


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module module_name ( port_list );Declarations:

Net declarations.Reg declarations.Parameter declarations.

Initial statements.Gate instantiation statements.Module instantiation statements.UDP instantiation statements.

Always statements.Continuous assignment.

endmodule

Mixing Structure and Behavior

EE432 VLSI Modeling and Design 22



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A module provides a template from which youcan create actual objectsVerilog creates a unique object from thetemplate when a module is invoked

The process of creating objects from a moduletemplate is called instantiation, and the objectsare called instancesIn Verilog, it is illegal to nest modules

One module definition cannot contain another module definition within the module and endmodulestatementsInstead, a module definition can incorporate copies

of other modules by instantiating them

Instances




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// Define the top-level module called ripple carry

// counter. It instantiates 4 T-flipflops. Interconnections are// shown in Section 2.2, 4-bit Ripple Carry Counter.

module ripple_carry_counter(q, clk, reset);output [3:0] q; //I/O signals and vector declarations

//will be explained later.input clk, reset; //I/O signals will be explained later.

//Four instances of the module T_FF are created. Each has a unique//name.Each instance is passed a set of signals. Notice, that//each instance is a copy of the module T_FF.

T_FF tff0(q[0],clk, reset);T_FF tff1(q[1],q[0], reset);T_FF tff2(q[2],q[1], reset);T_FF tff3(q[3],q[2], reset);

endmodule

Example-1




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// Define the module T_FF. It instantiates a D-flipflop. We assumed

// that module D-flipflop is defined elsewhere in the design. Refer // to Figure 2-4 for interconnections.module T_FF(q, clk, reset);

//Declarations to be explained later output q;input clk, reset;wire d;D_FF dff0(q, d, clk, reset); // Instantiate D_FF. Call it dff0.not n1(d, q); // not gate is a Verilog primitive. Explained

later.endmodule

Example-2




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The functionality of the design block can betested by applying stimulus and checking results

We call such a block the stimulus block or a test bench

Two styles of stimulus application are possible

Components of Simulation


First style Second style



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Faculty of Engineering Alexandria University 2013

ExampleRipple Carry Counter Top Block

Flipflop T_FF

27EE 432 VLSI Modeling and Design

module ripple_carry_counter(q, clk,reset);

output [3:0] q;

input clk, reset;//4 instances of the moduleT_FF are created.

T_FF tff0(q[0],clk, reset);T_FF tff1(q[1],q[0], reset);

T_FF tff2(q[2],q[1], reset);T_FF tff3(q[3],q[2], reset);endmodule

module T_FF(q, clk, reset);output q;input clk, reset;wire d;D_FF dff0(q, d, clk,

reset);not n1(d, q); /* not is a

Verilog-provided primitive.case sensitive*/endmodule



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Faculty of Engineering Alexandria Universityaculty of Engineering Alexandria University

// module D_FF with synchronous reset

module D_FF(q, d, clk, reset);output q;input d, clk, reset;reg q;

// Lots of new constructs. Ignore the functionality of the// constructs.// Concentrate on how the design block is built in a top-downfashion.

always @(posedge reset or negedge clk)if (reset)

q


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Faculty of Engineering Alexandria University

Example: Stimulus Blockmodule stimulus;

reg clk;reg reset;wire[3:0] q;// instantiate the design block

ripple_carry_counter r1(q, clk,reset);// Control the clk signal that drivesthe //design block. Cycle time = 10initialclk = 1'b0; //set clk to 0always#5 clk = ~clk; //toggle clk every 5time units

/* Control the reset signal that drivesthe design block */initial

beginreset = 1'b1;#15 reset = 1'b0;

#180 reset = 1'b1;#10 reset = 1'b0;#20 $finish; //terminate the

//simulationend// Monitor the outputsinitial

$monitor($time, " Output q = %d", q);endmodule




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y g g y

Basic Concepts




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Free format

Case sensitivewhite space (blank, tab, newline) can be used freelyIdentifiers: sequence of letters, $ and _(underscore).First has to be a letter or an _

Symbol

symbolR12_3$ _R2

Escaped identifiers: starts with a \ (backslash) and endwith white space

\7400

\.*.$.{*}\~Q

Keywords: Cannot be used as identifiersE.g. initial , assign , module

Basics




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y g g yy g g y

Comments: Two forms/* First form: camextend over

many lines */// Second form: ends at the end of this line

$SystemTask / $SystemFunction

$time$monitor Compiler-directive: directive remains in effectthrough the rest of compilation.

// Text substitution

define MAX_BUS_SIZE 32 ......reg [ MAX_BUS_SIZE -1:0] ADDRESS;

Basics (Contd)



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Comment examplesa = b && c; // This is a one-line comment/* This is a multiple linecomment *//* This is /* an illegal */ comment *//* This is //a legal comment */

Operatorsa = ~ b; // ~ is a unary operator. b is the operanda = b && c; // && is a binary operator. b and c are

operandsa = b ? c : d; // ?: is a ternary operator. b, c and d are

operands

Lexical Conventions (2)




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There are two types of number specification inVerilog: sized and unsized

Sized numbers ' 4'b1111 // This is a 4-bit binary number 12'habc // This is a 12-bit hexadecimal number 16'd255 // This is a 16-bit decimal number

Unsized numbers: Decimal numbers with a default size23456 // This is a 32-bit decimal number by default

'hc3 // This is a 32-bit hexadecimal number 'o21 // This is a 32-bit octal number

Number Specification




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Negative numbersNegative numbers can be specified by putting a minussign before the size for a constant number

-6'd3 // 8-bit negative number stored as 2's complement of 3-6'sd3 // Used for performing signed integer math

4'd-2 // Illegal specification

X or Z values An unknown value is denoted by an xA high impedance value is denoted by z

12'h13x // This is a 12-bit number; 4 least significant bits unknown6'hx // This is a 6-bit hex number 32'bz // This is a 32-bit high impedance number

Number Specification




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Strings A string is a sequence of characters that are enclosedby double quotesIt cannot be on multiple lines

Strings are treated as a sequence of one-byte ASCIIvalues

"Hello Verilog World" // is a string"a / b" // is a stringreg [8*18:1] string_value; // Declare a variable that is 18 bytes wide

Initialstring_value = "Hello Verilog World"; // String can be stored in variable

An underscore character "_" is allowed anywhere in anumber except the first character to improve readability

Strings




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Keywords are special identifiers reserved to definethe language constructs written in lowercaseIdentifiers are names given to objects so that theycan be referenced in the designIdentifiers are made up of alphanumeric characters,the underscore ( _ ), or the dollar sign ( $ )Identifiers are case sensitiveIdentifiers start with an alphabetic character or an

underscorereg value; // reg is a keyword; value is an identifier input clk; // input is a keyword, clk is an identifier

Identifiers and Keywords




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Value SetVerilog supports four values and eightstrengths to model thefunctionality of realhardwareThe four value levelsare: 0, 1, x, z

strength levels areoften used to resolveconflicts betweendrivers of different

strengths in digitalcircuits

Data Types




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Nets represent connections between hardware elements

Nets are declared primarily with the keyword wireThe terms wire and net are often used interchangeablyNets get the output value of their driversThe default value of a net is z

Example:

wire a; // Declare net a for the above circuitwire b,c; // Declare two wires b,c for the above circuitwire d = 1'b0; // Net d is fixed to logic value 0 at declaration.

Nets




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Registers represent data storage elements

Registers retain value until another value is placedonto themUnlike a net, a register does not need a driver Register data types are commonly declared by thekeyword regRegisters can also be declared as signed variablesThe default value for a reg data type is x

reg reset; // declare a variable reset that can hold its value

initial // this construct will be discussed later begin

reset = 1'b1; //initialize reset to 1 to reset the digital circuit.#100 reset = 1'b0; // after 100 time units reset is deasserted.

end

Registers




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Nets or reg data types can be declared as vectors(multiple bit widths)

wire a; // scalar net variable, defaultwire [7:0] bus; // 8-bit buswire [31:0] busA,busB,busC; // 3 buses of 32-bit width.

reg clock; // scalar register, defaultreg [0:40] virtual_addr; // Vector register, virtual address 41 bits

Vectors can be declared at [high# : low#] or [low#: high#], but the left number in the squaredbrackets is always the most significant bit of thevector

Vectors




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For the vector declarations shown above, it ispossible to address bits or parts of vectorsbusA[7] // bit # 7 of vector busAbus[2:0] // Three least significant bits of vector bus,

// using bus[0:2] is illegal because the significant bit should

// always be on the left of a range specificationvirtual_addr[0:1] // Two most significant bits of vector virtual_addr

Variable Vector Part Select Another ability provided in Verilog HDL is tohave variable part selects of a vector Check the Palnitkar Verilog reference (page 48)

Vector Part Select




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An integer is a general purpose register datatypeIntegers are declared by the keyword integer Integers store values as signed quantities

integer counter; // general purpose variable used as acounter.

initialcounter = -1; // A negative one is stored in the counter

Integer Numbers



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Unsigned integersPadding:10 b10 // padded with 0 s 10 bx10 // padded with x s ? can replace z in a number: used to enhancereadability where z is a high impedance

_(underscore) can be used anywhere to enhancereadability, except as the first character

Example:8 d-6 // illegal-8 d6 // -6 held in 8 bits

Integer Numbers (3)




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Real number constants and real register data types

are declared with the keyword realReal numbers cannot have a range declaration, andtheir default value is 0

real delta; // Define a real variable called delta

initialbegindelta = 4e10; // delta is assigned in scientific notationdelta = 2.13; // delta is assigned a value 2.13

endinteger i; // Define an integer iinitial

i = delta; // i gets the value 2 (rounded value of 2.13)

Real Numbers




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Decimal notation10.51.414210.01

Scientific notation235.1e2 (e is case insensitive) // 23510.03.6E2 // 360.05E-4 // 0.0005

Must have at least one digit on either side of decimalStored and manipulated in double precision(usually 64 bits)

Real Numbers (2)




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Verilog simulation is done with respect tosimulation time

A special time register data type is used inVerilog to store simulation time

A time variable is declared with the keywordtimeThe system function $time is invoked to get thecurrent simulation timetime save_sim_time; // Define a time variable save_sim_timeinitial

save_sim_time = $time; // Save the current simulation time

Time Data Type



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Arrays are allowed in Verilog for reg, integer, time,

real, realtime and vector register data typesMulti-dimensional arrays can also be declaredwith any number of dimensions

Arrays of nets can also be used to connect ports

of generated instances Arrays are accessed by[]

integer count[0:7]; // An array of 8 count variablesreg bool[31:0]; // Array of 32 one-bit boolean register variablestime chk_point[1:100]; // Array of 100 time checkpoint variablesinteger matrix[4:0][0:255]; // Two dimensional array of integerswire [7:0] w_array2 [5:0]; // Declare an array of 8 bit vector wirewire w_array1[7:0][5:0]; // Declare an array of single bit wires

Arrays




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Memories are modeled in Verilog simply as aone-dimensional array of registersEach element of the array is known as anelement or word and is addressed by a single

array indexEach word can be one or more bits

reg mem1bit[0:1023]; // Memory mem1bit with 1K 1-bit wordsreg [7:0] membyte[0:1023]; // Memory membyte with 1K

//8-bit words(bytes)membyte[511] // Fetches 1 byte word whose address is 511.

Memories




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Verilog allows constants to be defined in amodule by the keyword parameter Parameters cannot be used as variablesParameter values for each module instance can

be overridden individually at compile timeThis allows the module instances to becustomized

Parameters values can be changed at moduleinstantiation or by using the defparam statementparameter port_id = 5; // Defines a constant port_idparameter cache_line_width = 256; // Defines width of cache_line

parameter signed [15:0] WIDTH; // Fixed sign and range for width

Parameters




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Two waysdefparam statement:

Parameter value in any module instance can bechanged by using hierarchical name.

defparam FA.n1.XOR_DELAY = 2,FA.n2.AND_DELAY = 3;

Module instance parameter value assignment:Specify the parameter value in the moduleinstantiation.Order of assignment is the same as order of declarations within module

HA # (2, 3) h1 (.A(p), .B(Q), .S(S1), .C(X1));

Module Parameter Values




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Verilog provides standard system tasks for certainroutine operations

All system tasks appear in the form $Displaying information: $display is the main system taskfor displaying values of variables or strings or expressions$display(p1, p2, p3,....., pn); // p1, p2, p3,..., pn can be quoted

//strings or variables or expressions/Display value of current simulation time 230$display($time);

-- 230//Display value of port_id 5 in binaryreg [4:0] port_id;$display("ID of the port is %b", port_id);-- ID of the port is 00101

System Tasks




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Monitoring information: $monitor continuously

monitors the values of the variables or signalsspecified in the parameter list and displays allparameters in the list whenever the value of anyone variable or signal changes

$monitor(p1,p2,p3,....,pn); //p1, p2, ... , pn can be variables,//signal names, or quoted strings//Monitor time and value of the signals clock and reset//Clock toggles every 5 time units and reset goes down at 10 time unitsinitial

begin$monitor($time, " Value of signals clock = %b reset = %b",

clock,reset);end

System Tasks (2)




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Stopping and finishing in a simulation

The task $stop is provided to stop during a simulationThe $stop task puts the simulation in an interactive mode toenable debugingThe $finish task terminates the simulation

// Stop at time 100 in the simulation and examine the results// Finish the simulation at time 1000.initial // to be explained later. time = 0

beginclock = 0;

reset = 1;#100 $stop; // This will suspend the simulation at time = 100#900 $finish; // This will terminate the simulation at time = 1000

end

System Tasks (3)



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Modules and Ports



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To understand the components of a moduleshown above, check Example 4-1 (Palnitkar, P#63)

Components of a Verilog Module




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Ports provide the interface by which a modulecan communicate with its environmentThe internals of the module are not visible to theenvironment

This provides a very powerful flexibility to thedesigner The internals of the module can be changedwithout affecting the environment as long as theinterface is not modifiedPorts are also referred to as terminals

Ports




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A module definition contains an optional list of portsConsider a 4-bit full adder that is instantiatedinside a top-level module Top

Example

module fulladd4(sum, c_out, a, b, c_in); //Module with a list of portsmodule Top; // No list of ports, top-level module in simulation

List of Ports




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All ports in the list of ports must be declared in the moduleas follows

Each port in the port list is defined as input, output, or inout, based on the direction of the port signal

module fulladd4(sum, c_out, a, b, c_in);//Begin port declarationoutput[3:0] sum;output c_cout;input [3:0] a, b;input c_in;//End port declaration

Port Declaration


Alternative Declarationmodule fulladd4(output reg [3:0] sum,output reg c_out, // output and c_out are

//declared as reginput [3:0] a, b, //wire by defaultinput c_in); //wire by default



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Note that all port declarations are implicitly

declared as wire in VerilogThus, if a port is intended to be a wire, it issufficient to declare it as output, input, or inoutInput or inout ports are normally declared aswiresHowever, if output ports hold their value, theymust be declared as reg (inout cannot be

declared as reg)module DFF(q, d, clk, reset);output q;reg q; // Output port q holds value; therefore it is//declared as reg.in ut d clk reset

Port Declaration (2)




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There are rules governing port connectionswhen modules are instantiated within other modules

Width matchingUnconnected ports: Verilog allows ports to remainunconnected

Port Connection Rules




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There are two methods of making connections

between signals specified in the moduleinstantiation and the ports in a module definitionConnecting by ordered list: The signals to beconnected must appear in the module instantiation inthe same order as the ports in the port list in the module

definitionmodule Top;//Declare connection variablesreg [3:0]A,B;reg C_IN;

wire [3:0] SUM;wire C_OUT;//Instantiate fulladd4, call it fa_ordered.//Signals are connected to ports in order (by position)fulladd4 fa_ordered(SUM, C_OUT, A, B, C_IN);

Connecting Ports to External Signals



l l ( )


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Connecting ports by name: Verilog provides the

capability to connect external signals to ports by theport names, rather than by position

// Instantiate module fa_byname and connect signals to ports by namefulladd4 fa_byname(.c_out(C_OUT), .sum(SUM), .b(B), .c_in(C_IN),

.a(A),);

Note that only those ports that are to be connected toexternal signals must be specified in port connection bynameUnconnected ports can be dropped

// Instantiate module fa_byname and connect signals to ports by namefulladd4 fa_byname(.sum(SUM), .b(B), .c_in(C_IN), .a(A),);

Connecting Ports to External Signals (2)



i h


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Module definition:

module module_name ( port_list );declarations_and_statements

endmodule

Module instantiation statement:

module_name instance_name ( port_associations );Port associations can be positional or named; cannotbe mixed

local_net_name // positional

Port_Name (local_net_name ) // NamedPorts can be: input, output, inoutPort can be declared as a net or a reg; must havesame size as port

Hierarchy



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Unconnected module inputs are driven to zstateUnconnected module outputs are simplyunused

DFF d1 (.Q(QS), .QBAR(), .DADA(D),.PRESET(), .CLOCK(CK)); // Named

DFF d2 (QS, , D, , CK); // Positional// Output QBAR is not connected// Input PRESET is open and hence set to calue z

Hierarchy (2)



Hi hi l I i i


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Hierarchical Instantiationmodule sub_block1 (a, z);

input a;output z;wire a, z;IV U1 (.A(a), .Z(z));

endmodule

module sub_block2 (a, z);input a;

output z;wire a, z;IV U1 (.A(a), .Z(z));endmodule

module top (din1, din2, dout1,dout2);

input din1;input din2;output dout1;output dout2;

wire din1, din2, dout1, dout2;

sub_block1 U1(.a(din1), .z(dout1));;

sub_block2 U2(.a(din2), .z(dout2));;endmodule

72EE432 VLSI Modeling and Design


Hi hi l N


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Hierarchical name referencing allows us to denote everyidentifier in the design hierarchy with a unique name

A hierarchical name is a list of identifiers separated bydots (".") for each level of hierarchyThe top-level module is called the root module becauseit is not instantiated anywhere

Example:stimulus stimulus.qstimulus.qbar

stimulus.set

stimulus.reset stimulus.m1stimulus.m1.Qbar stimulus.m1.Q

stimulus.m1.Sstimulus.m1.R

stimulus.n1 stimulus.n2

Hierarchical Names



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Every identifier has a unique hierarchical path name

Period character is the separator New hierarchy is defined by: module instantiation, taskdefinition, function definition, named block

Hierarchical Path Name


function FUNC

module Top wire SBUS

module CHILDreg ART

task PROCreg ART

block BLAinteger DOT

block BLBreg ART, CIT

TOP.CHILD.ARTTOP.PROC.ARTTOP.PROC.BLB.CITTOP.PROC.BLA.DOTTOP.SBUS



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Gate-Level Modeling



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G t T


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Verilog supports basic logic gates as predefinedprimitivesThese primitives are instantiated like modulesexcept that they are predefined in Verilog and

do not need a module definitionThere are two classes of basic gates: and/or gates and buf/not gates

Gate Types



A d/O G t


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The and/or gates available in Verilog areand or xor nand nor xnor

The output terminal is denoted by out

Input terminals are denoted by i1 and i2More than two inputs can be specified in a gateinstantiation

And/Or Gates



B f/N t G t


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Buf/not gates have one scalar input and one or more scalar outputsTwo basic buf/not gate primitives are provided inVerilog

buf not

Buf/Not Gates



B fif/notif


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Gates with an additional control signal on buf and not

gates are also availablebufif1 notif1bufif0 notif0

These gates propagate only if their control signal isassertedThey propagate z if their control signal is deasserted

Bufif/notif



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Examples


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Gate-level multiplexer

Examples



4 bit Ripple Carry Full Adder


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4-bit Ripple Carry Full Adder


4-bit Ripple Carry Adder

1-bit full adder


Gate Delays


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Gate delays allow the Verilog user to specify delays

through the logic circuitsThree types of delay specifications are allowedRise (0, x, z 1)Fall (1, x, z 0)

Turn-off (0, 1, x z)If no delays are specified, the default value is zero

// Delay of delay_time for all transitionsand #(delay_time) a1(out, i1, i2);

// Rise and Fall Delay Specification.and #(rise_val, fall_val) a2(out, i1, i2);// Rise, Fall, and Turn-off Delay Specificationbufif0 #(rise_val, fall_val, turnoff_val) b1 (out, in, control);

Gate Delays



Gate Delays (2)


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Signal propagation delay from any gate input to

the gate outputUp to three values per output: rise, fall, turn-off delay

not N1 (XBAR, X); // Zero delaynand #(6) (out, in1, in2); // All delays = 6and #(3,5) (out, in1, in2, in3); /* rise delay = 3, fall delay = 5,

to_x_or_z = min(3,5) */

Each delay can be written in min:typ:max formas well

nand #(2:3:4, 4:3:4) (out, in1, in2);

Can also use a specify block to specify delays

Gate Delays (2)



Example


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// Define a simple combination module called Dmodule D (out, a, b, c);

// I/O port declarationsoutput out;input a,b,c;

// Internal netswire e;

// Instantiate primitive gates to build the circuitand #(5) a1(e, a, b); //Delay of 5 on gate a1or #(4) o1(out, e,c); //Delay of 4 on gate o1endmodule

Example



A Clock Generator


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module CLOCK (CLK);output CLK;

initial beginSTART = 1;#3 START = 0;

end

nor #5 (CLK, START, CLK);endmodule

// Generate a clock with on-off width of 5

// Not synthesizable// For waveform only

A Clock Generator



Time Unit and Precision


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Compiler directive: timescaletimescale time_unit / time_precision ;

1, 10, 100 /s, ms, us, ns, ps, fstimescale 1ns / 100psmodule AND_FUNC (Z, A, B);

output Z;input A, B;and # (5.22, 6.17) A1 (Z, A, B);

endmodule /* Delays are in ns. Delays are rounded to one-tenth of a ns(100ps). Therefore,

5.22 becomes 5.2ns, 6.17 becomes 6.2ns and 8.59 becomes8.6ns */// If the following timescale directive is used:timescale 10ns / 1ns// Then 5.22 becomes 52ns, 6.17 becomes 62ns, 8.59 becomes86ns

Time Unit and Precision



Getting Simulation Time


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System function, $ time : returns the simulation

time as an integer value scaled time unitspecified.

timescale 10ns / 1nsmodule TB;

......initial$monitor (PUT_A=%d PUT_B=%d, PUT_A, PUT_B,

GET_O=%d, GET_O, at time %t, $time );endmodule

PUT_A=0 PUT_B=0 GET_O=0 at time 0PUT_A=0 PUT_B=1 GET_O=0 at time 5PUT_A=0 PUT_B=0 GET_O=0 at time 11....../* $time calue is scaled to the time unit and then rounded */

Getting Simulation Time




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Switch-Level Modeling



Introduction


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Verilog provides the ability to design at a MOS-

transistor levelVerilog HDL currently provides only digitaldesign capability with logic values 0 1, x, z

There is no analog capabilityThus, in Verilog HDL, transistors are also knownswitches that either conduct or are open

Design at this level is becoming rare with theincreasing complexity of circuits

Introduction



MOS Switches


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Two types of MOS switches can be defined with

the keywords nmos and pmos

Example:

nmos n1(out, data, control); //instantiate a nmos switchpmos p1(out, data, control); //instantiate a pmos switch

MOS Switches



MOS Switches (2)


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The value of the out signal is determined from the values of data and control signals.Logic tables for out are shown in the following TableSome combinations of data and control cause the output to beeither a 1 or 0, or to an z value without a preference for either valueThe symbol L stands for 0 or z; H stands for 1 or z

MOS Switches (2)



CMOS Switches


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CMOS switches are declared with the keyword

cmos

Example:

cmos c1(out, data, ncontrol, pcontrol);//instantiate cmos gate.

CMOS Switches



Bidirectional Switches


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Three keywords are used to define bidirectional

switches: tran, tranif0, and tranif1

Example:tran t1(inout1, inout2); //instance name t1 is optionaltranif0 (inout1, inout2, control); //instance name is not specified

Bidirectional Switches



Power and Ground


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The power (Vdd, logic 1) and Ground (Vss, logic

0) sources are needed when transistor-levelcircuits are designedPower and ground sources are defined with

keywords supply1 and supply0Example:supply1 vdd;supply0 gnd;assign a = vdd; //Connect a to vddassign b = gnd; //Connect b to gnd

Power and Ground



Resistive Switches


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Resistive switches have higher source-to-drain

impedance than regular switches and reducethe strength of signals passing through themResistive switches are declared with keywords

that have an "r" prefixed to the correspondingkeyword for the regular switch

rnmos rpmos //resistive nmos and pmos switches

rcmos //resistive cmos switchrtran rtranif0 rtranif1 //resistive bidirectional switches

Resistive Switches



Example: CMOS NOR Gate


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//Define our own nor gate, my_nor module my_nor(out, a, b);output out;input a, b;//internal wireswire c;//set up power and ground linessupply1 pwr; //pwr is connected to Vddsupply0 gnd ; //gnd is connected to Vss(ground)//instantiate pmos switchespmos (c, pwr, b);

pmos (out, c, a);//instantiate nmos switchesnmos (out, gnd, a);nmos (out, gnd, b);endmodule

Example: CMOS NOR Gate



Example: 2-to-1 Multiplexer


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//Define a 2-to-1 multiplexer using switches

module my_mux (out, s, i0, i1);output out;input s, i0, i1;//internal wirewire sbar; //complement of s//create the complement of s;//use my_nor defined previously.my_nor nt(sbar, s, s); //equivalent to a not gate//instantiate cmos switchescmos (out, i0, sbar, s);cmos (out, i1, s, sbar);endmodule

Example: 2 to 1 Multiplexer




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User-Defined Primitives



Introduction


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Verilog provides the ability to define User-

Defined Primitives (UDP)There are two types of UDPs: combinationaland sequential

Combinational UDPs are defined where the outputis solely determined by a logical combination of theinputsSequential UDPs take the value of the current

inputs and the current output to determine thevalue of the next output.

Introduction



UDP basics


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UDP basicsUDP definition in pseudosyntax form is as follows:

//UDP name and terminal listprimitive ((onlyone allowed) );

//Terminal declarationsoutput

;input ;reg;(optional; only for sequential UDP)

// UDP initialization (optional;only for sequential UDPinitial = ;

//UDP state tabletable

endtable

//End of UDP definitionendprimitive



UDP Rules


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UDPs can take only scalar input terminals (1 bit)

UDPs can have only one scalar output terminal (1 bit)always appearing first in the terminal listIn the declarations section, the output terminal isdeclared with the keyword output

The output terminal of sequential UDP is declared asa regThe inputs are declared with the keyword inputThe state in a sequential UDP can be initialized withan initial statementThe state table entries can contain values 0, 1, or xUDPs are defined at the same level as modules

UDPs do not support inout ports

UDP Rules



State Table Entries


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Each entry in the state table in a combinational

UDP has the following pseudosyntax ..... : ;The values in a state table entry mustappear in the same order as they appear in the

input terminal listInputs and output are separated by a ":" A state table entry ends with a ";" All possible combinations of inputs, where theoutput produces a known value, must be explicitlyspecified. Otherwise, if a certain combinationoccurs and the corresponding entry is not in thetable, the output is x.

State Table Entries



Combinational UDP


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primitive MUX1BIT (Z, A, B, SEL);output Z;

input A, B, SEL;

table // A B SEL : Z

0 ? 1 : 0 ;1 ? 1 : 1 ;? 0 0 : 0 ;? 1 0 : 1 ;0 0 x : 0 ;1 1 x : 1 ;

endtable endprimitive

Any combination that is not specified is an x.Output port must be the first port.? represents iteration over 0, 1, or x logic values


Don t care


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Sequential UDP (Level)


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Level-sensitive sequential UDP example:primitive LATCH (Q, CLK, D);output Q;

reg Q;input CLK, D;

table

// CLK Data State Output(next state)1 1 : ? : 1 ;1 0 : ? : 0 ;0 ? : ? : - ;

endtable Endprimitive

? means don t -care- means no change in output

q ( )



Sequential UDP (Edge)


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Edge-sensitive sequential UDP example:primitive D_EDGE_FF (Q, CLK, D);output Q;

reg Q;input CLK, D;

table

// CLK Data State Output(next state)(01) 0 : ? : 0 ;(01) 1 : ? : 1 ;(0x) 1 : 1 : 1 ;(0x) 0 : 0 : 0 ;

// Ignore negative edge of clock;

(?0) ? : ? : - ;// Ignore data change on steady clock;? (??) : ? : - ;

endtable endprimitive

q ( g )




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Dataflow Modeling



Introduction


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For small circuits, the gate-level modeling

approach works very wellHowever, in complex designs the number of gates is very large

Thus, designers can design more effectively if they concentrate on implementing the functionat a level of abstraction higher than gate levelDataflow modeling provides a powerful way toimplement a designIn logic synthesis, automated tools create agate-level circuit from a dataflow description



Basics


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Models behavior of combinational logic

Dataflow style using continuous assignment Assign a value to a netExamples:

wire [3:0] Z, PRESET, CLEAR;assign Z = PRESET & CLEAR;

wire COUT, CIN;wire [3:0] SUM, A, B;assign {COUT, SUM} = A+ B + CIN;assign MUX = (S == 0) ? A: bz,

MUX = (S == 1) ? B: bz,MUX = (S == 2) ? C: bz,MUX = (S == 3) ? D: bz;

assign Z = ~(A | B) & ( C | D);Expression on right-hand side is evaluatedwhenever any operand changes



Net Declaration


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Can have an assignment in the net declaration wire [3:0] A = 4 b0; assign PRESET = b1;

wire #10 A_GT_B = A > B;

Only one assignment to a net using net declaration

Multiple assignments to a net is done using continuousassignmentsContinuous assignments have the followingcharacteristics:

The left hand side of an assignment must be a net (cannot be areg)Continuous assignments are always activeThe operands on the right-hand side can be registers or nets or function calls



Delays


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Delay values control the time between the

change in a right-hand-side operand and whenthe new value is assigned to the left-hand sideRegular Assignment Delay

assign #10 out = in1 & in2; // Delay in a continuous assign

y



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Expressions, Operators, and Operands


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Dataflow modeling describes the design in terms of

expressions instead of primitive gatesExpressions are constructs that combine operatorsand operands to produce a result

// Examples of expressions. Combines operands and operators

a ^ baddr1[20:17] + addr2[20:17]in1 | in2

Operands can be any one of the data types definedpreviously

integer count, final_count;final_count = count + 1;//count is an integer operand

p p p



Operands


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1. Numbered operands2. Functional call operands

A functional call can be used as an operand within anexpression

wire [7:0] A;// PARITY is a function described elsewhereassign PAR_OUT = PARITY(A);

3. Bit selectsinput [3:0] A, B, C;output [3:0] SUM;assign SUM[0] = (A[0] ^ B[0] ^ C[0]);

4. Part selects5. Memory addressingreg [7:0] RegFile [0:10]; // 11 b-bit registersreg [7:0] A;RegFile[3] = A; // A assigned to 3rd register in RegFile



Operators


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Operators act on the operands to produce

desired resultsd1 && d2 // && is an operator on operands d1 and d2


Arithmetic * / + - % **Logical ! && ||

Relational > < >= > >>


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+ (plus)- (minus)* (multiply)/ (divide)% (modulus)

Integer division will truncate

% gives the remainder with the sign of the firstoperandIf any bit of operand is x or z, the result is x reg data type holds an unsigned value, while integer

data type holds a signed valuereg [0:7] A;integer B;

A = -4 d6; // reg A has value unsigned 10B = -4 d6; // integer B has value signed -6

A-2 // result is 8B-2 // result is -8



Relational Operators


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> (greater than)< (less than)>= (greater than or equal to)


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== (logical equality, result may be unknown)!= (logical inequality, result may beunknown)=== (case equality, x and z also compared)!== (case inequality, x and z also compared)

A = b11x0; B = b11x0;

A == B is known.

A === B is true

Unknown is same as false in synthesisCompare bit by bit, zero-filling on most significantside


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Logical Operators


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&& (logical and)

|| (logical or)

A = b0110; // non-zeroB = b0100; // non-zero

A || B is 1. A && B is also 1

Non-zero value is treated as 1If result is ambiguous, set it to x




Bit-wise Operators


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~ (unary negation)& (binary and)| (binary or)^ (binary exclusive-or)~^,^~ (binary exclusive-nor)

A = b0110; B = b0100;

A | B is 0110 A & B is 0100

If operand sizes are unequal, smaller is zero-filed inthe most significant bit side




Reduction Operators


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& (unary and)~& (unary nand)| (unary or)~| (unary nor)^ (unary xor)~^ (unary xnor)

A = b0110; B = b0100;

| B is 1& B is 0

Bitwise operation on a single operand to produce 1-bitresult




Shift Operators


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> (right shift)

reg [0:7] D;

D = 4 b0111;

D >> 2 has the value 0001

Logic shift, fill vacant bits with 0If right operand is an x or a z, result is xRight operand is always an unsigned number




Conditional Operators


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expr1 ? expr2:expr3

wire [0:2] GRADE = SCORE > 60 ? PASS:FAIL;If expr1 is an x or a z, expr2 and expr3 arecombined bit by bit (all x s except 0 with 0 = 0, 1with 1 = 1)

Example:

//model functionality of a 2-to-1 mux

assign out = control ? in1 : in0;




Concatenation and Replication


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wire [7:0] DBUS;wire [11:0] ABUS;

assign ABUS[7:4] = {DBUS[0], DBUS[1], DBUS[2], DBUS30]};assign ABUS = {DBUS[3:0], DBUS[7:4]};

assign DBUS[7:4] = {2{4 B1011}}; // 1011_1011assign ABUS[7:4] = {{4{DBUS[7]}, DBUS}; // sign extension




Examples


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Write the Verilog description and test benches of

the following circuits using dataflow modeling:4-to-1 Multiplexer

Logic equation

Conditional operator 4-bit Full Adder Dataflow operatorsFull adder with carry lookahead

Ripple Counter




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Behavioral Modeling




Introduction


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Designers need to be able to evaluate the trade-

offs of various architectures and algorithms inthe earlier design stages Architectural evaluation takes place at analgorithmic levelVerilog provides designers the ability to describedesign functionality in an algorithmic manner In other words, the designer describes thebehavior of the circuitBehavioral modeling represents the circuit at avery high level of abstraction




Procedure Blocks


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Use procedural blocks to describe theoperation of the circuitTwo procedural blocks:

always block: executes repetitivelyinitial block: executes once

Concurrent procedural blocks

All execute concurrently All activated at time 0



The initial Block


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An initial block starts at time0, executes exactly onceduring a simulationPorts and variables can beinitialized in declaration

The initial block is alwaysused in testbenches

Example:module stimulus;

reg x,y, a,b, m;initial

m = 1'b0; //single statement; //does//not need to be grouped

initialbegin

#5 a = 1'b1; //multiple//statements; need to be grouped

#25 b = 1'b0;end

initialbegin

#10 x = 1'b0;#25 y = 1'b1;

endinitial

#50 $finish;endmodule




The always Block


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Can model:

combinational logicsequential logic

Syntax:// Single statementalways @ ( event expression )

statement // Sequential statementsalways @ ( event expression )

beginsequential statements

end




The always Block (2)


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event expression specified a set of events

based on which statements within the alwaysblock are executed sequentiallyThe type of logic synthesized is based on whatis specified in the event expression Four forms of event expressions are supported

An OR of several identifiers (comb/seq logic)The rising edge clock (register inference)

The falling edge clock (register inference) Asynchronous reset (register inference)



Event Expressions


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1. An OR of several identifiersCombinational or synchronous logic may be represented by a set of sequential statementsalways @ ( id1 or id2 or id3 or ... or idn )

beginsequential_statements

end

A synchronous block may appear inside an always block (representingsynchronous logic) in two forms:always @ ( posedge clock_name )

beginsequential_statements

end

always @ ( negedge clock_name )beginsequential_statements

endSequential statements not within a sequential block represents combinationallogic



Example


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module Comb (A, B, C, Y);input A, B, C;output Y;reg Y;

always @ ( A or B or C )begin

Y = A ^ B ^ C;end

endmodule



2 Th i i d l k ( i i f )Event Expressions


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2. The rising edge clock (register inference)The event expression denotes the rising edge of a clockThe behavior within block represents synchronous logic triggeredon the rising edge of clockalways @ ( posedge CLK)

beginQ = D;

end3. The falling edge clock (register inference)

The event expression denotes the falling edge of a clockThe behavior within block represents synchronous logic triggered

on the rising edge of clockalways @ ( negedge CLK)

beginNext_state = Current_state;

end



Register Inference


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module SEQ (CLK, A, B, Y);input CLK, A, B;output Y;reg Y;

always @ (posedge CLK )begin

Y = A + B;end

endmodule


CLK

A

B CLK

D Q

Q

Y


A h ( i i f )Event Expressions


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4. Asynchronous reset (register inference) Asynchronous resets in addition to register inferences (2& 3 above)always @ (negedge reset1or posedge CLK or posedge reset2)

beginif (!reset1)

begin/* sequential_statementsasynchronous input triggered by the false condition of reset1 to the registers */

endelse

begin/* sequential_statementOptional for sequential statements. Could well have else -if clauses*/

if (!reset2)begin

/* sequential_statements: Asynchronous inputs triggered by reset2 */end

elsebegin

// sequential_statements: register inference statements.end

endend



Register Inference


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The language constructs registers is

synthesized as a hardware register (flip-flop) if the register is assigned a value in: A sequential block An always block that has an event expressiondenoting a rising or falling clock edge

It is illegal to assign a register value on bothrising and falling edges of a clock



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Sequential Statements and the Always Block(2)


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An always block is concurrent and so may

appear in any order within a module bodywith other continuous assignments (moduleinstantiations or other always block)

Data is passed out of an always block usingregister variables



P d l i d l f i l

Procedural Assignments


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Procedural assignments update values of reg, integer, real, or time variablesThe value placed on a variable will remain unchanged untilanother procedural assignment updates the variable with adifferent valueThe syntax of procedural assignment

assignment ::= variable_lvalue = [ delay_or_event_control ]expression

The left-hand side of a procedural assignment canbe

A reg, integer, real, or time register variable or a memory elementA bit select of these variables (e.g., addr[0])

A part select of these variables (e.g., addr[31:16]) A concatenation of any of the above

There are two types of procedural assignment statements: blockingand nonblockinEE 432 VLSI Modeling and Design 142


Bl ki d l iBlocking versus Non-Blocking


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Blocking procedural assignment: Assignment is executed before any of the followingones are executed.Only applies to its own sequential block.

reg_a = 10;Non-blocking procedural assignment.

The procedural flow is not blocked# 2

reg_a


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Blocking (=)

Assignment are blocked,i.e., they must beexecuted beforesubsequent statementsare executed

always @ (posedgeclock)

beginB = A;C = B;D = C;

end1 flip-flop (Data in is A,data out is D)

Non-blocking (


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It is recommended that blocking and non-blockingassignments not be mixed in the same always blockUsing non-blocking assignments in place of blockingassignments is highly recommended in places whereconcurrent data transfers take place after a commonevent

blocking assignments can potentially cause raceconditions because the final result depends on theorder in which the assignments are evaluatedTypical applications of non-blocking assignmentsinclude pipeline modeling and modeling of several

mutually exclusive data transfersOn the downside, non-blocking assignments canpotentially cause a degradation in the simulator performance and increase in memory usage

g

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Blocking assignmentExample


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Blocking assignment initial

begin CLR = #5 0;CLR = #4 1;CLR = #10 1;

end// CLR is assigned at time 5, and then at 9 and then at 19

Non-blocking assignment initialbegin

CLR


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Allow expression to be driven continuously into

integers or netsassign and deassign procedural statements: for integersforce and release procedural statements: for nets

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A d l id Assign and Deassign


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An assign procedural statement overrides

all procedural assignments to a register The deassign procedural statement endsthe continuous assignment to a register

Value remains until assigned againIf assign applied to an already assignedregister, it is deassigned first before making

the new procedural continuous assignment


module DFF (D CLR CLK PRESET Q);

Example


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module DFF (D, CLR, CLK, PRESET, Q);input D, CLR, CLK, PRESET;output Q;reg Q;always @ (CLR or PRESET)

if (!CLR)assign

Q = 0; // D has no effect on Qelse if (!PRESET)assign Q = 1; // D has no effect on Q

elsedeassign Q;

always @ (posedge CLK)Q = D;endmodule ;


Si il t i d i t th t it b

Force and Release


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Similar to assign-deassign, except that it can be

applied to nets as well as registersforce procedural statement on a net overrides alldrivers of the net, until a release is executed on thenet

......or #1 (PRT, STD, DXZ);

initial begin

force PRT = DXZ & STD;#5 // Wait for 5 time units.release PRT;$finish ;

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ifHigh-Level Constructs


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if statementloop statement ( forever , repeat , while ,for )case statement


C diti l t t t d f ki

Conditional Statements


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Conditional statements are used for making

decisions based upon certain conditionsThese conditions are used to decide whether or not a statement should be executedKeywords if and else are used for conditionalstatementsThere are three types of conditional statements

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Usage of conditional statements is shown belowConditional Statements (2)


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Usage of conditional statements is shown below//Type 1 conditional statement. No else statement.

//Statement executes or does not execute.if () true_statement ;

//Type 2 conditional statement. One else statement//Either true_statement or false_statement is evaluatedif () true_statement ; else false_statement ;

//Type 3 conditional statement. Nested if-else-if.//Choice of multiple statements. Only one is executed.if () true_statement1 ;else if () true_statement2 ;else if () true_statement3 ;else default_statement ;

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Examples//Type 1 statements //Type 3 statements


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//Type 1 statementsif (!lock) buffer = data;if (enable) out = in;//Type 2 statementsif (number_queued

2-System Specifications Using Verilog HDL

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