Verilog Language Concepts
description
Transcript of Verilog Language Concepts
1Verilog Digital System Design Z. Navabi, 2006
Verilog Language Verilog Language ConceptsConcepts
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Now we are going to see:Now we are going to see: How modules are developedHow modules are developed How names, numbers and operators are usedHow names, numbers and operators are used
Module BasicsModule Basics
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Module BasicsModule BasicsModuleModule
BasicsBasics
Wires andWires andVariablesVariables ModulesModules
CodeCodeFormatFormat
Logic ValueLogic ValueSystemSystem
ModuleModulePortsPorts NamesNames NumbersNumbers
ArraysArrays VerilogVerilogOperatorsOperators
VerilogVerilogData TypesData Types
ArrayArrayIndexingIndexing
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Code FormatCode FormatModuleModule
BasicsBasics
Wires andWires andVariablesVariables ModulesModules
CodeCodeFormatFormat
Logic ValueLogic ValueSystemSystem
ModuleModulePortsPorts NamesNames NumbersNumbers
ArraysArrays VerilogVerilogOperatorsOperators
VerilogVerilogData TypesData Types
ArrayArrayIndexingIndexing
CodeCodeFormatFormat
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Code FormatCode Format
Verilog code is free format.Verilog code is free format. Spaces and new lines are served as separators. Spaces and new lines are served as separators. It is case sensitive.It is case sensitive. Language keywords use lowercase characters.Language keywords use lowercase characters. A comment designator start with // makes the rest of A comment designator start with // makes the rest of
line comment.line comment. The symbols /* … */ bracket the section of code The symbols /* … */ bracket the section of code
which is in between as a comment.which is in between as a comment.
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Logic Value SystemLogic Value SystemModuleModule
BasicsBasics
Wires andWires andVariablesVariables ModulesModules
CodeCodeFormatFormat
Logic ValueLogic ValueSystemSystem
ModuleModulePortsPorts NamesNames NumbersNumbers
ArraysArrays VerilogVerilogOperatorsOperators
VerilogVerilogData TypesData Types
ArrayArrayIndexingIndexing
Logic ValueLogic ValueSystemSystem
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Bit type, or bits of vectors or arrays, of Verilog wires Bit type, or bits of vectors or arrays, of Verilog wires and variables take the and variables take the 4-value logic4-value logic value system. value system.
Values in this system areValues in this system are 0 0, , 11, , ZZ and and XX..
The values The values 00 and and 11 logic low and high. logic low and high.
The The Z Z value represents an undriven, high impedance value represents an undriven, high impedance value.value.
The The XX value represent a conflict in multiple driving value represent a conflict in multiple driving values, an unknown or value of a variable not values, an unknown or value of a variable not initialized.initialized.
Logic Value SystemLogic Value System
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Logic Values and ExamplesLogic Values and Examples
Logic Value SystemLogic Value System
0X
0
1 0
X0 1
1x 1
0 :
1 :
Z or z :
X or x:
0
z1
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Wires and VariablesWires and VariablesModuleModule
BasicsBasics
Wires andWires andVariablesVariables ModulesModules
CodeCodeFormatFormat
Logic ValueLogic ValueSystemSystem
ModuleModulePortsPorts NamesNames NumbersNumbers
ArraysArrays VerilogVerilogOperatorsOperators
VerilogVerilogData TypesData Types
ArrayArrayIndexingIndexing
Wires andWires andVariablesVariables
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Wires and Variables:Wires and Variables: netnet: represents a wire driven by a hardware : represents a wire driven by a hardware
structure or output of a gate.structure or output of a gate. regreg: represents a variable that can be assigned : represents a variable that can be assigned
values in behavior description of a component in a values in behavior description of a component in a Verilog procedural block.Verilog procedural block.
Wires and VariablesWires and Variables
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ModulesModulesModuleModule
BasicsBasics
Wires andWires andVariablesVariables ModulesModules
CodeCodeFormatFormat
Logic ValueLogic ValueSystemSystem
ModuleModulePortsPorts NamesNames NumbersNumbers
ArraysArrays VerilogVerilogOperatorsOperators
VerilogVerilogData TypesData Types
ArrayArrayIndexingIndexing
ModulesModules
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Module is the main structure of definition of Module is the main structure of definition of hardware components and testbenchs.hardware components and testbenchs.
Begins with Begins with modulemodule keyword and end with keyword and end with endmoduleendmodule. .
Immediately following the Immediately following the modulemodule keyword, port list keyword, port list of the module appears enclosed in parenthesis.of the module appears enclosed in parenthesis.
ModulesModules
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`timescale`timescale 1ns/100ps 1ns/100ps
modulemodule FlipFlop (preset, reset, din, clk, qout); FlipFlop (preset, reset, din, clk, qout);
input input preset, reset, din, clk;preset, reset, din, clk;
outputoutput qout; qout;
regreg qout; qout;
alwaysalways @ ( @ (posedgeposedge clk) clk) beginbegin
ifif (reset) qout <= #7 0; (reset) qout <= #7 0;
else ifelse if (preset) qout <= #7 1; (preset) qout <= #7 1;
elseelse qout <= #8 din; qout <= #8 din;
endend
endmoduleendmodule
Ports are only Ports are only listed in the port listed in the port
list and declared as list and declared as separate input and separate input and output ports inside output ports inside
the body of the the body of the Flip-Flop moduleFlip-Flop module..
ModulesModules
Separate Port Declarations StatementsSeparate Port Declarations Statements
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Module PortsModule PortsModuleModule
BasicsBasics
Wires andWires andVariablesVariables ModulesModules
CodeCodeFormatFormat
Logic ValueLogic ValueSystemSystem
ModuleModulePortsPorts NamesNames NumbersNumbers
ArraysArrays VerilogVerilogOperatorsOperators
VerilogVerilogData TypesData Types
ArrayArrayIndexingIndexing
ModuleModulePortsPorts
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Inputs and outputs of a model must be declared as:Inputs and outputs of a model must be declared as: inputinput outputoutput inoutinout
By default, all declared ports are regarded as By default, all declared ports are regarded as netnets s and the default net type is used for the ports.and the default net type is used for the ports.
Ports declared as Ports declared as outputoutput may be declared as may be declared as regreg. . This way they can be assigned values in This way they can be assigned values in procedural blocks. procedural blocks.
An An inoutinout port can be used only as a port can be used only as a net net. Transfers . Transfers signal from and to module.signal from and to module.
Module PortsModule Ports
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NamesNamesModuleModule
BasicsBasics
Wires andWires andVariablesVariables ModulesModules
CodeCodeFormatFormat
Logic ValueLogic ValueSystemSystem
ModuleModulePortsPorts NamesNames NumbersNumbers
ArraysArrays VerilogVerilogOperatorsOperators
VerilogVerilogData TypesData Types
ArrayArrayIndexingIndexing
NamesNames
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A stream of characters starting with a letter or an A stream of characters starting with a letter or an underscore forms a Verilog identifier. underscore forms a Verilog identifier.
The $ character and underscore are allowed in an The $ character and underscore are allowed in an identifier.identifier.
Verilog uses Verilog uses keywordskeywords that are all formed by streams that are all formed by streams of of lowercase characterslowercase characters..
The names of The names of system taskssystem tasks and and functionsfunctions begin with begin with a a $$ character. character.
Compiler directive namesCompiler directive names are preceded by the are preceded by the `̀ (back (back single quote) character. Example: single quote) character. Example: `timescale`timescale
NamesNames
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The following are valid names for identifiers:The following are valid names for identifiers:
a_name , name1 , _name , Name,a_name , name1 , _name , Name,
Name$ , name55 , _55name , setup,Name$ , name55 , _55name , setup,
_$name._$name.
The following are Verilog keywords or system tasks.The following are Verilog keywords or system tasks.
$display$display, , defaultdefault, , $setup$setup,,
beginbegin
NamesNames
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NumbersNumbersModuleModule
BasicsBasics
Wires andWires andVariablesVariables ModulesModules
CodeCodeFormatFormat
Logic ValueLogic ValueSystemSystem
ModuleModulePortsPorts NamesNames NumbersNumbers
ArraysArrays VerilogVerilogOperatorsOperators
VerilogVerilogData TypesData Types
ArrayArrayIndexingIndexing
NumbersNumbers
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Constants in Verilog are Constants in Verilog are integerinteger or or realreal.. Specification of integers can include Specification of integers can include X X and and ZZ in addition to in addition to
the standard the standard 00 and and 11 logic values. logic values. Integers may beIntegers may be
Sized: Sized: Begins with the number of equivalent bitsBegins with the number of equivalent bits Unsized: Unsized: Without the number of bits specificationWithout the number of bits specification
The general format for a sized integers is:The general format for a sized integers is:
number_of_bits number_of_bits ‘ base_identifier‘ base_identifier digits digits
example: 6’b101100example: 6’b101100
The base specifier is a single lower or uppercase The base specifier is a single lower or uppercase character character bb, , dd, , oo or or hh
which respectively stand forwhich respectively stand for binarybinary, , decimaldecimal, , octaloctal and and hexadecimalhexadecimal
bases.bases.
NumbersNumbers
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Optionally, the base-identifier can be preceded by the Optionally, the base-identifier can be preceded by the single character single character ss (or (or S S) to indicate a) to indicate a signed signed quantity.quantity.
A A plus or minusplus or minus operator can be used on the left of the operator can be used on the left of the number specification to change the number specification to change the signsign of the of the number.number.
The The underscoreunderscore character (_) can be used anywhere in character (_) can be used anywhere in a number for a number for groupinggrouping its bits or digits for readability its bits or digits for readability purposes.purposes.
Real constants in Verilog use the standard format as Real constants in Verilog use the standard format as described by IEEE std 754-1985, the IEEE standard for described by IEEE std 754-1985, the IEEE standard for double precision floating-pointdouble precision floating-point numbers. Examples: numbers. Examples: 1.9, 2.6E9, 0.1e-6, 315.96-12.1.9, 2.6E9, 0.1e-6, 315.96-12.
NumbersNumbers
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ArraysArraysModuleModule
BasicsBasics
Wires andWires andVariablesVariables ModulesModules
CodeCodeFormatFormat
Logic ValueLogic ValueSystemSystem
ModuleModulePortsPorts NamesNames NumbersNumbers
ArraysArrays VerilogVerilogOperatorsOperators
VerilogVerilogData TypesData Types
ArrayArrayIndexingIndexing
ArraysArrays
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Verilog allows declaration and usage of multidimensional Verilog allows declaration and usage of multidimensional arrays for arrays for netnets or s or regregs. s.
The following declares The following declares a_array a_array as a two-dimensional as a two-dimensional array of 8-bit words:array of 8-bit words: regreg [7:0] a_array [0:1023][0:511]; [7:0] a_array [0:1023][0:511];
In an array declaration, the address range of the In an array declaration, the address range of the elements of the array comes after the name of the array. elements of the array comes after the name of the array.
Range specificationsRange specifications are enclosed in are enclosed in square bracketssquare brackets. . The size and range specification of the elements of an The size and range specification of the elements of an
array come after the array come after the netnet type (e.g., type (e.g., wirewire) or) or reg reg keyword. keyword. In the absence of a range specification before the name In the absence of a range specification before the name
of the array, an element size of one bit is assumed.of the array, an element size of one bit is assumed.
ArraysArrays
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ArraysArrays
Array SArray Structurestructures
07 Areg
7
0
Amem
// An 8-bit vector
reg [7:0] Areg;
// A memory of 8 one-bit elements
reg Amem [7:0];
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7
0
0
7
3
// A two-dimensional memory of one-bit elements
reg Bmem [7:0] [0:3];
// A memory of four 8-bit wordsreg [7:0] Cmem [0:3];
Bmem
Cmem
ArraysArrays
Array SArray Structures (Continued)tructures (Continued)
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ArraysArrays
Array SArray Structurestructures
4
00
3
12
3
reg [2:0] Dmem [0:3] [0:4];// A two-dimensional memory of 3-bit elements
Dmem
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Verilog OperatorsVerilog OperatorsModuleModule
BasicsBasics
Wires andWires andVariablesVariables ModulesModules
CodeCodeFormatFormat
Logic ValueLogic ValueSystemSystem
ModuleModulePortsPorts NamesNames NumbersNumbers
ArraysArrays VerilogVerilogOperatorsOperators
VerilogVerilogData TypesData Types
ArrayArrayIndexingIndexing
VerilogVerilogOperatorsOperators
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Verilog OperatorsVerilog OperatorsVerilogVerilog
OperatorsOperators
BasicBasicOperatorsOperators
EqualityEqualityOperatorsOperators
BooleanBooleanOperatorsOperators
ShiftShiftOperatorsOperators
ConcatenationConcatenationOperatorsOperators
ConditionalConditionalOperatorsOperators
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Basic OperatorsBasic OperatorsVerilogVerilog
OperatorsOperators
BasicBasicOperatorsOperators
EqualityEqualityOperatorsOperators
BooleanBooleanOperatorsOperators
ShiftShiftOperatorsOperators
ConcatenationConcatenationOperatorsOperators
ConditionalConditionalOperatorsOperators
BasicOperators
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Arithmetic Operations in Verilog take bit, vector, integer Arithmetic Operations in Verilog take bit, vector, integer and real operands.and real operands.
Basic operators of Verilog are Basic operators of Verilog are ++, , --, , **, , // and and ****..
An An XX or a or a Z Z value in a bit of either of the operands of a value in a bit of either of the operands of a multiplication causes the entire result of the multiply multiplication causes the entire result of the multiply operation to become operation to become XX..
Unary plus (+) and minus (−) are allowed in Verilog. Unary plus (+) and minus (−) are allowed in Verilog. These operatorsThese operators
take precedence over other arithmetic operators.take precedence over other arithmetic operators.
If any of the operands of a relational operator contain an If any of the operands of a relational operator contain an XX or a or a ZZ, then the result becomes , then the result becomes XX..
Basic OperatorsBasic Operators