Speaker: Tsung-Yi Wu RTL Coding for FPGA. Verilog Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL)....
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Transcript of Speaker: Tsung-Yi Wu RTL Coding for FPGA. Verilog Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL)....
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Speaker: Tsung-Yi Wu
RTL Coding for FPGA
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Verilog Verilog is a HARDWARE DESCRIPTIO
N LANGUAGE (HDL). Verilog is first introduced in 1984 for Gat
eway Verilog-XL digital simulator In 1989, Gateway acquired by Cadence.
Then in 1990, Cadence release the Verilog language and Verilog PLI to public.
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Verilog
Open Verilog International(OVI) was formed to maintain the Verilog standard, in 1993, OVI releases the Verilog 2.0 Reference Manual, then becomes the IEEE 1364-1995 (Verilog-1995)
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Verilog
The specification of the Verilog-2001 standard is complete– Voting draft completed March 1st, 2000– The official standard will be IEEE Std. 136
4-2001
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On-line Learning and Documents
http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html
http://toolbox.xilinx.com/docsan/2_1i/
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Simulation and Synthesis
Simulation? Synthesis? Testing? Verification? P&R? Configuration?
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Get a Simulator and Synthesizer
http://www.xilinx.com/sxpresso/webpack.htm
Register Now Register for ModelSim
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Register Transfer Level (RTL)
Any code that is synthesizable is called RTL code.
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Gate Level
Within the logic level the characteristics of a system are described by logical links and their timing properties.
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Introduction: Basic Verilog
Integer LiteralsInteger literals can have underscores embedded in t
hem for improved readability. For example,– Binary literal 2’b1Z– Octal literal 2’o17– Decimal literal 9 or ’d9– Hexadecimal literal 3’h189– Decimal literal 24_000
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Introduction: Basic Verilog
6'hCA 001010 truncated, not 11001010 6'hA 001010 filled with two '0' on left 16'bZZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z filled with 16 Z's
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Introduction: Basic Verilog
Module Port Declarations input a,b;output sum;inout c;– An Example
module adder(a,b,sum);input a,b;output sum;:
endmodule
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Introduction: Basic Verilog
Data Typesreal a, b, c; // a,b,c to be realinteger j, k; // integer variableinteger i[1:32]; // array of integer variablesreg [8*14:1] string ; /* This defines a vector with range [msb_expr: lsb_expr] */reg [15:0] mem16X512 [0:511];
// 16-bit by 512 word memory// mem16X512[4] addresses word 4// the order lsb:msb or msb:lsb is not important
wire net1;
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Introduction: Basic Verilog
Net types– wire tri– wand triand– wor trior– tri0 tri1– supply0 supply1– trireg
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Introduction: Basic Verilog
Relational Operators – a<b a less than b– a>b a greater than b– a<=b a less than or equal to b– a>=b a greater than or equal to b
Arithmetic Operators +, -, *, /, % (the modulus operator)
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Introduction: Basic Verilog
Equality Operators – a === b a equal to b, including x and z– a !== b a not equal to b, including x and z– a == b a equal to b, resulting may be unknown– a != b a not equal to b, result may be unknown
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Introduction: Basic Verilog
Logical Operators – ! logic negation– && logical and– || logical or
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Introduction: Basic Verilog
0 if the relation is false 1 if the relation is true x if any of the operands has unknown x
bits z ?
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Introduction: Basic Verilog
Bitwise Operators– ~m Invert each bit of m– m&n AND each bit of m with each bit of n– m|n OR each bit of m with each bit of n– m^n Exclusive OR each bit of m with n
Exercise~(4’b0011)=?
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Example– 0&x = 0 – 1&x = x&x = x – 1|x = 1 – 0|x = x|x = x – 0^x = x
Introduction: Basic Verilog
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<< left shift >> right shift {b, {3{c, d}}}
this is equivalent to {b, c, d, c, d, c, d} out = (enable) ? data : 8'bz;
// Tri state buffer
Introduction: Basic Verilog
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Introduction: Basic Verilog
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Introduction: Basic Verilog
module dff (q,qb,clk,d,rst); input clk,d,rst ; // input signals output q,qb ; // output definition wire dl,dbl ;
// parameter value assignment paramter delay1 = 3, delay2 = delay1 + 1;
nand #delay1 n1(cf,dl,cbf), n2(cbf,clk,cf,rst); nand #delay2 n3(dl,d,dbl,rst), n4(dbl,dl,clk,cbf), n5(q,cbf,qb), n6(qb,dbl,q,rst);
endmodule
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initial : initial blocks execute only once at time zero (start execution at time zero).
always : always blocks loop to execute over and over again, in other words as name means, it executes always
initial is un-synthesizable statement
Introduction: Basic Verilog
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Introduction: Basic Verilog
Example : initial and always
Initial always @ (posedge clk) begin begin : D_FF reset = 0; if (reset == 1) q <= 0; q <= 0; end else q <=d; end
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Introduction: Basic Verilog
Bug?wire clk, resetreg enable, data; Initial begin clk = 0; reset = 0; enable = 0; data = 0; end
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Introduction: Basic Verilog for (i = 0 ; i < 7 ; i=i+1) memory[i] = 0 ; // initialize to 0 repeat (bit-width) b = b << 1; case (select)
0: out[0] = 1; 1: out[1] = 1;endcase
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Introduction: Basic Verilog
while(delay) begin @(posedge clk);
ldlang = oldldlang; delay = delay - 1;end
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Introduction: Basic Verilog
module and_from_nand(A, B, Y);
input A, B;output Y;wire W;// Two instantiations of the module NANDnand U1(A, B, W);nand U2(W, W, Y);
endmodule
Structural model of AND gate from two NANDS
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Introduction: Basic Verilog
always @ (posedge enable) repeat (20) @ (posedge clk) ; while (mem_read == 1'b1) begin
wait (data_ready) data = data_bus; read_ack = 1;end
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Introduction: Basic Verilog
Function function [range] FCTID;
{input [range] {ARGID,};}[{declaration}]begin [{sequential_statement}]endendfunction
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Introduction: Basic Verilog
Task task TASKID;
[{input | output | inout [range] {ARGID,};}][{declaration}]begin [{sequential_statement}]end
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Introduction: Basic Verilog
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Introduction: Basic Verilog
System task– $stop Interrupt– $finish Terminate – $display[defbase]([fmtstr,] {expr,}); – $monitor[defbase] ([fmtstr,] {expr,});
Compiler Directives– `define WORD_SIZE 32– `include head.v– `timescale100 ns / 1 ns
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Introduction: Basic Verilog
Example– $display( “Example of using function”);
/* display to screen */– $monitor($time, “a=%b, clk = %b, add=%h”,
a,clk,add); // monitor signals– $setuphold( posedge clk, datain, setup, hol
d); // setup and hold checks
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Combination CKT Coding
Combinational circuit is used to calculate the next state of the flip-flops
Data Path can be constructed by combination CKT
Combinational CircuitF( inputs, flip-flops )
Sequential CircuitFlip-Flops inside here
InputsOutputs
Outputs
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Combination CKT Coding Verilog Example of Priority Encoded if Statement
module mult_if(a, b, c, d, sel, z);input a, b, c, d;input [3:0] sel;output z;reg z;always @(a or b or c or d or sel)begin
z = 0;if (sel[0]) z = a;if (sel[1]) z = b;if (sel[2]) z = c;if (sel[3]) z = d;
endendmodule
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Combination CKT Coding Verilog Example for Single if Statement (Not Priority Encoded)
module single_if(a, b, c, d, sel, z);input a, b, c, d;input [3:0] sel;output z;reg z;always @(a or b or c or d or sel)begin
z = 0;if (sel[3])z = d;else if (sel[2])z = c;else if (sel[1])z = b;else if(sel[0])z = a;end
endmodule
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Verilog for Single case Statement
module case1(a, b, c, d, sel, z);input a, b, c, d;input [3:0] sel;output z;reg z;always @(a or b or c or d or sel)begin
casex (sel)4’b1xxx: z = d;4’bx1xx: z = c;4’bxx1x: z = b;4’bxxx1: z = a;default: z = 1’b0;endcase
endendmodule
Combination CKT Coding
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Combination CKT Coding
Example 3-1 Verilog for Decoder Using Indexingmodule decoder_index (in1, out1);parameter N = 8;parameter log2N = 3;input [log2N-1:0] in1;output [N-1:0] out1;reg [N-1:0] out1;always @(in1)beginout1 = 0;out1[in1] = 1’b1;endendmodule
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Combination CKT Coding
Example 3-3 Verilog for Decoder Using Loopmodule decoder38_loop (in1, out1); parameter N = 8; parameter log2N = 3; input [log2N-1:0] in1; output [N-1:0] out1; reg [N-1:0] out1; integer i; always @(in1) begin for(i=0;i<N;i=i+1) out1[i] = (in1 == i); endendmodule
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Combination CKT Coding
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Combination CKT Coding
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Combination CKT Coding Example 3-8 Verilog for Reduction XOR Chain
module XOR_reduce (data_in, data_out); parameter N = 5; input [N-1:0] data_in; output data_out; reg data_out; function XOR_reduce_func; input [N-1:0] data; integer I; begin XOR_reduce_func = 0; for (I = N-1; I >= 0; I=I-1) XOR_reduce_func = XOR_reduce_func ^ data[I]; end endfunction always @(data_in) begin data_out <= XOR_reduce_func(data_in); endendmodule
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Combination CKT Coding
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Combination CKT Coding
Verilog for XOR Treemodule XOR_tree(data_in, data_out); parameter N = 5; parameter logN = 3; input[N-1:0] data_in; output data_out; reg data_out; function even; input [31:0] num; begin even = ~num[0]; end endfunction
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Combination CKT Coding Verilog for XOR Treefunction XOR_tree_func;input [N-1:0] data;integer I, J, K, NUM;reg [N-1:0] temp, result;begin temp[N-1:0] = data_in[N-1:0]; NUM = N; for (K=logN-1; K>=0; K=K-1) begin J = (NUM+1)/2; J = J-1; if (even(NUM)) for (I=NUM-1; I>=0; I=I-2) begin result[J] = temp[I] ^ temp[I-1]; J = J-1; end else
begin for (I=NUM-1; I>=1; I=I-2) begin result[J] = temp[I] ^ temp[I-1]; J = J-1; end result[0] = temp[0]; end temp[N-1:0] = result[N-1:0]; NUM = (NUM+1)/2; end XOR_tree_func = result[0]; endendfunctionalways @(data_in)begin data_out <= XOR_tree_func(data_in);endendmodule
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Combination CKT Coding
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Combination CKT Coding Example 4-1 Original Verilog Before Logic Duplication
module BEFORE (ADDRESS, PTR1, PTR2, B, CONTROL, COUNT); input [7:0] PTR1,PTR2; input [15:0] ADDRESS, B; input CONTROL; // CONTROL is late arriving output [15:0] COUNT; parameter [7:0] BASE = 8’b10000000; wire [7:0] PTR, OFFSET; wire [15:0] ADDR; assign PTR = (CONTROL == 1’b1) ? PTR1 : PTR2; assign OFFSET = BASE - PTR; //Could be any function // f(BASE,PTR) assign ADDR = ADDRESS - {8’h00, OFFSET}; assign COUNT = ADDR + B;endmodule
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Combination CKT Coding
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Combination CKT Coding
Example 5-3 Combinational Ripple Carry Adderfunction [7:0] adder;input [7:0] a, b;reg c;integer i;begin c = 0; for (i = 0; i <= 7; i = i + 1) begin adder[i] = a[i] ^ b[i] ^ c; c = a[i] & b[i] | a[i] & c | b[i] & c; endendendfunction
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Combination CKT Coding Example shows how a task statement is used to define an adder function.
module task_example (a,b,c);input [7:0] a,b;output [7:0] c;reg [7:0] c;
task adder;input [7:0] a,b;output [7:0] adder;reg c;integer i;begin c = 0; for (i = 0; i <= 7; i = i+1) begin adder[i] = a[i] ^ b[i] ^ c; c = (a[i] & b[i]) | (a[i] & c) | (b[i] & c); endendendtask
alwaysadder (a,b,c); //c is a regendmodule
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Sequential CKT Coding
Verilog Showing Unintentional Latch Inferencealways @(cond_1)begin if (cond_1) data_out <= data_in;end
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Sequential CKT Coding : in out declaration
module UP_COUNTER (clock,reset,value_now);input clock,reset;output [7:0]value_now;
reg [7:0]value_now; // Q value for filp-flops……endmodule
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Sequential CKT Coding : combinational ckt
wire [7:0]value_now_d; // D values for flip-flopsassign value_now_d=reset?8'b0:(value_now+1'b1);
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Sequential CKT Coding : sequential ckt
A edge triggered always block will infer real flip-flops
always@(posedge clock)begin
value_now<= value_now_d;end
Above statement will use 8 flip-flops
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Sequential CKT Coding
Example 5-11 RTL Nonblocking Assignmentsmodule rtl (clk, data, regc, regd);input data, clk;output regc, regd;reg regc, regd;always @(posedge clk)begin
regc <= data;regd <= regc;
endendmodule
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Sequential CKT Coding
Example 5-12 Blocking Assignmentmodule rtl (clk, data, rega, regb);input data, clk;output rega, regb;reg rega, regb;always @(posedge clk)begin
rega = data;regb = rega;
endendmodule
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Sequential CKT Coding
Latch Inference Using an if Statementalways @ (DATA or GATE) begin
if (GATE) beginQ = DATA;
endend
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Sequential CKT Coding
Avoiding Latch Inferencealways @ (DATA, GATE) begin Q = 0; if (GATE) Q = DATA;end
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Sequential CKT Coding: Verification
How can we ensure our design is right?
UP_COUNTER
Test bench(a test machine)
Real design
A special Verilogmodule to test the design
Give inputs Observe outputs
Do the responses right?
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Sequential CKT Coding: test-bench
`timescale 1ns/1ps
module test_up_counter; // test bench module
reg clock,reset,max,freeze,pre_load;reg [7:0]pre_load_val;wire [7:0]value_now;
UP_COUNTER MY_COUNTER(clock,reset, value_now);
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Sequential CKT Coding: test-bench
initialbegin
clock=1; reset=1; #81reset=0;
end
always #10 clock=~clock;
always@(posedge clock)begin
#5$display("Present valur of the up counter=%d",value_now);
end
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Sequential CKT Coding: outputs/responses
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Sequential CKT Coding: synthesis
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Sequential CKT Coding
Example 6-14 D Latch With Asynchronous Resetmodule d_latch_async_reset (RESET, GATE, DATA, Q);input RESET, GATE, DATA;output Q;reg Q;//synopsys async_set_reset "RESET"always @ (RESET or GATE or DATA) if (~RESET) Q = 1’b0; else if (GATE) Q = DATA;endmodule
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Sequential CKT Coding
Positive-Edge-Triggered D Flip-Flopmodule mslatch (SCK, MCK, DATA, Q);input SCK, MCK, DATA;output Q;reg Q;always @ (posedge SCK) Q <= DATA;endmodule
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Sequential CKT Coding
Negative-Edge-Triggered D Flip-Flopmodule dff_neg (DATA, CLK, Q);input DATA, CLK;output Q;reg Q;always @(negedge CLK) Q <= DATA;endmodule
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Sequential CKT Coding
D Flip-Flop With Synchronous Resetmodule dff_sync_reset (DATA, CLK, RESET, Q);input DATA, CLK, RESET;output Q;reg Q;//synopsys sync_set_reset "RESET"always @(posedge CLK)if (~RESET) Q <= 1’b0;else Q <= DATA;endmodule
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Sequential CKT Coding
Example 6-27 D Flip-Flop With Asynchronous Setmodule dff_async_set (DATA, CLK, SET, Q);input DATA, CLK, SET;output Q;reg Q;always @(posedge CLK or negedge SET) if (~SET) Q <= 1’b1; else Q <= DATA;endmodule
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Sequential CKT Coding
Drink Machine—State Machine VersionThe design is a vending control unit for a soft dri
nk vending machine. The circuit reads signals from a coin-input unit a
nd sends outputs to a change-dispensing unit and a drink-dispensing unit.
Input signals from the coin-input unit are nickel_in (nickel deposited), dime_in (dime deposited), and quarter_in (quarter deposited).
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Sequential CKT Coding
Drink Machine—State Machine Version
Outputs to the vending control unit are collect (collect coins), to the coin-input unit; nickel_out (nickel change) and dime_out (dime change), to the change-dispensing unit; and dispense (dispense drink), to the drink-dispensing unit.
The price of a drink is 35 cents.
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Sequential CKT Coding
Drink Machine—State Machine Version‘define vend_a_drink {D,dispense,collect} = {IDLE,2’b11}module drink_machine(nickel_in, dime_in, quarter_in,collect, nickel_out, dime_out,dispense, reset, clk) ; parameter IDLE=0,FIVE=1,TEN=2,TWENTY_FIVE=3, FIFTEEN=4,THIRTY=5,TWENTY=6,OWE_DIME=7; input nickel_in, dime_in, quarter_in, reset, clk; output collect, nickel_out, dime_out, dispense; reg collect, nickel_out, dime_out, dispense; reg [2:0] D, Q; /* state */ // synopsys state_vector Q
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Sequential CKT Codingalways @ ( nickel_in or dime_in or quarter_in or reset )begin nickel_out = 0; dime_out = 0; dispense = 0; collect = 0; if ( reset ) D = IDLE; else begin D = Q; case ( Q ) IDLE: if (nickel_in) D = FIVE; else if (dime_in) D = TEN; else if (quarter_in) D = TWENTY_FIVE;
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Sequential CKT CodingFIVE: if(nickel_in) D = TEN; else if (dime_in) D = FIFTEEN; else if (quarter_in) D = THIRTY;TEN: if (nickel_in) D = FIFTEEN; else if (dime_in) D = TWENTY; else if (quarter_in) ‘vend_a_drink;TWENTY_FIVE: if( nickel_in) D = THIRTY; else if (dime_in) ‘vend_a_drink; else if (quarter_in) begin ‘vend_a_drink; nickel_out = 1; dime_out = 1; end
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Sequential CKT CodingFIFTEEN: if (nickel_in) D = TWENTY; else if (dime_in) D = TWENTY_FIVE; else if (quarter_in) begin ‘vend_a_drink; nickel_out = 1; endTHIRTY: if (nickel_in) ‘vend_a_drink; else if (dime_in) begin ‘vend_a_drink; nickel_out = 1; end else if (quarter_in) begin ‘vend_a_drink; dime_out = 1; D = OWE_DIME; end
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Sequential CKT CodingTWENTY: if (nickel_in) D = TWENTY_FIVE; else if (dime_in) D = THIRTY; else if (quarter_in) begin ‘vend_a_drink; dime_out = 1; end OWE_DIME: begin dime_out = 1; D = IDLE; end endcase endendalways @ (posedge clk ) begin Q = D;endendmodule
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Sequential CKT CodingSchematic
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Sequential CKT Coding
FSM