Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.
-
Upload
claud-harvey -
Category
Documents
-
view
230 -
download
5
Transcript of Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.
![Page 1: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/1.jpg)
Verilog Basics
Nattha JindapetchNovember 2008
![Page 2: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/2.jpg)
Agenda
Logic design review Verilog HDL basics LABs
![Page 3: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/3.jpg)
Logic Design Review
![Page 4: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/4.jpg)
Basic Logic gates
![Page 5: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/5.jpg)
Additional Logic Gates
![Page 6: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/6.jpg)
Two Types Combinational circuit
No "memory" Its output depends only upon the current
state of its inputs. Sequential circuit
Contains memory elements Its output depends not only upon the
current state of its inputs, but also on the current state of the circuit itself.
Two Styles: Synchronous and Asynchronous
![Page 7: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/7.jpg)
Combinational Circuits: examples
Multiplexers 2n x 1 multiplexer receives 2n input bits and n
selector bits, and outputs exactly one of the input bits, determined by the pattern of the selector bits.
![Page 8: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/8.jpg)
Combinational Circuits: examples
Demultiplexers 1 x 2n DMUX is the
inverse of MUX It takes 1 input and
transmits that input on exactly one of its outputs, determined by the pattern of its n selector bits.
![Page 9: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/9.jpg)
Combinational Circuits: examples
Encoders 2n x n encoder takes
2n inputs and sets each of its n outputs, based upon the pattern of its inputs.
an encoder is the inverse of a decoder.
![Page 10: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/10.jpg)
Combinational Circuits: examples
Decoders An n x 2n
decoder takes n inputs and sets exactly one of its 2n outputs, based upon the pattern of its inputs.
![Page 11: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/11.jpg)
Sequential Circuits Circuits with feedback
Cross-coupled NOR gates
R S Q Q’
0 0 No change
1 0 0 1 Reset
0 1
1 0 Set
1 1 Not allowed
R
S
Q
Q'
![Page 12: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/12.jpg)
Sequential Elements
Latches vs Flip-Flops Latches work on Level-sensitive Flip-Flops work on Edge-
triggered RS, JK, D, T
S R Q Q’
0 0 No change
0 1 0 1 Reset
1 0
1 0 Set
1 1 Not allowed
J K Q Q’
0 0 No change
0 1 0 1
1 0
1 0
1 1 Toggle
D Q
0 0
1 1
T Q
0 1
1 0
![Page 13: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/13.jpg)
Counters
Synchronous counter Clock of synchronous cou
nter are same clock. Asynchronous counter
Clock of second flip-flop is Q of first flip-flop.
The clock of asynchronous counter are different source.
![Page 14: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/14.jpg)
Registers
A register is used for storing several bits of digital data.
It basically consists of a set of flip-flops. each flip-flop representing one bit of the register. Thus, an n-bit register has n flip-flops.
A Simple Shift Register Consisting of D-type Flip-flops
![Page 15: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/15.jpg)
Verilog HDL basics
![Page 16: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/16.jpg)
HDL (Hardware Description Language)
Big picture: Two main HDLs out there VHDL
Designed by committee on request of the Department of Defense
Based on Ada Verilog HDL
Designed by a company for their own use Based on C
Both now have IEEE standards Both are in wide use
![Page 17: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/17.jpg)
Verilog Description Styles
Verilog supports a variety of descriptio n styles
Structural explicit structure of the circuit e.g., each logic gate instantiated and connecte
d to others Behavioral
program describes input/output behavior of circuits
Mixed
![Page 18: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/18.jpg)
Verilog Module
module module-name (list-of-port); input/output declarations local net declarations
parallel statements endmodule
![Page 19: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/19.jpg)
Structural Module: example1
module half_adder (s, a, b, co);inputa, b;output s, co;
wire w0, w1, w2; assign w0 = a & b,
w1 = ~w0,w2 = a | b,s = w1 & w2,co = w0;
endmodule
a
b w0w1
w2
co
s
a b s co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 1 1
![Page 20: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/20.jpg)
HAa
b
i0co
s
HAa
b
i1co
s
w0
ci
a
b
w1
w2
s
co
Structural Module: example1
module full_adder (s, a, b, co, ci);inputa, b, ci;output s, co;
wire w0, w1, w2; assign co = w1 | w2;half_adder i0
(.co(w1), .s(w0), .a(a), .b(b));half_adder i1
(.co(w2), .s(s), .a(w0), .b(ci));endmodule
![Page 21: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/21.jpg)
Structural Module: example1
module adder4 (s, a, b, co, ci);input [3:0] a, b;input ci;output [3:0] s, output co;
wire w0, w1, w2; full_adder i0
(.co(w0), .s(s[0]), .a(a[0]), .b(b[0]), .ci(ci));full_adder i1
(.co(w1), .s(s[1]), .a(a[1]), .b(b[1]), .ci(w0));full_adder i2
(.co(w2), .s(s[2]), .a(a[2]), .b(b[2]), .ci(w1));full_adder i3(.co(co), .s(s[3]), .a(a[3]), .b(b[3]), .ci(w2));
endmodule
FAa
b
i0
co
sci
FAa
b
i1
co
sci
FAa
b
i2
co
sci
FAa
b
i3
co
sci
w0
w1
w2
ci
a[0]
b[0]
a[1]
b[1]
a[2]
b[2]
a[3]
b[3]
s[0]
s[2]
s[1]
s[3]
co
![Page 22: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/22.jpg)
Behavioral Module: example1module adder4 (s, a, b, co, ci);
input [3:0] a, b;input ci;output [3:0] s, output co;
reg [3:0] s;reg co;
always @(a or b or ci) {co, s} = a + b + ci;
endmodule
![Page 23: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/23.jpg)
Verilog Data Types
Possible Values: 0 0: logic , false 1 1: logic , true X : unknown logic value Z H HHH HH HHHHHHH HHHHH:
Registers and Nets (wires) are the main dat a types
Integer, time, and real are used in behavior al modeling, and in simulation
HHHH HHHH HHHH are not synt hesi zed !
![Page 24: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/24.jpg)
Verilog Registers
Abstract model of a data storage element
A reg holds its value from one assignme nt to the next
The value “sticks” Register type declarations
reg a; // a scalar register reg [3:0] b; // a 4-bit vector register
![Page 25: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/25.jpg)
Verilog Nets
Nets (wires ) model physical connections
They don’t hold their value They must be driven by a “driver” (i .e. a
gate output o r a continuous assignment) Their value is Z if not driven
Wire declarations wire d; // a scalar wire wire [3:0] e; // a 4- bit vector wire
![Page 26: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/26.jpg)
Verilog Parameters
Used to define constantsparameter size = 16, value 8= ;wire - [ 1:0] ; // defines a 15:0 bus
![Page 27: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/27.jpg)
Verilog Operators
Arithmetic operators: +, -, *, /, % Logical operators: &&, ||, ! Bitwise operators: &, |, ~, ^, ^~ Equality operators: ==, !=, Relational operators: >, <, >=, <= Reduction operators: &, ~&, |, ~|, ^ Shift operators: >>, << Conditional: ?:
![Page 28: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/28.jpg)
Example2: 4:1 multiplexer
module mux4 (s, d, z); //bitwise operators
input [1:0] s;input [3:0] d;output z;assign z =(~s[1] & ~s[0] & d[0]) |
(~s[1] & s[0] & d[1]) | ( s[1] & ~s[0] & d[2]) | ( s[1] & s[0] & d[3]) ;
endmodule
![Page 29: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/29.jpg)
Example2: 4:1 multiplexer
module mux4 (s, d, z); //using conditional operatorsinput [1:0] s;input [3:0] d;output z;assign z = s[1] ? (s[0] ? d[3] : d[2]) : (s[0] ? d[1] : d[0]);endmodule
![Page 30: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/30.jpg)
Verilog Assignments
Two types: Continuous Assignments
assign values to nets This means combinational logic
Procedural Assignments assign values to registers Only allowed inside procedural blocks
(initial and always)
![Page 31: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/31.jpg)
Continuous Assignments
Models combinational logic using a logical expression instead of gates
Assignment is evaluated whenever any signal changes
wire a, b, out; assign out = ~(a & b);
wire [15:0] sum, a, b;wire cin, cout;assign {cout,sum} = a + b + cin;
![Page 32: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/32.jpg)
Procedural Assignments
Assigns values to register types They do not have a duration
The register holds the value until the next procedural assignment to that variable
They occur only within procedural blocks initial and always
They are triggered when the flow of execution reaches them
![Page 33: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/33.jpg)
always Blocks When is an always block executed?
always Starts at time 0
always @(a or b or c) Whenever there is a change on a, b, or c Used to describe combinational logic
always @(posedge foo) Whenever foo goes from low to high Used to describe sequential logic
always @(negedge bar) Whenever bar goes from high to low
![Page 34: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/34.jpg)
Inside always blocks
Procedural assignments if statements case statements for, while, forever statements wait statements
![Page 35: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/35.jpg)
Blocking vs Non-blocking
![Page 36: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/36.jpg)
Blocking vs Non-blocking
beginq1 =
x1;q2 =
q1;z1 =
q2;end
Blocking
beginq1 <=
x1;q2 <=
q1;z1 <=
q2;end
Non-Blocking
![Page 37: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/37.jpg)
Quick Review
Continuous assignments to wires assign variable = exp; Result in combinational logic
Procedural assignment to regs Always inside procedural blocks (always blocks
in particular for synthesis) blocking
variable = exp; non-blocking
variable <= exp; Can result in combinational or sequential logic
![Page 38: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/38.jpg)
Quick Review
module name (args…);input …; // define inputsoutput …; // define outputs
wire… ; // internal wiresreg …; // internal regs, possibly output
// the parts of the module body are// executed concurrently<continuous assignments><always blocks>
endmodule
![Page 39: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/39.jpg)
comment in Verilog_HDL // Single-line comment /*………….
…………..*/ multiple-line comment
module mux2_1(out,a,b,sel); // port declare. input a,b,sel; output out; wire sel_,a1,b1 /* structural design using logic operator mux2_1 */ not (sel_,sel); and (a1,a,sel),(b1,b,sel); or (out,a1,b1); endmodule;
![Page 40: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/40.jpg)
Naming in Verilog_HDL
ข้�อกำ��หนด ในกำ�รตั้��งชื่��อไฟล์� กำ�รตั้��งชื่��ออ�ปกำรณ์� แล์ะกำ�รเชื่��อมตั้ อ ส�ยส�ญญ�ณ์ จะตั้�องไม เป%นคำ��สงวนข้องภ�ษ� ระหว �งข้�อคำว�ม หร�อตั้�วเล์ข้ ส�ม�รถใชื่� เคำร��องหม�ย _ หร�อ
$ ได� ตั้�วแรกำที่,�ตั้� �งชื่��อตั้�องเป%น ตั้�วอ�กำษร a-z หร�อ A-Z หร�อ _ ตั้�วอ�กำษรตั้�วใหญ แล์ะ ตั้�วเล์-กำ จะม,คำว�มหม�ยแตั้กำตั้ �งกำ�น
![Page 41: Verilog Basics Nattha Jindapetch November 2008. Agenda Logic design review Verilog HDL basics LABs.](https://reader036.fdocuments.in/reader036/viewer/2022062314/56649e245503460f94b13114/html5/thumbnails/41.jpg)
ศึ�กษาเพิ่�มเติม .... Evita_Verilog Teerayod_Verilog_Thai