Digital System Design Verilog: System Tasks and...
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Digital System Design Verilog: System Tasks and Testbench Dr. Bassam Jamil
Transcript of Digital System Design Verilog: System Tasks and...
Digital System Design
Verilog:System Tasks and Testbench
Dr. Bassam Jamil
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Topics
System Tasks and Functions
Testbench Testing and Simulation commands
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System Tasks and Functions
System Task and Functions start with $
Common tasks and functions Display the value of variables File I/O Simulation control : Stop (i.e. suspend) , finish (i.e.
exit) simulation
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Display the value of variables
$monitor ("text_with_format_specifiers", signal, signal, ... ); Continuously monitors the signals listed, and prints the
formatted message whenever one of the signals changes. A newline is automatically added to the text printed.
$display ("text_with_format_specifiers", signal, signal, ... ); Prints the formatted message once when the statement is
executed during simulation. A newline is automatically added to the text printed.
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$display Example
Output of $display task
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More $display Examples
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$monitor Example
$time: returns simulation time
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File I/O
ptr = $fopen("file_name"); A function that opens a file for writing, and returns
a integer pointer to the file.
$fclose (ptr); A function that closes a disk file that was opened
by $fopen.
$monitor (ptr, "text_with_format_specifiers", signal, signal, ... ); Results of $monitor is sent to output file
$display (ptr, "text_with_format_specifiers", signal, signal, ... ); Results of $display is sent to output file
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File I/O
$readmemb("file_name", register_array, start, end) Read file_name and load it into register_array. Data is in binary format
$readmemh("file_name", register_array, start, end); Read file_name and load it into register_array. Data is hex format
$fscanf("file_name", format, arguments)
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File I/O: Generate Output File
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File I/O: Reading From a File
Note: 14410= 1001 0000
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File I/O: VCD Generation
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File I/O: VCD Generation
$dumpfile Sets the VCD file name
$dumpvars Enable dumping all variables in the design
$dumpvars ( level, module) Dump all the vars at level module with depth of level
$dumpon / $dumpoff Enable/disable dumping
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VCD File Example
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Simulation Control
$finish; Finishes a simulation and exits the simulation
process.
$stop; Halts a simulation and enters an interactive debug
mode.
$random (seed); Returns a random 32-bit signed integer.
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Testbench
A testebench is a verilg program to verify a design. It consists of: Stimulus Generators: set the values of the design
inputs Monitors: observe the values of the design output (and
possibly internal nodes) Checkers: verifies the behavior of the design
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Testbench Module: Main Components
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Testbench Example: 4-bit Counter
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Testbench Example: 4-bit Counter
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Testbench Example: 4-bit Counter
endmodule
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Testbench Example: half-adder design
