Uses of Synchronized Clocks in Test and Measurement Systems

CHESS

March 3, 2009

Uses of Synchronized Clocks in Test and Measurement Systems

Jeff Burch, Adam Cataldo, John Eidson, Andrew Fernandez, Conrad Proft, Dieter Vook

Measurement Research Laboratory, Agilent Technologies, Inc.

CHESS

Slide 2 March 3, 2009

Agenda

1. Overview of clock synchronization and driving applications

2. Test & measurement (LXI Class B instrumentation & DAQ)

3. Experimental results

4. Conclusions

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Purpose of IEEE 1588

NETWORK

IEEE 1588 is a protocol designed to synchronize real-time clocks in the nodes of a distributed system that communicate using a network

• It does not say how to use these clocks (this is specified by the respective application areas)

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Coupling IEEE 1588 to your application

IEEE 1588 Clock

Latchtrigger-in

timestampgenerating timestamps

IEEE 1588 Clock

Comparator trigger-out

event time generating events

Latch

IEEE 1588 Clock Synthesizer waveform

generating waveforms

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Synchronization Basics – Delay Request-Response Mechanism

Mastertime

Slavetime

t1

t4

t3

t2

Timestamps knownby slave

t-ms

t-sm

Sync

Follow_Up

Delay_Req

Delay_Resp

t1, t2, t3, t4

t1, t2, t3

t2t1, t2

Grandmaster- M S- BC - M S- OC

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Under the assumption that the link is symmetric

Offset = (Slave time) – (Master time) = [(t2 – t1) – (t4 – t3)]/2 = [(t-ms) – (t-sm)]/2

(propagation time) = [(t2 – t1) + (t4 – t3)]/2 = [(t-ms) + (t-sm)]/2

Can rewrite the offset as

Offset = t2 – t1 – (propagation time) = (t-ms) – (propagation time)

If the link is not symmetric

• The propagation time computed as above is the mean of the master-to-slave and slave-to- master propagation times

• The offset is in error by the difference between the actual master-to-slave and mean propagation times

Synchronization Basics – Delay Request-Response Mechanism - 2

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Synchronization Basics – Peer Delay Mechanism

Mastertime

Slavetime

t1

t4

t3

t2

Timestamps knownby slave

t-ms

t-sm

Sync

Follow_Up

Pdelay_Req

Pdelay_Resp

t3, t4, t5, t6

t3

t2t1, t2

Grandmaster- M S- BC - M S- OC

t5

t6Pdelay_Resp_Follow_Upt6

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IEEE 1588

MASTER SLAVE

T1

T2

T4

T3

Sync

Delay_Req

PHY

MAC

OS

Application Code

IEEE 1588 Code

IEEE 1588 Packet Detection

IEEE 1588 Clock

IEEE 1588 Control

Application IEEE 1588 Timing Support (e.g. time stamping, time triggers…)

MII

LAN

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The residence time is accumulated in a field of the Sync (one-step clock) or Follow_Up (two-step clock) messages

End-to-End Transparent Clocks

Residence time bridgeIngress Egress

- +Ingress timestamp Egress timestamp

++

Message at ingress Message at egress

Preamble

PTP messagepayload

NetworkprotocolheadersCorrection field

Preamble

PTP messagepayload

NetworkprotocolheadersCorrection field

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How well can you synchronize?

SyncE Enabled

Measured Quantity

Mean Standard Deviation

Peak-to-peak

No 10 MHz clock output

-2.148 ns 5.237 ns 48.3 ns

Yes 10 MHz clock output

319 ps 80.6 ps 900 ps

Yes 1 pulse per second output

1.005 ns 2.8 ps 2.02 ns

From: “DP83640 Synchronous Ethernet Mode: Achieving Sub-nanosecond Accuracy in PTP Applications, National Semiconductor Application Note 1730, David Miller,

September 2007

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Infrastructure:

• Boundary and transparent clocks (IEEE 1588 bridges): Hirschmann, Westermo, Cisco, others

• GPS master clocks: Symmetricom, Meinberg, Westermo,…

Silicon: • Microprocessors with embedded 1588: Intel, Hyperstone, Freescale,

AMCC,…

• PHY/MAC level: National Semiconductor, others in proto or 1st silicon (some also implement synchronous Ethernet)

Protocol & misc:

• 1588 stacks, IP blocks, consulting: IXXAT, U. Zurich, MoreThanIP, others

• Wireshark

Products (partial listing)

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WebsitesGeneral IEEE 1588 site: contains product pointers, conference records, general guidance, standards related

http://ieee1588.nist.gov/

ISPCS (International IEEE Symposium on Precision Clock Synchronization) site: Conference on IEEE 1588 and related subjects

http://www.ispcs.org/

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RoboTeam in Action: Process Relative Motion

Courtesy of Kuka Robotics Corp.

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e.g. high speed printing Courtesy of Bosch-Rexroth.

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IEEE 1588 enabled flight test instrumentation in the forward fuselage of a test aircraft. (Data acquisition)

Courtesy of Teletronics

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GE uses 1588 in the Mark™ Vie control system for large generators, turbines, wind farms, and other DCS applications. (>50K I/O Packs with 1588 shipped to date)

http://gepower.com/prod_serv/products/oc/en/control_solution/ppc_markviedcs_cs.htm

Power System Applications (Courtesy of General Electric)



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IEEE Power System Relaying Committee (PSRC) recently approved formation

of Working Group H7 "IEEE 1588 Profile for Protection Applications"

Power System Applications

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Cellular backhaul is the major telecom application to date. Metro-Ethernet in field trial. Femtocells beginning.

Companies involved (partial list):

• Nokia-Siemens, Brilliant, Semtech, Zarlink, …

Telecommunications Applications

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Consumer electronics: IEEE 802.1as

http://www.ieee802.org/1/pages/802.1as.html

The “AVB” effort should be carefully investigated by both PTIDES and PRET.

Audio/video systems applications

http://www.ieee802.org/1/pages/802.1as.html

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LXI Class-C Instrument

LXI Class A&B Instrument Overview

TSTTRXTX

PHYMeas FW Meas HW DUT

LXI Class B Instrument

LAN TCP HTTP

SCPI

App Code

IEEE1588

UDP

P2P

LXI Class B• IEEE1588 Clock Sync• Peer-to-Peer Messages• Event Logs• Downloaded Application Code

LXI Class A Instrument

Trigger Bus

8 LVDS

LXI Class A• Trigger Bus

Event Log

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LXI Class A&B benefits

Class B:

• Increased visibility of system configuration, timing and performance

• Increased visibility for fault diagnosis and trouble shooting

• Ability to precisely time measurement execution and state evolution system-wide

• Increased ability to optimize system performance, e.g. throughput, timing precision

• Increased ability to do cross domain measurement correlations based on precisely time stamped data

Class A:

• Increased traditional triggering flexibility: 8-wide, daisy chain

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DEMO TIME!

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LXI Class B experimental test system

Test system block diagram

Experiments:

1. Frequency response

2. Fault shutdown

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LXI Class B experimental test system

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PC Paced Instrument Sequencing-frequency response

*TRG; *OPC?

DONE

HW Trigger

HW Trigger*TRG; *OPC?

DONE

http://h10010.www1.hp.com/wwpc/us/en/sm/WF25a/321957-321957-64295-321838-3329741-1839859.html

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Instrument Sequencing by PC (Baseline)

Irregular signal timing due to timing jitter in PC

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Peer-to-Peer Instrument Sequencing

MEASURE

STEP

COMPLETE

STEP

MEASURE


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Instrument Sequencing by P2P Messages

More regular signal timing

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LXI Class B: Time-Triggered Instrument Sequencing

COMPLETE

TTTT

TT

TT

TT

TT

TT

TT

Time overlap


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Instrument Sequencing by Time-Triggers

Shorter interval due to overlap

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Sequencing to measure frequency response

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Power Supply Shutdown

TS

FAULTPOLL

FAULT

SHUTDOWN

SHUTDOWNTT = TS + Δ2TT = TS + Δ1

SHUTDOWN

TSFAULT

SHUTDOWNSHUTDOWN

PC Polled

P2P Timed

P2P Immediate


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PC polled

TT-Fault FET

PS-Volt

FG-out

DMM-off

1. Short PS load

2. PS shuts off

3. Turn off FG

4. Turn off DMM

Asynchronous Fault

Protect

Shutdown

Shutdown

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Time-Triggered Emergency Shutdown

Asynchronous Fault

Protect

Shutdown

Shutdown

Δ1

Δ2

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Power Shutdown performance

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Power Shutdown Event Log-based Analysis

PS

Common Time Scale

FGEN

DMM

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Conclusions: Benefits of Class A & B:

• Increased visibility of system configuration, timing and performance

• Increased visibility for fault diagnosis and trouble shooting

• Ability to precisely time measurement execution and state evolution system-wide

• Increased ability to optimize system performance, e.g. throughput, timing precision

• Increased ability to do cross domain measurement correlations based on precisely time stamped data

• Increased traditional triggering flexibility: 8-wide, daisy chain

Performance measurements illustrate these benefits.

Uses of Synchronized Clocks in Test and Measurement Systems

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