Upgrading the CDF Track Trigger to 3-D for High Instantaneous Luminosity

11 Feb 2005; p.1Cornell JC : CDF XFT Upgrade

Ben Kilminster

Upgrading the CDF Track Trigger to 3-D3-D for High Instantaneous

Luminosity

Ben KilminsterOhio State UniversityCDF Collaboration L = 1x1032

cm-2s-1 Last week !

Project includes physicists and engineers from: Ohio State, Baylor, Fermilab, Illinois, Purdue, UC Davis


Ben Kilminster

CDF Central Outer Tracker (COT)

8 “superlayers” of cells 4 with axial wires: r - measurement 4 with stereo wires: z measurement

Each cell 0.88 cm drift (avg.) Max drift time ~220 ns 12 sense wires/cell: 96 measurements 2540 cells, 30240 channels


Ben Kilminster

Detector Elements

CAL COT MUON SVX CES

XFT MuonPrim XCES

XTRP

CAL Track Muon

CAL SVT

Global Level 1

Global Level 2 TSI/Clock

eXtremely Fast Tracker = Level 1 Track Trigger

Role of tracking Top, W/Z, Exotic Physics triggers

require High momentum electron and muon Level 1 trigger candidates

Bottom Physics require low momentum tracking at the Level 1 trigger

electrons muons hadronic tracks

L1 Trigger Primitives Electrons: XFT track + EM cluster Muons: XFT track + muon stub

L2 Trigger Tracks XFT Track + Silicon Hits

CDF Trigger System


Ben Kilminster

Overview of Existing XFT

Hit Finding: Mezzanine Card Hits are classified as prompt

or delayed (i.e. “2-bin”) Segment Finding

In the axial layers patterns of wires within one

superlayer Track Finding

Looking across 3 or 4 axial layers, search for patterns of segments consistent with Pt>1.5 GeV/c

Good hit patterns are identified as segment, then segments are linked as tracks

Tracks only found in 2-Dimensions (r,)


Ben Kilminster

The Hit and Segment Finders

Hits : 2 bins - Prompt or delayedMask : A specific pattern of prompt and delayed hits on the 12 wires of an axial COT layer generated by simulating tracksPixel: represents the phi position of the track at the midpoint of the cell.

Track segments are found by comparing hit patterns in a given layer to a list of valid patterns or “masks”.

“Delayed” hit

“Prompt” hit

Layer Cells Masks Pixels

1 192 2304 166

2 288 3456 227

3 384 2304 292

4 480 2880 345


Ben Kilminster

Segment Finder Output In the inner two layers, each

mask corresponds to 1 of 12 pixel positions in the middle of the layer.

The pixel represents the phi position of the track.

In the outer 2 layers, each mask corresponds to 1 of 6 pixel positions and 1 of 3 slopes: (low pt +, low pt -, high pt).

When a mask is located, the corresponding pixel is turned on.


Ben Kilminster

The Segment Linker

Slopes must match

Pixels mustmatch

Tracks are found by comparing fired pixels in all 4 layers to a list of valid pixel patterns or “roads”.

• Chamber is divided into 288 1.25–degree “identical” Linkers

•Highest track reported for each linker •-> Max of 288 tracks per event

• Each linker uses a look-up table of ~1200 roads


Ben Kilminster

XFT System Electronics

Mezzanine Cards 168 cards Classifies hits as prompt/delayed

Final Finder system 24 SL1-3 boards 24 SL2-4 boards Heavy reliance on PLDs

Allows for some redesign: new patterns for number of misses, wire sag, faster gas, etc

Final Linker System 24 Linker boards Heavy reliance on PLDs

Allows for new road set based on new beam positions

Have already developed 2 new roads sets due to accelerator changes.


Ben Kilminster

XFT Performance in CDF RunII

Performance of the XFT in CDF’s RunII has been excellent1. Momentum resolution 1.74%/GeV/c2. Phi Resolution < 6mRad3. Efficiency ~ 95% (almost 100% for high Pt tracks)


Ben Kilminster

Why an Upgrade? The XFT was designed for a luminosity

of: L=1x1032cm-2s-1 with 396 nsec

bunch crossings <int/crossing> ~ 3

Then it was supposed to switch to : L=2x1032cm-2s-1 132nsec bunch

<int/crossing> ~ 2 But 132ns was not feasible

Accelerator Performance Max luminosity attained: 1x1032cm-

2s-1 Expect to reach L=3x1032cm-2s-1 at

396nsec bunch crossing <int/crossing> ~ 9 Factor of 3-4 above design

Design @ 132 ns

Design @ 396 ns


Ben Kilminster

Z ee at low lum.0 add. Int./crossing


Ben Kilminster



Ben Kilminster

Two-Track Triggers Two Track Trigger for B

Physics 2 tracks pT>2.5 GeV Opposite charge pT(1)+ pT(2)>6.5 GeV < 135

Quadratic growth (overlaps + fakes)

(L=5E31)/(L =0)=1.5 Extrapolate:

linear(L=1.5E32) = 225b 34kHz

Real (from overlapped MB) (L=1.5E32) = 500b 75kHz

100b

160b

We are stuck with FIXED Bandwidth (Accept Rate):

L1: 30 kHz L2: 1 kHz L3: 100 Hz

Run II Data


Ben Kilminster

What’s needed: Primary problem is the growth of fake tracks due to pattern

recognition problems:

Need a way to model the highest luminosity running Simulations of the XFT System Study the effect of high luminosity running on a variety of triggers

Two-Track Trigger (low PT) Single Track Trigger (high PT: Track Only) Electron Trigger (Track + Other object)

Consider modifications/additions to the current system Reduce fake rate Maintain resolution

fakeFake tracks can be made from pieces of different real physical tracks.

Trigger Rate is the “Figure of Merit”


Ben Kilminster

XFT Simulation of High Lum. All events are passed through a

hit-level simulation Start with COT hits Gives exactly the same answer

as hardware when run with same masks, roads and XFT hits

Outputs XFT hits, pixels, and tracks for axial and XFT pixels for stereo

Simulate High luminosity by Merging events “main” event with zero bias Merge COT hits (combine

overlapping hits) simulate XFT with various options

Add tracks from individual events together

Offline tracks serve as “truth” for the event

This method allows us to probe up to 4E32


Ben Kilminster

Upgrade Strategy

Current XFT uses 4 axial layers only

Upgrade adds 3 stereo layers. Use full 396ns between crossings to send more precise hit information.

Studied various upgrade paths Replacing Axial System (Use additional

264ns between crossings) Add information from Stereo Layers of

COT Replace linker with finer segment

linking Doing some of the above

Advantages of Stereo Upgrade Gives us the fake track rejection we

need. Allows for more additional handles in

trigger Track pointing to muon stubs & calor

(L2) Possibility of Two-Track Invariant Mass

Cuts (Understudy) Parallel Path to Axial System

Commission parasitically.

Only Minor changes to Axial System Slight Changes to existing firmware. KEEP A WORKING SYSTEM

No extended downtime

We picked this.

Stereo layers


Ben Kilminster

Impact of Stereo The stereo can have an impact

in two ways: Confirmation Segment: Since

often fake XFT tracks are the result of linking two unrelated low Pt segments, requiring another high Pt stereo segment in the allowed window around an axial track can be very powerful.

We will use this at Level 1 Provide Z-pointing to tracks:

Since EM and muon calorimeters are segmented in Z, coarse pointing can be very helpful in eliminating fakes

We can use this effectively at Level 2

one stereo layer rejection


Ben Kilminster

Stereo association studies

Reals

Fakes

SL5

SL6

SL7

Expected pixel position (z = 0)

pixel (SL7)Displacement from stereo angle

Measured pixel position (z 0)

SL5 has opposite displacement from SL7

pixel (SL5)

SL3

SL4

pixel (SL3)Displacement from stereo angle

Measured pixel position (z 0)

Pixel displacement is a measure of eta of track


Ben Kilminster

Overview of Upgrade Hit Stage

Provide 6 times bins per wire per bunch crossing instead of the present 2 for stereo layers

maintain existing 2-bin system for axial layers Pass stereo hit information to Finders via optical cable

maintain existing Ansley cables for axial layers Segment Finding Stage

Using 6 times bins, measure phi (pixel) position and slope of segments in 3 outer stereo layers

maintain existing axial segment finding system Axial Segment Linking stage

maintain existing axial track finding system Add new Stereo Linker Association Stage

Associate existing axial tracks from the axial system with stereo segments to reduce number of fake track


Ben Kilminster

Current XFT ConfigurationAnsley trigger cable (220 ft)Data @45MHz LVDS

168 TDCfrom COT

axial layers

24 crates

24+24Axial

Finders

3 crates 3 crates

XTC

~2 m copper Cable Data @33MHz (channel link)

~10 m of cable to XTRP

24Linkers

24LinkerOutput

Modules

Neighboring cards connected over backplane


Ben Kilminster

XFT Upgrade ConfigurationAnsley trigger cable (220 ft)Data @45MHz LVDS

168 TDCfrom COT

axial layers

24 crates

24+24Axial

Finders

3 crates 3 crates

~2 m copper Cable Data @33MHz (channel link)

~10 m of cable to XTRP

24Linkers

12+12+12StereoFinders

24SLAMs

2 crates

~3m optical Cable @60.6MHz

Neighboring cards connected over backplane

126 TDC from COT

stereo layers

New cable (~150ft) Optical Data ~45MHz

Data to L2

SLAMs replace Linker Output Modules

2 bin XTC

6 bin XTC 2


Ben Kilminster

Timing is Tight !


Ben Kilminster

XTC 2 :Measured start/stop time for each windowConsistent with 3ns timing resolution

Getting TDC data to XFT

COT data split into two paths: trigger and data

Trigger info is put into 6 time bins by the new XTC2 mezzanine card

Data driven to Stereo Finders by optical fiber link from optical transmitter card to optical receiver card

XTCXTCXTCXTC2

TDC

Tx

Rx

XFT StereoFinder

~150 ftOptical fiber

CO

T

Rx card on Finder:Receives optical dataTests show good performance

Rx


Ben Kilminster

Improving the Hit Binning Algorithm

Change binning of hits 6 Bins Maximized time window intervals to

avoid some bins being under-utilized Better fake rejection than trivial

binning: 20%

“Not sure” window Most hits fire two time bins <pulse width>~40ns Bin width: 24ns If hit exists in previous bin, ignore

hits at beginning of bin (“not sure window”)

Both improvements give an additional ~40% fake rejection compared to no “not-sure” window 24ns

Not sureWindow

18ns Time

Bin N Bin N+1

ASDQThreshold


Ben Kilminster

Improving Segment Finding Patterns

New Finder Chips Driving factor in chip

choice 7 times more “masks”

== unique segment patterns from track simulation

Segment Finder Chips

2 Time Bins, masks

6 Time Bins, Masks

Finder Axial SL1 166 1344




Segment Finder Chips

Implementation Logic Elements Used

Speed

Stereo Layer 46 bins

Flex 10K50 2,500 / 2,88087% used

16.5 ns

Axial Layer 42 bins

Stratix 2S60 10,602 / 48,35222% used

33 ns


Ben Kilminster

Output Stereo-confirmed Tracks

A look at the SLAM Board(OSU responsibility)

Optical IO

VME Interface

(Control Code, and State machine interface)

SLAM Chip

Clock Gen/Dist

Design Storage

Linker Input

TracksStereo Finder Segments


Ben Kilminster

Impact on A Specific Trigger

Scenario C Two-Track Trigger

Lumi[1E32 cm-2s-1] 0.5 1.0 1.5 2.0 3.0

2-Bin [mb] 0.12 0.28 0.50 0.78 1.5

Using 6-Bin Stereo [mb]

0.08 0.13 0.21 0.33 0.65

Ratio 0.37 0.38 0.39 0.40 0.42

Luminosity

Uses only 2 of 3 Stereo Layers 3x1032 cm-2s-1


Ben Kilminster

Conclusions Accelerator performance has been excellent

But…high luminosity at 396nsec bunch spacing leads to many interactions/crossing

We need to upgrade the XFT to take advantage of the great opportunity The XFT Upgrade will meet the needs of high L running

This upgrade gives us the required factor of 3 rejection of fakes System can be installed and commissioned with little impact on the current XFT Not all capabilities have been explored

Current rejection only making use of 2 of 3 stereo layers. Expect another factor of ~2 by using stereo extrapolation in Level 2 Mass triggers are also possible at Level 1 and/or Level 2

Schedule: Prototypes under design.

Make extensive use of experience from existing system. Expect completed system in ~15 months System Operational by Jan 2006.


Ben Kilminster

BACKUPS


Ben Kilminster

XFT Data Path

TDC Transition module Timing and multiplexing

Fiber optic transmit board Use on: TDC TM, SLAM interface

Fiber optic receiver board Use on: Finder, L2 Pulsar

Prototypes built and tested Look good. Investigating higher data rates Production runs will await vertical

slice test.

Optical data

Electrical data


Ben Kilminster

Fibers Used in the XFT Upgrade

Fibers from XTC to Finder 200ft + 2ft breakout each end Total installation: 38 bundles

of 4 fibers + 36 bundles of 6 fibers

Pulling fibers expected to take ~7 days

Will need fibers pulled for commissioning transition boards


Ben Kilminster

XFT Stereo Finder Board

RX Mezzanine

RX Mezzanine

RX Mezzanine

TX Mezzanine

FinderA

(8 cell)

FinderB

FinderC

FinderD

FinderE

VMEbusSlave &Control

Pixel and Slope Output to the SLAM

Pixel and Slope Output to the L2

18

1818

18

18

1818

18

18

1818

4 x 18

FPGADownload

FPGADownload

FPGADownload

FPGADownload

FPGADownload

FPGADownload

PixelDriver

10 x 15

PulsarDriver

5 x 32

1 x 18

FPGADownload

Fiber 1

Fiber 2

Fiber 3

Fiber 4

Fiber 5

Fiber 6

Fiber 7

Fiber 8

Fiber 9

Fiber 10

Fiber 11

Fiber 12

1

23

4

5

67

8

9

1011


Ben Kilminster

Firmware Progress

Stereo Chip Compilation ; Family ; Stratix II ; Device ; EP2S60F484C3 ; Timing Models ; Preliminary ; Total ALUTs ; 10,602 / 48,352 ( 21 % ) ; Total pins ; 150 / 335 ( 44 % ) ; Total memory bits ; 33,088 / 2,544,192 ( 1 % ) ; DSP block ; 0 / 288 ( 0 % ) ; Total PLLs ; 0 / 6 ( 0 % ) ; Total DLLs ; 0 / 2 ( 0 % )

SLAM Chip Compilation ; Family ; Stratix ; Device ; EP1S40F1020C5 ; Timing Models ; Production ; Total logic elements ; 25,081 / 41,250 ( 60 % ) ; Total pins ; 341 / 782 ( 43 % ) ; Total memory bits ; 6,912 / 3,423,744 ( < 1 % ) ; DSP block ; 0 / 112 ( 0 % ) ; Total PLLs ; 1 / 12 ( 8 % ) ; Total DLLs ; 0 / 2 ( 0 % )

Quartus II Version

4.1 Build 181 06/29/2004

SJ Full Version

The Stereo Finder and SLAM designs make extensive use of reprogrammable devices. Major progress in firmware over the last 6 months Functional designs have been implemented Timing has been studied


Ben Kilminster

The Axial Finder Chip

140 inputs Maskfinding

Dead COTwire list L1 and L2 storage

Pixel Output

Axial Finder: implemented using Altera FLEX 10K70 chip.Stereo Finder: Altera Stratix EP2S60 chip


Ben Kilminster

InputAlingment3-FIFOS

Wire DataStorage

Registers

8 to 1Multiplexer

Pixel MASKSet

T=5 Clock Ticks T=24 Clock Ticks T=1 Clock Ticks T=3 Clock Ticks

A

B

C

A

B

C

Cell 3

Cell 2

Cell 1

Cell 0

Cell 431

Cell 430

Cell 429

Cell 428

Cell 427

Cell 426

16 bits

16 bits

16 bits

72 bits

72 bits

133 bits

16 bits

16 bits

16 bits

12 Pixelsto Pixel

Chip

WireData

6 timeBins

1 Clock Ticks= 16.5ns

Finder CHIP BLOCK

Pulsar MASKSet

96 Bit FIFO8 slices deep

3 to 1 mux

32 Pixelsto Pulsar

Chip96 bits 96 bits133 bits

T=3 Clock Ticks T=2 Clock Ticks T=1 Clock Ticks

+ 7 Clock Ticks to process all 8 cells

+ 23 Clock Ticks to process all 8 cells

Dead Wire Reg.

L2 Buffers(4)VME

VME

Cell 425

Cell 424

Stereo Finder Chip

Aligns data from 3 TDC moduleswrt 16.5 ns clock

To register 6 time binsfor 12 cells, requires 24 time slices

Data multiplexed toprovide 133 bits of information for segmentfinding in one core cell

For each of 8 core cells, finder algorithm is runproducing 12 pixels of phi and/or slope output toSLAM module

concentration on path to SLAM


Ben Kilminster

Pixel Driver Chip

3-FIFOS

A

B

C

A

B12 bits

12 bits

12 bits

3-FIFOS

C

D

E

A

B

C

12 bits

12 bits

12 bits

C3 to 1

Multiplexer

3 to 1Multiplexer

Channel Ato SLAM

Channel Bto SLAM

Controller - State Machine

Pixel Driver BLOCK

T=2 Clock Ticks T=1 Clock Ticks+

Channel A & BControl

Total time = 2 clock ticks for FIFO(in and out) and 18clock ticks to send the 18 Slices of Pixel Data

FromFinderChips

DataVaildfrom

FinderChips

5

12 bits

12 bits

12 bits

12 bits

12 bits

12 bits

12 bits

12 bitsPixels from 5 Finder Chips sent through two paths to SLAM

Pixel Data from 3 Finder Chips(18 core cells) are accumulatedin each FIFO

Pixel Data sent to SLAM in two 15°slices containing 18 core cells of pixelsfor association to axial tracks


Ben Kilminster

L2 Output Chipdemonstration of something

which works - can be optimized

5-FIFOS

A

B

C

32 bits

32 bits

32 bits

D

E32 bits

32 bits

5 to 1Multiplexer

To Backplane& Auxillary

MezzzanineBoard

Controller - State Machine

Pulsar CHIP BLOCK

T=2 Clock Ticks T=1 Clock Ticks+

A

B

C

32 bits

32 bits

32 bits

D

E32 bits

32 bits

2 to 1Multiplexer

16 bits

16 bits

32 bits 16 bits

FromFINDERCHIPs

T=1 Clock Ticks

ControlL1 Accept

+

Total time to send data on a L1 Accept = (96 bits/cell * 8 cells/Finder * 4.5 Finders / 16 bits) * 16.5ns = 3.564us

• 32 bits of Pixel data is stored as a slice in the FIFOs, 3 slices per Cell, 8 Cells from each Finder.

• On L1 Accept, FIFO outputs to multiplexers, then sent to PULSAR board. Otherwise, FIFO slice overwritten.

96 bits per cell * 8 cells per Finder Chip * 4.5 Finder Chips = 3,456 bits per Finder SL7 board 16 bits every 16.5ns, so it will take --> 3,456/16 * 16.5ns = 3.564us


Ben Kilminster

Cable

Reader

Latch

Pixels3=t

Remap

Pixels

SubRoad

Finder

Stereo pixels @16nsec

Single Linker L3 pixels

All L5 pixels

All L7 pixels

All L3 pixels

3lay

ers

by 3

cab

les

Stereo pixels @16.5nsec



Process

PtByPhi Array

Reformat

Linker

Linkers 0-5 to XTRP @33nsec

Linkers 6-11 to XTRP @33nsec

4 Phi bits by 48 Pt Bits Array

Stereo Confirmation

Bit @8.25nsec

SLAM Chip

3=t

5.0=t

1=t1=t

5.0=t

Loop over 12 linkers

12=t


Ben Kilminster

Firmware Progress

Stereo Chip Compilation ; Family ; Stratix II ; Device ; EP2S60F484C3 ; Timing Models ; Preliminary ; Total ALUTs ; 10,602 / 48,352 ( 21 % ) ; Total pins ; 150 / 335 ( 44 % ) ; Total memory bits ; 33,088 / 2,544,192 ( 1 % ) ; DSP block ; 0 / 288 ( 0 % ) ; Total PLLs ; 0 / 6 ( 0 % ) ; Total DLLs ; 0 / 2 ( 0 % )

SLAM Chip Compilation ; Family ; Stratix ; Device ; EP1S40F1020C5 ; Timing Models ; Production ; Total logic elements ; 25,081 / 41,250 ( 60 % ) ; Total pins ; 341 / 782 ( 43 % ) ; Total memory bits ; 6,912 / 3,423,744 ( < 1 % ) ; DSP block ; 0 / 112 ( 0 % ) ; Total PLLs ; 1 / 12 ( 8 % ) ; Total DLLs ; 0 / 2 ( 0 % )

Quartus II Version

4.1 Build 181 06/29/2004

SJ Full Version

The Stereo Finder and SLAM designs make extensive use of reprogrammable devices. Major progress in firmware over the last 6 months Functional designs have been implemented Timing has been studied

Finder Timing

61 (16.5 ns) clock ticks = 1007 ns from when first TDC data arrivesto when output of receiver on SLAM has 18 cells


Ben Kilminster

Stereo Finder Algorithm

Finder Algorithm Similar to axial XFT 6 time bins input (72 bits per 12-wire

cell) vs 2 time bins(24 bits) 8 12-wire cells vs 4 cells per FPGA 16.5ns clock vs 33ns clock Much larger Mask set L2 Pulsar Data(96 bits output) Implement in newest ALTERA Stratix

2 FPGA


Ben Kilminster

Segment Finding Algorithm

Found pixelphi & slope !

Check 4-wire patterns (generated by simulating tracks) in top, middle, and bottom 4 wires

Check all allowedcombinations of the three 4-wire- patterns

Output 1,2, or 3 misses

• For each SL (3,5,7), there are 3 designs for each allowed number of misses (1,2,or 3)• 2 designs can be loaded: one of the above plus a testing algorithm which allows us to input test vectors and verify output through rest of the system

SL

Upgrading the CDF Track Trigger to 3-D for High Instantaneous Luminosity

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