United States Texas- Richardson › XilinxClassReport › Location › ... · C-based design:...

Important Notice:

1. Class Schedule list below is as of December 06, 2018. 2. Class dates are subject to change due to low enrollment. Please contact your local training representative if you have any questions. 3. Confirm any timezone diffrences with the ATP when you register.

If you have any questions, please contact the Registrar at [email protected].

United States Texas- RichardsonDate Location Facility Price TC Reg. URL

C-based design: High-Level Synthesis with Vivado HLx Tool1/15/2019 3101 E. Pres George Bush Richardson USA, TX, Richardson - Avnet

Office1600 (USD) 16 Register

Designing FPGAs Using the Vivado Design Suite 11/17/2019 3101 E. Pres George Bush Richardson USA, TX, Richardson - Avnet


Designing FPGAs Using the Vivado Design Suite 22/26/2019 3101 E. Pres George Bush Richardson USA, TX, Richardson - Avnet


Zynq UltraScale+ MPSoC for the Software Developer2/28/2019 3101 E. Pres George Bush Richardson USA, TX, Richardson - Avnet


Classroom - Designing with VHDL2/19/2019 3101 E. Pres George Bush Richardson USA, TX, Richardson - Avnet


Classroom - Designing FPGAs Using the Vivado Design Suite 33/19/2019 3101 E. Pres George Bush Richardson USA, TX, Richardson - Avnet


Classroom - UltraFast Design Methodology1/22/2019 3101 E. Pres George Bush Richardson USA, TX, Richardson - Avnet


Classroom - Designing with the Zynq UltraScale+ RFSoC1/24/2019 3101 E. Pres George Bush Richardson USA, TX, Richardson - Avnet


United States NewYork- HauppaugeDate Location Facility Price TC Reg. URL

Embedded Systems Hardware Design Boot Camp (BLT version)12/12/2018 135 Engineers Rd Hauppauge USA, NY, Hauppauge -

Avnet Office2400 (USD) 24 Register

Vivado Boot Camp Phase-2 (BLT version)1/30/2019 135 Engineers Rd Hauppauge USA, NY, Hauppauge -


Vivado Boot Camp Phase-3 (BLT version)3/13/2019 135 Engineers Rd Hauppauge USA, NY, Hauppauge -


Embedded Systems Hardware Design Boot Camp (BLT version)3/20/2019 135 Engineers Rd Hauppauge USA, NY, Hauppauge -


mailTo:[email protected]

https://www.xilinx.com/training/courses/c-based-design-with-vivado-hlx.html

https://www.fastertechnology.com/store/courses/dsp-design-courses/vivado-hls-c-based-design.html

https://www.xilinx.com/training/courses/designing-fpgas-vivado-design-suite-1.html

https://www.fastertechnology.com/store/courses/fpga-design-courses/designing-fpgas-using-vivado-design-suite1.html?dir=d


https://www.fastertechnology.com/store/courses/fpga-design-courses/designing-fpgas-using-the-vivado-design-suite2.html

https://www.xilinx.com/training/courses/zynq-ultrascale-plus-mpsoc-software-developer.html

https://www.fastertechnology.com/store/courses/embedded-systems-development/zynq-ultrascale-mpsoc-software-designer-4.ht

https://www.xilinx.com/training/courses/designing-with-vhdl.html

http://www.fastertechnology.com/classschedule/event/cal/event///view-month%7Cpage_id-55/tx_cal_phpicalendar//designing_w


http://www.fastertechnology.com/classschedule/event/cal/event///view-month%7Cpage_id-55/tx_cal_phpicalendar//designing_f

https://www.xilinx.com/training/courses/ultrafast-design-methodology.html

https://www.fastertechnology.com/store/courses/fpga-design-courses/ultrafast-design-methodology.html?dir=desc&order=news

https://www.xilinx.com/content/dam/xilinx/training/connectivity/conn-rfsoc-ilt.pdf

https://www.fastertechnology.com/store/courses/connectivity-courses/designing-with-the-zynq-ultrascale-rfsoc.html

http://www.bltinc.com/Training-Course-BLT-Embedded-Systems-Hardware-Design-Boot-Camp.html

http://www.bltinc.com/XilinxTraining_PublicSchedule.htm

http://www.bltinc.com/Training-Course-BLT-Vivado-Boot-Camp-Phase-2.html






United States NewJersey- MarltonDate Location Facility Price TC Reg. URL

Vivado Boot Camp Phase-1 (BLT version)1/23/2019 13000 Lincoln Drive West Marlton USA, NJ, Marlton - Avnet


Embedded Systems Hardware Design Boot Camp (BLT version)1/28/2019 13000 Lincoln Drive West Marlton USA, NJ, Marlton - Avnet


C-based design: High-Level Synthesis with Vivado HLx Tool2/18/2019 13000 Lincoln Drive West Marlton USA, NJ, Marlton - Avnet


Essential DSP Implementation Techniques for Xilinx FPGAs2/20/2019 13000 Lincoln Drive West Marlton USA, NJ, Marlton - Avnet


DSP Design Using System Generator2/21/2019 13000 Lincoln Drive West Marlton USA, NJ, Marlton - Avnet






United States NewYork- RochesterDate Location Facility Price TC Reg. URL

Vivado Boot Camp Phase-2 (BLT version)1/23/2019 245 Kenneth Drive Rochester USA, NY, Rochester - Avnet


Vivado Boot Camp Phase-3 (BLT version)3/6/2019 245 Kenneth Drive Rochester USA, NY, Rochester - Avnet


C-based design: High-Level Synthesis with Vivado HLx Tool3/25/2019 245 Kenneth Drive Rochester USA, NY, Rochester - Avnet


Essential DSP Implementation Techniques for Xilinx FPGAs3/27/2019 245 Kenneth Drive Rochester USA, NY, Rochester - Avnet


DSP Design Using System Generator3/28/2019 245 Kenneth Drive Rochester USA, NY, Rochester - Avnet


Embedded Systems Hardware Design Boot Camp (BLT version)4/10/2019 245 Kenneth Drive Rochester USA, NY, Rochester - Avnet








https://www.xilinx.com/training/courses/essential-dsp-implementation-techniques.html


https://www.xilinx.com/training/courses/dsp-design-using-system-generator.html


















The Netherlands - HeeschDate Location Facility Price TC Reg. URL

Designing with the UltraScale and UltraScale+ Architectures12/20/2018 Cereslaan 10b Heesch NLD, Heesch - CoreVision

Headquarters1500 (EUR) 18 Register

Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users1/9/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Zynq UltraScale+ MPSoC for the Hardware Designer1/18/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Zynq UltraScale+ MPSoC for the System Architect1/16/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - C-based design: High-Level Synthesis with Vivado HLx Tool1/28/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Designing with Xilinx Serial Transceivers1/23/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - SDSoC Development Environment and Methodology1/30/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Advanced SDSoC Development Environment and Methodology1/31/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Designing FPGAs Using the Vivado Design Suite 12/4/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision




Classroom - Essential Digital Design Techniques (CoreVision Version)12/18/2018 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Comprehensive VHDL (CoreVision Version)12/10/2018 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - VHDL for Designers (CoreVision Version)12/10/2018 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Advanced VHDL (CoreVision Version)12/13/2018 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Designing with the UltraScale and UltraScale+ Architectures2/13/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Embedded Systems Design2/18/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Embedded Systems Software Design2/20/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Expert VHDL (CoreVision Version)2/25/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Expert VHDL Verification (CoreVision Version)2/27/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Zynq SoC System Architecture3/4/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Advanced Features and Techniques of Embedded Systems Design3/6/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Advanced Features and Techniques of Embedded Systems Software Design

https://www.xilinx.com/training/courses/designing-with-ultrascale-ultrascale-plus.html

https://www.core-vision.nl/events/designing-with-the-ultrascale-and-ultrascale-architectures-7/

https://www.xilinx.com/training/courses/vivado-xdc-and-static-timing-analysis.html

https://www.core-vision.nl/events/vivado-design-suite-advanced-xdc-and-static-timing-analysis-for-ise-software-users-8/?

https://www.xilinx.com/training/courses/zynq-ultrascale-plus-hardware-designer.html

https://www.core-vision.nl/events/zynq-ultrascale-mpsoc-for-the-hardware-designer-4/?lang=en

https://www.xilinx.com/training/courses/zynq-ultrascale-plus-system-architect.html

https://www.core-vision.nl/events/zynq-ultrascale-mpsoc-for-the-system-architect-5/?lang=en


https://www.core-vision.nl/events/c-based-design-high-level-synthesis-with-the-vivado-hlx-tool-6/?lang=en

https://www.xilinx.com/training/courses/designing-with-xilinx-serial-transceivers.html

https://www.core-vision.nl/events/designing-with-ultrascale-fpga-transceivers-2/?lang=en

https://www.xilinx.com/training/courses/sdsoc-development-environment-method.html

https://www.core-vision.nl/events/sdsoc-development-environment-and-methodology-6/?lang=en

https://www.xilinx.com/training/courses/advanced-sdsoc-development-environment-methodology.html

https://www.core-vision.nl/events/advanced-sdsoc-development-environment-and-methodology-6/?lang=en


https://www.core-vision.nl/events/designing-fpgas-using-the-vivado-design-suite-1-10/?lang=en



https://www.core-vision.nl/events/essential-digital-design-techniques-6/?lang=en


https://www.core-vision.nl/events/comprehensive-vhdl-6/?lang=en

https://www.core-vision.nl/training-schedule/?lang=en

https://www.core-vision.nl/events/vhdl-for-designers/?lang=en

https://www.core-vision.nl/events/vhdl-for-designers-4/?lang=en

https://www.core-vision.nl/events/advanced-vhdl-6/

https://www.core-vision.nl/events/advanced-vhdl-6/?lang=en


https://www.core-vision.nl/events/designing-with-the-ultrascale-and-ultrascale-architectures-8/?lang=en

https://www.xilinx.com/training/courses/embedded-systems-design.html

https://www.core-vision.nl/events/embedded-systems-design-8/?lang=en

https://www.xilinx.com/training/courses/embedded-systems-software-design.html

https://www.core-vision.nl/events/embedded-systems-software-design-9/?lang=en

https://www.core-vision.nl/events/expert-vhdl-5/

https://www.core-vision.nl/events/expert-vhdl-7/?lang=en

https://www.core-vision.nl/events/expert-vhdl-verification-5/?lang=en

https://www.core-vision.nl/events/expert-vhdl-verification-7/?lang=en

https://www.xilinx.com/training/courses/zynq-soc-system-architecture.html

https://www.core-vision.nl/events/zynq-all-programmable-soc-system-architecture-9/?lang=en

https://www.xilinx.com/training/courses/advanced-embedded-systems-design.html

https://www.core-vision.nl/events/advanced-features-and-techniques-embedded-systems-design-8/?lang=en

https://www.xilinx.com/training/courses/advanced-embedded-systems-software-design.html

3/8/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVisionHeadquarters

750 (EUR) 9 Register

Classroom - Comprehensive VHDL (CoreVision Version)3/11/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - VHDL for Designers (CoreVision Version)3/11/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Advanced VHDL (CoreVision Version)3/14/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision






Classroom - UltraFast Design Methodology3/28/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Essential Digital Design Techniques (CoreVision Version)3/25/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - C-based design: High-Level Synthesis with Vivado HLx Tool4/1/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - SDSoC Development Environment and Methodology4/3/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Advanced SDSoC Development Environment and Methodology4/4/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - DSP Design Using System Generator4/11/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Essential DSP Implementation Techniques for Xilinx FPGAs4/18/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Zynq UltraScale+ MPSoC for the System Architect4/24/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


Classroom - Zynq UltraScale+ MPSoC for the Hardware Designer4/26/2019 Cereslaan 10b Heesch NLD, Heesch - CoreVision


United Kingdom - RingwoodDate Location Facility Price TC Reg. URL

ARM Cortex-A53 for Zynq UltraScale+ MPSoC (Doulos course)12/10/2018 Doulos Ltd, Church Hatch, 22 Market Place Ringwood GBR, Ringwood - Doulos

Headquarters3100 (GBP) 36 Register

Comprehensive VHDL (Doulos version)12/10/2018 Doulos Ltd, Church Hatch, 22 Market Place Ringwood GBR, Ringwood - Doulos


Virtual - SDSoC Adopter Class (Doulos version)1/30/2019 Doulos Ltd, Church Hatch, 22 Market Place Ringwood GBR, Ringwood - Doulos


Classroom - Vivado Adopter Class (Doulos version)1/22/2019 Doulos Ltd, Church Hatch, 22 Market Place Ringwood GBR, Ringwood - Doulos


https://www.core-vision.nl/events/advanced-features-and-techniques-embedded-systems-software-design-6/?lang=en



https://www.core-vision.nl/events/vhdl-for-designers/?lang=en

https://www.core-vision.nl/events/vhdl-for-designers-5/?lang=en

https://www.core-vision.nl/events/advanced-vhdl-6/

https://www.core-vision.nl/events/advanced-vhdl-8/?lang=en






https://www.core-vision.nl/events/ultrafast-design-methodology-8/?lang=en




https://www.core-vision.nl/events/c-based-design-high-level-synthesis-with-the-vivado-hlx-tool-7/?lang=en


https://www.core-vision.nl/events/sdsoc-development-environment-and-methodology-7/?lang=en


https://www.core-vision.nl/events/advanced-sdsoc-development-environment-and-methodology-7/?lang=en


https://www.core-vision.nl/events/dsp-design-using-system-generator-10/?lang=en


https://www.core-vision.nl/events/essential-dsp-implementation-techniques-for-xilinx-fpgas-9/?lang=en


https://www.core-vision.nl/events/zynq-ultrascale-mpsoc-for-the-system-architect-6/?lang=en

https://www.xilinx.com/training/courses/zynq-ultrascale-plus-hardware-designer.html

https://www.core-vision.nl/events/zynq-ultrascale-mpsoc-for-the-hardware-designer-5/?lang=en

https://www.doulos.com/content/training/arm_cortex_A53_for_ultrascale_plus.php

https://www.doulos.com/content/training/arm_cortex_A53_for_ultrascale_plus.php

https://www.doulos.com/content/training/comprehensive_vhdl_training.php

https://www.doulos.com/content/training/comprehensive_vhdl_training.php

https://www.doulos.com/content/training/xilinx_SDSoCAdopter.php

https://www.doulos.com/content/training/xilinx_SDSoCAdopter.php

https://www.doulos.com/content/training/xilinx_vivado_adopter.php

https://www.doulos.com/content/training/xilinx_vivado_adopter.php

Taiwan - TaipeiDate Location Facility Price TC Reg. URL

Designing with the UltraScale and UltraScale+ Architectures12/13/2018 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-

Elemements Office20000 (USD) 16 Register

Designing with Ethernet MAC Controllers12/20/2018 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-


Designing FPGAs Using the Vivado Design Suite 312/27/2018 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-




Zynq UltraScale+ MPSoC for the System Architect1/15/2019 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-


Embedded Systems Design1/10/2019 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-


Designing with UltraScale FPGA Transceivers1/29/2019 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-


Advanced SDSoC Development Environment and Methodology2/14/2019 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-




Introduction to Zynq All Programmable SoC Architecture2/26/2019 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-


Designing an Integrated PCI Express System3/7/2019 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-


Embedded Systems Design3/12/2019 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-


Designing with the UltraScale and UltraScale+ Architectures3/14/2019 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-


C-based design: High-Level Synthesis with Vivado HLx Tool3/19/2019 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-


Designing with Ethernet MAC Controllers3/26/2019 5F, No.61, Lane76, Ruiguang Rd. Taipei TWN, Taipei - E-




United States Massachusetts- BurlingtonDate Location Facility Price TC Reg. URL

Accelerating C C++ OpenCL & RTL Applications w SDAccel - Classroom2/14/2019 TBD Burlington USA, MA, Burlington -- TBD

Hardent Venue1800 (USD) 18 Register

Developing AWS F1 Applications Using the SDAccel Environment Course - Classroom2/11/2019 TBD Burlington USA, MA, Burlington -- TBD



https://www.xilinx.com/training/courses/designing-with-ethernet-mac-controllers.html





https://www.xilinx.com/training/courses/designing-with-ultrascale-fpga-transceivers.html



https://www.xilinx.com/training/courses/introduction-to-zynq-architecture.html

https://www.xilinx.com/training/courses/designing-integrated-pci-express.html






https://www.hardent.com/course/accelerating-with-the-sdaccel-environment/

https://www.hardent.com/course/developing-aws-f1-applications-using-the-sdaccel-environment/

Canada Quebec- MontrealDate Location Facility Price TC Reg. URL

SDSoC Development Environment and Methodology12/19/2018 450 Saint Pierre, #300 Montreal CAN, QC, Montreal -

Hardent Headquarters800 (USD) 8 Register

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology(combined course)1/21/2019 450 Saint Pierre, #300 Montreal CAN, QC, Montreal -


Embedded System Design for the Zynq UltraScale+ MPSoC (combined course)3/6/2019 450 Saint Pierre, #300 Montreal CAN, QC, Montreal -


C-based design: High-Level Synthesis with Vivado HLx Tool1/24/2019 450 Saint Pierre, #300 Montreal CAN, QC, Montreal -


Introduction to Universal Verification Methodology (UVM)1/21/2019 450 Saint Pierre, #300 Montreal CAN, QC, Montreal -


Embedded Design with PetaLinux Tools3/4/2019 450 Saint Pierre, #300 Montreal CAN, QC, Montreal -


Advanced SDSoC Development Environment and Methodology12/20/2018 450 Saint Pierre, #300 Montreal CAN, QC, Montreal -


Accelerating C C++ OpenCL & RTL Applications w SDAccel - Classroom1/14/2019 450 Saint Pierre, #300 Montreal CAN, QC, Montreal -


Developing AWS F1 Applications Using the SDAccel Environment Course - Classroom12/20/2018 450 Saint Pierre, #300 Montreal CAN, QC, Montreal -


Japan - YokohamaDate Location Facility Price TC Reg. URL

RTL(Verilog) Design with Vivado Design Suite (HDLab version)1/8/2019 Innotec Bldg 10F 3-17-6, Shin-Yokohama, Kouhoku-ku

YokohamaJPN, Yokohama - HDLabHeadquarters

113510 (JPY) 8 Register

Classroom - UltraFast Design Methodology1/24/2019 Innotec Bldg 10F 3-17-6, Shin-Yokohama, Kouhoku-ku



Understand Simulation with Vivado Design Suite (HDLab version)2/12/2019 Innotec Bldg 10F 3-17-6, Shin-Yokohama, Kouhoku-ku



Vivado Design Suite Static Constraints and Timing Analysis (HDLab version)2/13/2019 Innotec Bldg 10F 3-17-6, Shin-Yokohama, Kouhoku-ku



RTL(Verilog) Design with Vivado Design Suite (HDLab version)2/19/2019 Innotec Bldg 10F 3-17-6, Shin-Yokohama, Kouhoku-ku



Vivado Design Suite Static Timing Closure (HDLab version)2/28/2019 Innotec Bldg 10F 3-17-6, Shin-Yokohama, Kouhoku-ku



MicroBlaze for beginner with ARTY Board ( HDLab course)3/7/2019 Innotec Bldg 10F 3-17-6, Shin-Yokohama, Kouhoku-ku



Vivado Design Suite Tool Flow with Artix-7 Board (HDLab course)3/8/2019 Innotec Bldg 10F 3-17-6, Shin-Yokohama, Kouhoku-ku



RTL(VHDL) Design with Vivado Design Suite (HDLab version)3/11/2019 Innotec Bldg 10F 3-17-6, Shin-Yokohama, Kouhoku-ku



C for beginner with Vivado HLS tool (HDLab version)3/18/2019 Innotec Bldg 10F 3-17-6, Shin-Yokohama, Kouhoku-ku




https://www.hardent.com/course/sdsoc-development-and-methodology/

https://www.hardent.com/course/vivado-design-suite-advanced-xdc-and-static-timing-analysis-with-design-methodology/

https://www.hardent.com/course/embedded-system-design-for-the-zynq-ultrascale-mpsoc/


https://www.hardent.com/course/c-based-design-high-level-synthesis-with-vivado-hls/

https://www.hardent.com/course/universal-verification-methodology-uvm/


https://www.xilinx.com/training/courses/embedded-design-with-petalinux.html

https://www.hardent.com/course/embedded-design-with-petalinux-tools/


https://www.hardent.com/course/advanced-sdsoc-development-environment-and-methodology/



http://info.hdlab.co.jp/training/xilinx/vrtl_verilog/

http://info.hdlab.co.jp/training/schedule/



http://info.hdlab.co.jp/training/xilinx/vivad_sim/


http://info.hdlab.co.jp/training/xilinx/timing/


http://info.hdlab.co.jp/training/xilinx/vrtl_verilog/


http://info.hdlab.co.jp/training/xilinx/closure/


http://info.hdlab.co.jp/training/xilinx/microblaze/


http://info.hdlab.co.jp/training/xilinx/artix7/


http://info.hdlab.co.jp/training/xilinx/vrtl_vhdl/


http://info.hdlab.co.jp/training/xilinx/hls_c/


United States California- El SegundoDate Location Facility Price TC Reg. URL

C-based design: High-Level Synthesis with Vivado HLx Tool12/17/2018 2100 East Mariposa Ave El Segundo USA, CA, El Segundo -

Hilton Garden Inn1600 (USD) 16 Register

Israel - Petah-TikvaDate Location Facility Price TC Reg. URL

Vivado Design Suite Advanced XDC and Timing Analysis for ISE Users12/26/2018 32 Shacham St, Ramat-Siv Industrial Park Petah-Tikva ISR, Petah-Tikva - Logtel

Headquarters1600 (USD) 15 Register

PCIe Gen1.X to 4.X (Logtel course)12/24/2018 32 Shacham St, Ramat-Siv Industrial Park Petah-Tikva ISR, Petah-Tikva - Logtel


Advanced Designing with Verilog (Logtel version)12/11/2018 32 Shacham St, Ramat-Siv Industrial Park Petah-Tikva ISR, Petah-Tikva - Logtel


Designing FPGAs Using the Vivado Design Suite 212/10/2018 32 Shacham St, Ramat-Siv Industrial Park Petah-Tikva ISR, Petah-Tikva - Logtel


Russia - MoscowDate Location Facility Price TC Reg. URL

Classroom - Designing with VHDL12/17/2018 78, prospect Vernadskogo Moscow RUS, Moscow - MIREA 1500 (RUB) 15 Register

Classroom - Designing with SystemVerilog12/10/2018 78, prospect Vernadskogo Moscow RUS, Moscow - MIREA 1600 (RUB) 16 Register

France - SèvresDate Location Facility Price TC Reg. URL

Designing FPGAs Using the Vivado Design Suite 312/11/2018 7 avenue de l'europe Sèvres FRA, Paris - MVD Training

Classroom1600 (EUR) 16 Register

Designing FPGAs Using the Vivado Design Suite 412/13/2018 7 avenue de l'europe Sèvres FRA, Paris - MVD Training


VHDL Logical Synthesis and Simulation for Xilinx? FPGA design (MVD version)12/17/2018 7 avenue de l'europe Sèvres FRA, Paris - MVD Training



http://bit.ly/2DHtXlB

https://www.xilinx.com/training/courses/vivado-xdc-and-static-timing-analysis.html

http://www.logtel.com/sites/default/files/regform-liran.pdf

http://www.logtel.com/content/training/hardware/pcb-world/pcie-gen1x-4x

http://www.logtel.com/content/training/hardware/pcb-world/pcie-gen1x-4x

http://www.logtel.com/content/training/hardware/hardware-definition-languages/advanced-design-verilog

http://www.logtel.com/content/training/hardware/hardware-definition-languages/advanced-design-verilog



https://plis2.ru/training/designing-with-vhdl.html

https://www.xilinx.com/training/courses/designing-with-system-verilog.html

https://plis2.ru/training/designing-with-system-verilog.html


https://www.mvd-training.com/fr/formation/fpga/vivado/FPGA_VDES3_Vivado_Design_Suite.php


https://www.mvd-training.com/fr/formation/fpga/vivado/FPGA_VDES4_Vivado_Design_Suite.php

http://www.mvd-training.com/en/formation/fpga_vhdl/fpga/maitrise_conception_fpga/L_VHDL_5_VHDL_logical_synthesis_and_simulation_for_Xilinx_FPGA_design.php

https://www.mvd-training.com/fr/formation/langage/VHDL/L_VHDL_Synthese_logique_et_simulation_VHDL_pour_conception_de_FPG

Germany - FreiburgDate Location Facility Price TC Reg. URL

Professional Vivado (PLC2 version)12/17/2018 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 3832 (EUR) 45 Register

Compact Advanced VHDL Testbenches and Verification /OSVVM (PLC2 course)12/17/2018 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 2300 (EUR) 27 Register

Version Control for Xilinx with Git (PLC2 course)12/17/2018 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 2300 (EUR) 27 Register

Tcl Schnellstart ( PLC2 version)12/17/2018 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 1533 (EUR) 18 Register

Advanced Vivado Tcl-Scripting (PLC2 version)12/18/2018 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 2300 (EUR) 27 Register

Professional ZYNQ-7000 SoC (PLC2 version)1/21/2019 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 3100 (EUR) 45 Register

Easy Start FPGA Vivado (PLC2 version)1/28/2019 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 1700 (EUR) 18 Register

Designing a LogiCORE PCI Express System (PLC2 version)5/13/2019 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 2300 (EUR) 27 Register

Easy Start Embedded for ZYNQ-7000 SoC Systems (PLC2 version)2/11/2019 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 1533 (EUR) 18 Register

Professional VHDL (PLC2 version)2/11/2019 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 3832 (EUR) 45 Register

Vivado Design Suite Static Timing Analysis and XILINX Design Constraints (PLC2 version)3/6/2019 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 2300 (EUR) 27 Register

Professional ZYNQ UltraScale+ MPSoC (PLC2 version)3/18/2019 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 3832 (EUR) 45 Register

Professional Vivado (PLC2 version)3/25/2019 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 3832 (EUR) 45 Register

Classroom - Designing with 7 Series3/14/2019 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 1600 (EUR) 16 Register

Professional FPGA Schaltungstechnik (PLC2 course)4/1/2019 Hugstmattweg 30 Freiburg DEU, Freiburg - PLC2 Office 3832 (EUR) 45 Register

http://www.plc2.com/assets/files/2015/03FPGA/Prof_Vivado.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/fpga/professional-vivado.html

http://www.plc2.com/assets/files/2015/03FPGA/Compact_Adv_VHDL_OSVVM.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/fpga/compact-osvvm.html

http://www.plc2.com/assets/files/2015/03FPGA/Version_Control_with_Git.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/fpga/git.html

http://www.plc2.com/assets/files/2015/03FPGA/Tcl_Quickstart.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/fpga/tcl-schnellstart-2-tage.html

http://www.plc2.com/assets/files/2015/03FPGA/Adv_Vivado-Tcl-Scripting.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/fpga/advanced-vivado-tcl-scripting.html

http://www.plc2.com/assets/files/2015/04Embedded/Prof_ZYNQ-7000.pdf

https://www.plc2.com/en/fpga-training/course-overview/embedded/professional-zynq-7000-soc.html

http://www.plc2.com/assets/files/2015/01Easy%20Start/Easy_Start_FPGA_Vivado.pdf

https://www.plc2.com/en/fpga-training/course-overview/easy-start/easy-start-fpga-vivado.html

http://www.plc2.com/assets/files/2015/06Connectivity/Des_with_PCI_Express.pdf

https://www.plc2.com/en/fpga-training/course-overview/connectivity/designing-with-pci-express.html

http://www.plc2.com/assets/files/2015/01Easy%20Start/Easy_Start_Emb_ZYNQ.pdf

https://www.plc2.com/en/fpga-training/course-overview/easy-start/easy-start-embedded-for-zynq-7000-soc-systems.html

http://www.plc2.com/assets/files/2015/03FPGA/Professional_VHDL.pdf

https://www.plc2.com/en/fpga-training/course-overview/fpga/professional-vhdl.html

http://www.plc2.com/assets/files/2015/03FPGA/Vivado_Stat_Timing.pdf

https://www.plc2.com/en/fpga-training/course-overview/fpga/vivado-design-suite-static-timing.html

http://www.plc2.com/assets/files/2015/04Embedded/Prof_ZYNQ_US_MPSoC.pdf

http://www.plc2.com/assets/files/2015/03FPGA/Prof_Vivado.pdf

https://www.xilinx.com/training/courses/designing-xilinx-7-series-families.html

https://www.plc2.com/en/fpga-training/course-overview/fpga/designing-with-the-spartan-7-family.html

http://www.plc2.com/assets/files/2015/03FPGA/Prof_FPGA_Schalt.pdf

https://www.plc2.com/en/fpga-training/course-overview/fpga/professional-fpga-design-techniques.html

India - BangaloreDate Location Facility Price TC Reg. URL

UltraFast Design Methodology12/10/2018 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -

Sandeepani School ofEmbedded System Design

800 (USD) 8 Register

Xilinx Partial Reconfiguration Tools & Techniques12/13/2018 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Zynq-7000 All Programmable SoC System Architecture12/17/2018 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Advanced SDSoC Development Environment and Methodology12/20/2018 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Designing with 7 Series1/3/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Classroom - Designing with the UltraScale and UltraScale+ Architectures1/7/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Classroom - UltraFast Design Methodology1/10/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Custom HLS and SDSoC1/17/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Custom SDAccel1/21/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Classroom - Designing with UltraScale FPGA Transceivers1/23/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Custom Partial Reconfiguration1/30/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



How to Design a High-Speed Memory Interface2/4/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Classroom - Embedded Design with PetaLinux Tools2/6/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Classroom - SDSoC Development Environment and Methodology2/11/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Custom Zynq UltraScale+MPSoC2/13/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Classroom - Embedded Systems Software Design2/18/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Classroom - Essential DSP Implementation Techniques for Xilinx FPGAs2/21/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Classroom - Designing FPGAs Using the Vivado Design Suite 12/25/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -




https://tinyurl.com/ydevh5fc

https://www.xilinx.com/training/courses/partial-reconfiguration-tools-and-techniques.html

https://tinyurl.com/y7zcz9ya


https://tinyurl.com/y7znr9ov


https://tinyurl.com/ycjtzamt

https://www.xilinx.com/training/courses/designing-xilinx-7-series-families.html

https://tinyurl.com/y7n4uypy


https://tinyurl.com/y8l2uz39


https://tinyurl.com/yd4yddrk

https://tinyurl.com/y8kffqgn

https://tinyurl.com/ydbsucq3

https://www.xilinx.com/training/courses/designing-with-ultrascale-fpga-transceivers.html

https://tinyurl.com/y7a62fb8

https://tinyurl.com/yb4n6qab

https://tinyurl.com/y94as5zh


https://tinyurl.com/ycszm5pd


https://tinyurl.com/yct54342

https://tinyurl.com/ybft744l


https://tinyurl.com/yccaypyu


https://tinyurl.com/y9z6v6h4


https://tinyurl.com/yan7kxr4

Classroom - Designing FPGAs Using the Vivado Design Suite 22/27/2019 #21, 7th Main, 1st Block, Koramangala Bangalore IND, Bangalore -



Austria - ViennaDate Location Facility Price TC Reg. URL

Essential DSP Implementation Techniques for Xilinx FPGAs12/10/2018 Lustkandlg. 52 Vienna AUT, Vienna - So-Logic

Office1500 (EUR) 16 Register

C-based design: High-Level Synthesis with Vivado HLx12/12/2018 Lustkandlg. 52 Vienna AUT, Vienna - So-Logic


DSP Design Using System Generator12/12/2018 Lustkandlg. 52 Vienna AUT, Vienna - So-Logic


C-based HLS Coding for Software Designers12/14/2018 Lustkandlg. 52 Vienna AUT, Vienna - So-Logic


C-based HLS Coding for Hardware Designers12/14/2018 Lustkandlg. 52 Vienna AUT, Vienna - So-Logic


United States NewJersey- ParsippanyDate Location Facility Price TC Reg. URL

Vivado Boot Camp Phase-1 (BLT version)1/23/2019 61 Interpace Parkway Parsippany USA, NJ, Parsippany -

Sonesta ES Suites2700 (USD) 27 Register

Embedded Systems Hardware Design Boot Camp (BLT version)1/28/2019 61 Interpace Parkway Parsippany USA, NJ, Parsippany -


C-based design: High-Level Synthesis with Vivado HLx Tool2/18/2019 61 Interpace Parkway Parsippany USA, NJ, Parsippany -


Essential DSP Implementation Techniques for Xilinx FPGAs2/20/2019 61 Interpace Parkway Parsippany USA, NJ, Parsippany -


DSP Design Using System Generator2/21/2019 61 Interpace Parkway Parsippany USA, NJ, Parsippany -


DSP Design Using System Generator3/7/2019 61 Interpace Parkway Parsippany USA, NJ, Parsippany -







https://tinyurl.com/y7taux5a


https://www.so-logic.net//en/training_courses/xilinx/xilinx_dsp/xil_dsp_imp


https://www.so-logic.net//en/training_courses/xilinx/xilinx_dsp/c_design_vivado_hls


https://www.so-logic.net//en/training_courses/xilinx/xilinx_dsp/xil_dsp_sysgen

https://www.xilinx.com/training/courses/c-based-hls-coding-for-software-designers.html

https://www.so-logic.net//en/training_courses/xilinx/xilinx_dsp/HLS_SW_Engineers

https://www.xilinx.com/training/courses/c-based-hls-coding-for-hardware-designers.html

https://www.so-logic.net//en/training_courses/xilinx/xilinx_dsp/HLS_HW_Engineers








BLT makes substantial commitments of its resources to host each training class. We expect that our students are as commi









United States Florida- OrlandoDate Location Facility Price TC Reg. URL

Embedded System Design for the Zynq UltraScale+ MPSoC (combined course)1/28/2019 TBD Orlando USA, FL, Orlando - TBD


Embedded Design with PetaLinux Tools1/31/2019 TBD Orlando USA, FL, Orlando - TBD


Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology(combined course)3/6/2019 TBD Orlando USA, FL, Orlando - TBD


SystemVerilog for Verification3/11/2019 TBD Orlando USA, FL, Orlando - TBD


Introduction to Universal Verification Methodology (UVM)2/4/2019 TBD Orlando USA, FL, Orlando - TBD


SDSoC Development Environment and Methodology2/6/2019 TBD Orlando USA, FL, Orlando - TBD


Advanced SDSoC Development Environment and Methodology2/7/2019 TBD Orlando USA, FL, Orlando - TBD


C-based design: High-Level Synthesis with Vivado HLx Tool2/4/2019 TBD Orlando USA, FL, Orlando - TBD


Classroom - Designing with the Zynq UltraScale+ RFSoC3/4/2019 TBD Orlando USA, FL, Orlando - TBD


Canada Ontario- OttawaDate Location Facility Price TC Reg. URL

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology(combined course)4/15/2019 TBD Ottawa CAN, ON, Ottawa - TBD


Classroom - Designing with the Zynq UltraScale+ RFSoC3/26/2019 TBD Ottawa CAN, ON, Ottawa - TBD


Classroom - DSP Design Using System Generator4/24/2019 TBD Ottawa CAN, ON, Ottawa - TBD






https://www.hardent.com/course/systemverilog-for-verification/











https://www.hardent.com/course/designing-with-the-zynq-ultrascale-rfsoc/





https://www.hardent.com/course/dsp-design-using-system-generator/

Canada Ontario- TorontoDate Location Facility Price TC Reg. URL

Embedded System Design for the Zynq UltraScale+ MPSoC (combined course)1/15/2019 TBD Toronto CAN, ON, Toronto - TBD


C-based design: High-Level Synthesis with Vivado HLx Tool3/11/2019 TBD Toronto CAN, ON, Toronto - TBD


SDSoC Development Environment and Methodology3/13/2019 TBD Toronto CAN, ON, Toronto - TBD


Advanced SDSoC Development Environment and Methodology3/14/2019 TBD Toronto CAN, ON, Toronto - TBD


SystemVerilog for Verification (Hardent version)1/28/2019 TBD Toronto CAN, ON, Toronto - TBD


Introduction to Universal Verification Methodology (UVM) (Hardent version)4/8/2019 TBD Toronto CAN, ON, Toronto - TBD


Accelerating C C++ OpenCL & RTL Applications w SDAccel - Classroom1/29/2019 TBD Toronto CAN, ON, Toronto - TBD


Classroom - Vivado Design Suite Advanced XDC and Static Timing Analysis with DesignMethodology (combined course)5/22/2019 TBD Toronto CAN, ON, Toronto - TBD


United States Indiana- TBDDate Location Facility Price TC Reg. URL

Designing FPGAs Using the Vivado Design Suite 212/7/2018 TBD TBD USA, IN - TBD VAI Logic

Venue1600 (USD) 16 Register

Virtual - Embedded Systems Software Design2/18/2019 TBD TBD USA, IN - TBD VAI Logic


Classroom - Designing with the Zynq UltraScale+ RFSoC3/7/2019 TBD TBD USA, IN - TBD VAI Logic


Classroom - Designing with the Zynq UltraScale+ RFSoC3/8/2019 TBD TBD USA, IN - TBD VAI Logic


United States Ohio- TBDDate Location Facility Price TC Reg. URL

Designing FPGAs Using the Vivado Design Suite 312/13/2018 TBD TBD USA, OH - TBD VAI Logic


Classroom - Embedded Design with PetaLinux Tools2/26/2019 TBD TBD USA, OH - TBD VAI Logic


Classroom - Embedded Design with PetaLinux Tools2/27/2019 TBD TBD USA, OH - TBD VAI Logic
















https://www.cognitoforms.com/VaiTechnology2/ClassRegistration













United States Michigan- TBDDate Location Facility Price TC Reg. URL

Designing FPGAs Using the Vivado Design Suite 312/12/2018 TBD TBD USA, MI - TBD VAI Logic


Embedded Systems Design12/18/2018 TBD TBD USA, MI - TBD VAI Logic


Embedded Systems Design12/19/2018 TBD TBD USA, MI - TBD VAI Logic


Germany - BerlinDate Location Facility Price TC Reg. URL

Designing a LogiCORE PCI Express System (PLC2 version)12/10/2018 TBD Berlin DEU, Berlin - TBD PLC2

Venue2300 (EUR) 27 Register

Python (PLC2 course)12/10/2018 TBD Berlin DEU, Berlin - TBD PLC2


High-Speed Memory Interfacing (PLC2 version)3/11/2019 TBD Berlin DEU, Berlin - TBD PLC2


DDR4 Interfacing with XILINX FPGAs (PLC2 version)2/11/2019 TBD Berlin DEU, Berlin - TBD PLC2


Professional PCI Express (PLC2 version)4/8/2019 TBD Berlin DEU, Berlin - TBD PLC2


Easy Start FPGA Vivado (PLC2 version)3/18/2019 TBD Berlin DEU, Berlin - TBD PLC2


Debugging Techniques Using the Vivado Logic Analyzer (PLC2 version)3/20/2019 TBD Berlin DEU, Berlin - TBD PLC2


Germany - FrankfurtDate Location Facility Price TC Reg. URL

Compact FPGA 7 Series (PLC2 version)12/10/2018 TBD Frankfurt DEU, Frankfurt - TBD PLC2


Expert ZYNQ-7000 SoC (PLC2 version)12/17/2018 TBD Frankfurt DEU, Frankfurt - TBD PLC2


FPGA Board Design (PLC2 course)1/24/2019 TBD Frankfurt DEU, Frankfurt - TBD PLC2


Professional FPGA (PLC2 version)2/18/2019 TBD Frankfurt DEU, Frankfurt - TBD PLC2


ZYNQ-7000 SoC System Architecture (PLC2 version)2/18/2019 TBD Frankfurt DEU, Frankfurt - TBD PLC2


Compact ZYNQ UltraScale+ MPSoC for HW Designers (PLC2 version)2/20/2019 TBD Frankfurt DEU, Frankfurt - TBD PLC2


Vivado Design Suite Tool Flow (PLC2 version)2/25/2019 TBD Frankfurt DEU, Frankfurt - TBD PLC2





https://www.cognitoforms.com/VaiTechnology2/classRegistration


https://www.cognitoforms.com/VaiTechnology2/classRegistration


https://www.plc2.com/de/schulungen/kursuebersicht/connectivity/designing-with-pci-express.html

http://www.plc2.com/assets/files/2015/03FPGA/Python_for_Programmers.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/fpga/python.html

http://www.plc2.com/assets/files/2015/06Connectivity/HighSpeed_Memory_Interface.pdf

https://www.plc2.com/en/fpga-training/course-overview/connectivity/high-speed-memory-interfacing.html

http://www.plc2.com/assets/files/2015/06Connectivity/DDR4_Interfacing_XILINX_FPGA.pdf

https://www.plc2.com/en/fpga-training/course-overview/connectivity/ddr4-interfacing-with-xilinx-fpgas.html

http://www.plc2.com/assets/files/2015/06Connectivity/Profess_PCI_Express.pdf

https://www.plc2.com/en/fpga-training/course-overview/connectivity/professional-pci-express.html

http://www.plc2.com/assets/files/2015/01Easy%20Start/Easy_Start_FPGA_Vivado.pdf

http://www.plc2.com/assets/files/2015/03FPGA/Debug_Tech_VIVADO.pdf

http://www.plc2.com/assets/files/2015/03FPGA/Comp_FPGA_7.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/fpga/compact-fpga-7-series.html

http://www.plc2.com/assets/files/2015/04Embedded/Expert_ZYNQ.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/embedded/expert-zynq.html

http://www.plc2.com/assets/files/2015/06Connectivity/Board_Design.pdf

https://www.plc2.com/en/fpga-training/course-overview/connectivity/fpga-board-design.html

http://www.plc2.com/assets/files/2015/03FPGA/Pro_FPGA.pdf

https://www.plc2.com/en/fpga-training/course-overview/fpga/professional-fpga.html

http://www.plc2.com/assets/files/2015/04Embedded/ZYNQ_7000_SoC.pdf

https://www.plc2.com/en/fpga-training/course-overview/embedded/zynq-7000-soc-system-architecture.html

http://www.plc2.com/assets/files/2015/04Embedded/Comp_ZYNQ_US_HW_Design.pdf

http://www.plc2.com/assets/files/2015/03FPGA/Vivado_Tool_Flow.pdf

https://www.plc2.com/en/fpga-training/course-overview/fpga/vivado-design-suite-tool-flow.html

Germany - MunchenDate Location Facility Price TC Reg. URL

Advanced Vivado HLS (PLC2 version)12/10/2018 TBD Munchen DEU, Munchen - TBD PLC2


Compact ZYNQ UltraScale+ MPSoC for HW Designers (PLC2 version)12/12/2018 TBD Munchen DEU, Munchen - TBD PLC2


AXI Interface Technology (PLC2 version)12/13/2018 TBD Munchen DEU, Munchen - TBD PLC2


Classroom - Designing with Multi-Gigabit Serial I/O1/28/2019 TBD Munchen DEU, Munchen - TBD PLC2


Compact FPGA Schaltungstechnik (PLC2 course)1/21/2019 TBD Munchen DEU, Munchen - TBD PLC2


Classroom - Designing with Ethernet MAC Controllers1/30/2019 TBD Munchen DEU, Munchen - TBD PLC2


UltraScale Connectivity (PLC2 version)3/25/2019 TBD Munchen DEU, Munchen - TBD PLC2


Compact Verilog (PLC2 version)2/11/2019 TBD Munchen DEU, Munchen - TBD PLC2


DSP Design using System Generator (PLC2 version)2/11/2019 TBD Munchen DEU, Munchen - TBD PLC2


Expert DSP Design using System Generator (PLC2 version)2/11/2019 TBD Munchen DEU, Munchen - TBD PLC2


Compact ZYNQ-7000 SoC for SW Designers (PLC2 version)3/25/2019 TBD Munchen DEU, Munchen - TBD PLC2


Python (PLC2 course)3/25/2019 TBD Munchen DEU, Munchen - TBD PLC2


Compact UltraScale (PLC2 version)3/18/2019 TBD Munchen DEU, Munchen - TBD PLC2


http://www.plc2.com/assets/files/2015/03FPGA/Advanced_VIVADO_HLS%20.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/applikationen/advanced-vivado-hls.html

http://www.plc2.com/assets/files/2015/04Embedded/Comp_ZYNQ_US_HW_Design.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/embedded/compact-zynq-ultrascale-mpsoc-for-hw-designers.html

http://www.plc2.com/assets/files/2015/04Embedded/Consider_Cplusplus_Embed_Targ.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/embedded/axi-interface-technology.html

https://www.xilinx.com/training/courses/designing-multi-gigabit-serial-io.html

https://www.plc2.com/en/fpga-training/course-overview/connectivity/designing-with-multi-gigabit-serial-io.html

http://www.plc2.com/assets/files/2015/03FPGA/Compact_FPGA_Schalt.pdf


https://www.plc2.com/en/fpga-training/course-overview/connectivity/designing-with-ethernet-mac-controllers.html

http://www.plc2.com/assets/files/2015/06Connectivity/UltraScale_Connectivity.pdf

https://www.plc2.com/en/fpga-training/course-overview/connectivity/ultrascale-connectivity.html

http://www.plc2.com/assets/files/2015/03FPGA/Compact_Verilog.pdf

https://www.plc2.com/en/fpga-training/course-overview/fpga/compact-verilog.html

http://www.plc2.com/assets/files/2015/05DSP/DSP_Design_SysGen.pdf

https://www.plc2.com/en/fpga-training/course-overview/applikationen/dsp-design-using-system-generator.html

http://www.plc2.com/assets/files/2015/05DSP/Expert_DSP_Design.pdf

https://www.plc2.com/en/fpga-training/course-overview/applikationen/expert-dsp-design-using-system-generator.html

http://www.plc2.com/assets/files/2015/04Embedded/Compact_ZYNQ_7000_SW_Des.pdf

http://www.plc2.com/assets/files/2015/03FPGA/Python_for_Programmers.pdf

http://www.plc2.com/assets/files/2015/03FPGA/Compact_UltraScale.pdf

Germany - StuttgartDate Location Facility Price TC Reg. URL

DDR4 Interfacing with XILINX FPGAs (PLC2 version)12/10/2018 TBD Stuttgart DEU, Stuttgart - TBD PLC2


Designing a LogiCORE PCI Express System (PLC2 version)2/4/2019 TBD Stuttgart DEU, Stuttgart - TBD PLC2


Continuous Integration (PLC2 course)2/18/2019 TBD Stuttgart DEU, Stuttgart - TBD PLC2


Compact Advanced VHDL Testbenches and Verification /OSVVM (PLC2 course)3/6/2019 TBD Stuttgart DEU, Stuttgart - TBD PLC2


Classroom - Zynq UltraScale+ MPSoC for the System Architect3/6/2019 TBD Stuttgart DEU, Stuttgart - TBD PLC2


Compact FPGA Schaltungstechnik (PLC2 course)3/20/2019 TBD Stuttgart DEU, Stuttgart - TBD PLC2


Classroom - Embedded Design with PetaLinux Tools3/28/2019 TBD Stuttgart DEU, Stuttgart - TBD PLC2


Advanced Vivado HLS (PLC2 version)3/11/2019 TBD Stuttgart DEU, Stuttgart - TBD PLC2


AXI Interface Technology (PLC2 version)3/14/2019 TBD Stuttgart DEU, Stuttgart - TBD PLC2


Compact ZYNQ-7000 SoC for HW Designers (PLC2 version)3/13/2019 TBD Stuttgart DEU, Stuttgart - TBD PLC2


http://www.plc2.com/assets/files/2015/06Connectivity/DDR4_Interfacing_XILINX_FPGA.pdf

https://www.plc2.com/de/schulungen/kursuebersicht/connectivity/ddr4-interfacing-with-xilinx-fpgas.html


https://www.plc2.com/en/fpga-training/course-overview/connectivity/designing-with-pci-express.html

https://www.plc2.com/de/schulungen/kursuebersicht/fpga/continuous-integration.html

http://www.plc2.com/assets/files/2015/03FPGA/Compact_Adv_VHDL_OSVVM.pdf

https://www.plc2.com/en/fpga-training/course-overview/fpga/compact-osvvm.html


https://www.plc2.com/de/schulungen/kursuebersicht/embedded/zynq-ultrascale-mpsoc-system-architecture.html

http://www.plc2.com/assets/files/2015/03FPGA/Compact_FPGA_Schalt.pdf


http://www.plc2.com/assets/files/2015/03FPGA/Advanced_VIVADO_HLS%20.pdf

https://www.plc2.com/en/fpga-training/course-overview/applikationen/advanced-vivado-hls.html

http://www.plc2.com/assets/files/2015/04Embedded/Consider_Cplusplus_Embed_Targ.pdf

https://www.plc2.com/en/fpga-training/course-overview/embedded/axi-interface-technology.html

http://www.plc2.com/assets/files/2015/04Embedded/Compact_ZYNQ_7000_HW_Des.pdf

https://www.plc2.com/en/fpga-training/course-overview/embedded/compact-zynq-for-hw-designers.html

United States Maryland- ColumbiaDate Location Facility Price TC Reg. URL

Vivado Boot Camp Phase-2 (BLT version)1/15/2019 8830 Stanford Boulevard #100 Columbia USA, MD, Columbia -

University of PhoenixCampus


Designing with VHDL2/12/2019 8830 Stanford Boulevard #100 Columbia USA, MD, Columbia -






C-based design: High-Level Synthesis with Vivado HLx Tool3/4/2019 8830 Stanford Boulevard #100 Columbia USA, MD, Columbia -



Essential DSP Implementation Techniques for Xilinx FPGAs3/6/2019 8830 Stanford Boulevard #100 Columbia USA, MD, Columbia -



DSP Design Using System Generator3/7/2019 8830 Stanford Boulevard #100 Columbia USA, MD, Columbia -



Embedded Systems Hardware Design Boot Camp (BLT version)3/12/2019 8830 Stanford Boulevard #100 Columbia USA, MD, Columbia -









Designing with VHDL5/29/2019 8830 Stanford Boulevard #100 Columbia USA, MD, Columbia -



United States Indiana- FishersDate Location Facility Price TC Reg. URL

Classroom - Designing FPGAs Using the Vivado Design Suite 21/23/2019 11451 Overlook Fishers USA, IN, Fishers - VAI Logic


Classroom - Designing FPGAs Using the Vivado Design Suite 21/24/2019 11451 Overlook Fishers USA, IN, Fishers - VAI Logic


























South Korea - SeoulDate Location Facility Price TC Reg. URL

Designing FPGAs Using the Vivado Design Suite 212/10/2018 #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu

SeoulKOR, Seoul - Wedu Office 500 (USD) 6 Register

How to Design a High-Speed Memory Interface12/12/2018 #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu


Embedded Systems Design12/17/2018 #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu


Zynq UltraScale+ MPSoC for the System Architect12/19/2018 #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu


Classroom - Designing with Verilog1/2/2019 #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu


Classroom - Designing FPGAs Using the Vivado Design Suite 21/7/2019 #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu


Classroom - Designing with Ethernet MAC Controllers1/9/2019 #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu


Classroom - Zynq SoC System Architecture12/17/2018 #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu


Classroom - Embedded Design with PetaLinux Tools1/16/2019 #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu


Classroom - C-based design: High-Level Synthesis with Vivado HLx Tool1/21/2019 #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu



https://www.xilinx.com/training/courses/how-to-design-high-speed-memory-interface.html



https://www.xilinx.com/training/courses/designing-with-verilog.html






Japan - TokyoDate Location Facility Price TC Reg. URL

Essentials of FPGA Design12/13/2018 Art Village Osaki Central Tower 4F 1-2-2, Osaki,

Shinagawa-ku TokyoJPN, Tokyo - Xilinx JapanOffice


Embedded Systems Software Design12/19/2018 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Advanced Features and Techniques of Embedded Systems Software Design12/21/2018 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Essentials of FPGA Design (HDLab version)1/10/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - UltraFast Design Methodology1/16/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - Designing an Integrated PCI Express System1/17/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - Zynq SoC System Architecture1/22/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Debugging Techniques Using the Vivado Logic Analyzer (HDLab version)1/31/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,






Classroom - Xilinx Partial Reconfiguration Tools & Techniques2/13/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - C-based design: High-Level Synthesis with Vivado HLx Tool2/14/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Vivado Design Suite Tool Flow (HDLab version)2/20/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - Embedded Systems Design2/21/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - Advanced Features and Techniques of Embedded Systems Design2/26/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - Zynq SoC System Architecture3/5/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,






Debugging Techniques Using the Vivado Logic Analyzer (HDLab version)3/19/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - Embedded Systems Software Design3/27/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - Advanced Features and Techniques of Embedded Systems Software Design3/29/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - SDSoC Development Environment and Methodology2/12/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



Classroom - Advanced SDSoC Development Environment and Methodology2/13/2019 Art Village Osaki Central Tower 4F 1-2-2, Osaki,



https://www.xilinx.com/training/courses/essentials-fpga-design.html






http://info.hdlab.co.jp/training/xilinx/vivadess/




https://www.xilinx.com/training/courses/designing-integrated-pci-express.html




http://info.hdlab.co.jp/training/xilinx/vla/








http://info.hdlab.co.jp/training/xilinx/vtoolflow/




https://www.xilinx.com/training/courses/advanced-embedded-systems-design.html






http://info.hdlab.co.jp/training/xilinx/vla/










United States California- San JoseDate Location Facility Price TC Reg. URL

Developing with Embedded Linux (Doulos version)12/10/2018 2100 Logic Drive San Jose USA, CA, San Jose - Xilinx

Learning Center3100 (USD) 31 Register

UVM Adopter Class (Doulos course)12/10/2018 2100 Logic Drive San Jose USA, CA, San Jose - Xilinx

Learning Center3600 (USD) 36 Register

United States California- San DiegoDate Location Facility Price TC Reg. URL

Designing with Xilinx Serial Transceivers12/19/2018 10815 Rancho Bernado Rd San Diego USA, CA, San Diego - Xilinx

San Diego Office1600 (USD) 16 Register

Classroom - Designing FPGAs Using the Vivado Design Suite 112/17/2018 10815 Rancho Bernado Rd San Diego USA, CA, San Diego - Xilinx

San Diego Office1600 (USD) 16 Register

United States Virginia- SterlingDate Location Facility Price TC Reg. URL

Vivado Boot Camp Phase-2 (BLT version)1/15/2019 22685 Holiday Park Drive, Suite 60 Sterling USA, VA, Sterling - Executive

Conference & TrainingCenter


Designing with VHDL2/12/2019 22685 Holiday Park Drive, Suite 60 Sterling USA, VA, Sterling - Executive






C-based design: High-Level Synthesis with Vivado HLx Tool3/4/2019 22685 Holiday Park Drive, Suite 60 Sterling USA, VA, Sterling - Executive



Essential DSP Implementation Techniques for Xilinx FPGAs3/6/2019 22685 Holiday Park Drive, Suite 60 Sterling USA, VA, Sterling - Executive



Embedded Systems Hardware Design Boot Camp (BLT version)3/12/2019 22685 Holiday Park Drive, Suite 60 Sterling USA, VA, Sterling - Executive









Designing with VHDL5/29/2019 22685 Holiday Park Drive, Suite 60 Sterling USA, VA, Sterling - Executive



https://www.doulos.com/content/training/embedded_linux.php

https://www.doulos.com/content/training/embedded_linux.php

https://www.doulos.com/content/training/systemverilog_uvm_adopter.php

https://www.doulos.com/content/training/systemverilog_uvm_adopter.php

https://www.xilinx.com/training/courses/designing-with-xilinx-serial-transceivers.html

http://bit.ly/2N6HSRH


http://bit.ly/2BN48gO



















OnlineDate Location Facility Price TC Reg. URL

Zynq UltraScale+ MPSoC for the System Architect1/10/2019 Online 1600 (USD) 16 Register

Zynq-7000 All Programmable SoC System Architecture1/8/2019 Online 1600 (USD) 16 Register

Designing with System Verilog2/4/2019 Online 2400 (USD) 24 Register

Virtual - Zynq UltraScale+ MPSoC for the Software Developer2/7/2019 Online 1600 (USD) 16 Register

United States Minnesota- OronoDate Location Facility Price TC Reg. URL

Designing FPGAs Using the Vivado Design Suite 312/10/2018 2500 Shadywood Rd Orono USA, MN, Orono -- MAPS

Training Center1600 (USD) 16 Register

STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (MAPS)12/12/2018 2500 Shadywood Rd Orono USA, MN, Orono -- MAPS


Classroom - Zynq UltraScale+ MPSoC for the System Architect2/4/2019 2500 Shadywood Rd Orono USA, MN, Orono -- MAPS


Classroom - C-based design: High-Level Synthesis with Vivado HLx Tool2/7/2019 2500 Shadywood Rd Orono USA, MN, Orono -- MAPS


Classroom - Embedded Design with PetaLinux Tools12/27/2018 2500 Shadywood Rd Orono USA, MN, Orono -- MAPS


Canada British Columbia- CoquitlamDate Location Facility Price TC Reg. URL

Embedded System Design for the Zynq UltraScale+ MPSoC (combined course)2/25/2019 TBD Coquitlam CAN, BC, Coquitlam - TBD


Embedded Design with PetaLinux Tools2/28/2019 TBD Coquitlam CAN, BC, Coquitlam - TBD


Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology(combined course)3/12/2019 TBD Coquitlam CAN, BC, Coquitlam - TBD


C-based design: High-Level Synthesis with Vivado HLx Tool1/21/2019 TBD Coquitlam CAN, BC, Coquitlam - TBD


SDSoC Development Environment and Methodology1/23/2019 TBD Coquitlam CAN, BC, Coquitlam - TBD


Advanced SDSoC Development Environment and Methodology1/24/2019 TBD Coquitlam CAN, BC, Coquitlam - TBD


SystemVerilog for Verification1/14/2019 TBD Coquitlam CAN, BC, Coquitlam - TBD



https://www.fastertechnology.com/store/courses/embedded-systems-development/zynq-ultrascale-mpsoc-system-architect-onlin


https://www.fastertechnology.com/store/courses/embedded-systems-development/zynq-soc-system-architecture-jan-8-9-2019-on

https://www.xilinx.com/training/courses/designing-with-system-verilog.html

https://www.fastertechnology.com/store/courses/language-courses/introduction-to-verilog.html


https://www.fastertechnology.com/store/courses/embedded-systems-development/zynq-ultrascale-mpsoc-software-designer-5.ht


ttps://morgan-aps.com/training/register/?date=12-10-2018&class=FPGA-VDES3&loc=OronoMN

https://morgan-aps.com/trainingpdf/FPGA-STAXDCADV.pdf

https://morgan-aps.com/training/register/?date=12-14-2018&class=FPGA-STAXDCADV&loc=OronoMN


https://morgan-aps.com/training/register/?date=02-04-2019&class=EMBD-ZUPSA&loc=OronoMN


https://morgan-aps.com/training/register/?date=02-07-2019&class=DSP-HLS&loc=SchaumburgIL


https://morgan-aps.com/training/register/?date=12-27-2018&class=EMBD-PLNX&loc=OronoMN













United States Alabama- HuntsvilleDate Location Facility Price TC Reg. URL

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology(combined course)1/15/2019 TBD Huntsville USA, AL, Huntsville - TBD


SDSoC Development Environment and Methodology4/10/2019 TBD Huntsville USA, AL, Huntsville - TBD


Advanced SDSoC Development Environment and Methodology4/11/2019 TBD Huntsville USA, AL, Huntsville - TBD


C-based design: High-Level Synthesis with Vivado HLx Tool4/8/2019 TBD Huntsville USA, AL, Huntsville - TBD


Embedded System Design for the Zynq UltraScale+ MPSoC (combined course)2/18/2019 TBD Huntsville USA, AL, Huntsville - TBD


Embedded Design with PetaLinux Tools2/21/2019 TBD Huntsville USA, AL, Huntsville - TBD


Classroom - Designing with the Zynq UltraScale+ RFSoC4/24/2019 TBD Huntsville USA, AL, Huntsville - TBD


Canada Ontario- OttawaDate Location Facility Price TC Reg. URL

SystemVerilog for Verification2/25/2019 15 Fitzgerald Road Ottawa CAN, ONT, Ottawa -- Avnet


Developing AWS F1 Applications Using the SDAccel Environment Course - Classroom12/11/2018 15 Fitzgerald Road Ottawa CAN, ONT, Ottawa -- Avnet


Japan - Yokohama Shi, KanagawaDate Location Facility Price TC Reg. URL

Understand IP Management with Vivado Design Suite (HDLab version)12/18/2018 3-17-6 Shin-Yokohama Kohhoku-ku Yokohama Shi,

KanagawaJPN, Yokohama Shi,Kanagawa - HD Lab, Inc.


Vivado Design Suite For Large Design (HDLab version)12/19/2018 3-17-6 Shin-Yokohama Kohhoku-ku Yokohama Shi,

KanagawaJPN, Yokohama Shi,Kanagawa - HD Lab, Inc.


United States Wisconsin- MilwaukeeDate Location Facility Price TC Reg. URL

Designing FPGAs Using the Vivado Design Suite 12/7/2019 Milwaukee, WI Milwaukee USA, WI, Milwaukee - MAPS


United States Missouri- St. LouisDate Location Facility Price TC Reg. URL

Embedded Design with PetaLinux Tools12/10/2018 St. Louis St. Louis USA, MO, St. Louis - MAPS

Venue 21600 (USD) 16 Register
















http://info.hdlab.co.jp/training/xilinx/vivado_ip/


http://info.hdlab.co.jp/training/xilinx/largedesign/



https://morgan-aps.com/training/register/?date=02-07-2019&class=DSP-HLS&loc=MilwaukeeWI


https://morgan-aps.com/training/register/?date=12-10-2018&class=EMBD-PLNX&loc=SaintLouisMO

United States Iowa- Cedar RapidsDate Location Facility Price TC Reg. URL

C-based design: High-Level Synthesis with Vivado HLx Tool12/17/2018 Cedar Rapids, IA Cedar Rapids USA, IA, Cedar Rapids -

MAPS Venue1600 (USD) 16 Register

STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (MAPS)1/7/2019 Cedar Rapids, IA Cedar Rapids USA, IA, Cedar Rapids -


Zynq UltraScale+ MPSoC for the Software Developer1/10/2019 Cedar Rapids, IA Cedar Rapids USA, IA, Cedar Rapids -


United States Illinois- SchaumburgDate Location Facility Price TC Reg. URL

Zynq UltraScale+ MPSoC for the System Architect1/21/2019 475 N. Martingale Rd. Schaumburg USA, IL, Schaumburg - Xilinx


United States Kansas- OlatheDate Location Facility Price TC Reg. URL

Classroom - Designing with VHDL2/4/2019 Olathe, KS Olathe USA, KS, Olathe - MAPS


United States Kansas- WichitaDate Location Facility Price TC Reg. URL

Designing with the UltraScale and UltraScale+ Architectures1/17/2019 Wichita, KS Wichita USA, KS, Wichita - MAPS


United States Wisconsin- MadisonDate Location Facility Price TC Reg. URL

STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (MAPS)12/19/2018 Madison, WI Madison USA, WI, Madison - MAPS


Designing FPGAs Using the Vivado Design Suite 112/17/2018 Madison, WI Madison USA, WI, Madison - MAPS


United States NorthCarolina- RaleighDate Location Facility Price TC Reg. URL

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology(combined course)2/26/2019 TBD Raleigh USA, NC, Raleigh - TBD


Classroom - Designing with the Zynq UltraScale+ RFSoC4/11/2019 TBD Raleigh USA, NC, Raleigh - TBD


United States Utah- Salt Lake CityDate Location Facility Price TC Reg. URL

Designing with the Zynq UltraScale+ RFSoC3/25/2019 Salt Lake City USA, UT, Salt Lake City --

TBD Faster TechnologyVenue


Zynq UltraScale+ MPSoC for the System Architect2/13/2019 Salt Lake City USA, UT, Salt Lake City --

TBD Faster TechnologyVenue



https://morgan-aps.com/training/register/?date=12-17-2018&class=DSP-HLS&loc=CedarRapidsIA


https://morgan-aps.com/training/register/?date=01-07-2019&class=FPGA-STAXDCADV&loc=CedarRapidsIA


https://morgan-aps.com/training/register/?date=01-10-2019&class=EMBD-ZUPSW&loc=CedarRapidsIA


https://morgan-aps.com/training/register/?date=01-21-2019&class=EMBD-ZUPSA&loc=SchaumburgIL


https://morgan-aps.com/training/register/?date=02-06-2019&class=LANG-VHDL&loc=OlatheKS


https://morgan-aps.com/training/register/?date=01-17-2019&class=FPGA-US&loc=WichitaKS


https://morgan-aps.com/training/register/?date=12-19-2018&class=FPGA-STAXDCADV&loc=MadisonWI


https://morgan-aps.com/training/register/?date=12-17-2018&class=FPGA-VDES1&loc=MadisonWI





https://www.fastertechnology.com/store/courses/connectivity-courses/designing-with-the-zynq-ultrascale-rfsoc.html


https://www.fastertechnology.com/store/courses/embedded-systems-development/zynq-ultrascale-mpsoc-system-architect.html

United States Massachusetts- BurlingtonDate Location Facility Price TC Reg. URL

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology(combined course)1/28/2019 TBD Burlington USA, MA, Burlington -- TBD


Embedded System Design for the Zynq UltraScale+ MPSoC (combined course)3/11/2019 TBD Burlington USA, MA, Burlington -- TBD


C-based design: High-Level Synthesis with Vivado HLx Tool3/18/2019 TBD Burlington USA, MA, Burlington -- TBD


SDSoC Development Environment and Methodology3/20/2019 TBD Burlington USA, MA, Burlington -- TBD


Advanced SDSoC Development Environment and Methodology3/21/2019 TBD Burlington USA, MA, Burlington -- TBD


SystemVerilog for Verification2/11/2019 TBD Burlington USA, MA, Burlington -- TBD


Introduction to Universal Verification Methodology (UVM)3/18/2019 TBD Burlington USA, MA, Burlington -- TBD


Embedded Design with PetaLinux Tools3/14/2019 TBD Burlington USA, MA, Burlington -- TBD


Advanced Universal Verification Methodology (UVM) (Hardent version)2/19/2019 TBD Burlington USA, MA, Burlington -- TBD


Xilinx Partial Reconfiguration Tools & Techniques2/26/2019 TBD Burlington USA, MA, Burlington -- TBD


Classroom - Designing with the Zynq UltraScale+ RFSoC2/12/2019 TBD Burlington USA, MA, Burlington -- TBD


Training and/or services provided by Xilinx Authorized Training Providers are provided solely by the ATPs and not Xilinx.Training schedules are provided by each ATP and updated regularly; however, the schedules as displayed on these pages areas a courtesy to you and all times, dates, and locations should be verified directly with the applicable ATP.















https://www.hardent.com/course/advanced-universal-verification-methodology-uvm/

https://www.hardent.com/course/advanced-universal-verification-methodology-uvm/


https://www.hardent.com/course/xilinx-partial-reconfiguration-tools-and-techniques/



United States Texas- Richardson › XilinxClassReport › Location › ... · C-based design:...

Documents

Transcript of United States Texas- Richardson › XilinxClassReport › Location › ... · C-based design:...