UNIT-VII Advanced Micro Processors

8/14/2019 UNIT-VII Advanced Micro Processors

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UNIT-VII

Advanced Micro Processors


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Introduction to 80286

80286 16 bit p 16 Mbytes physical memory

Multi-user

Multitasking

OS

User protection

Virtual memory management


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80286 - Architecture

The bus unit BU

Performs all memory and i/o reads and writes, pre-fetches instructionbytes and controls transfer of data to and from processor extensiondevices such as the 80287 math coprocessor.

The instruction unit IU IU fully decodes up to three pre-fetched instructions and holds them in a

queue, where the execution unit can access them. Instructions in the pipeline

The execution unit EU Machine Status Word (MSW) register

The address unit AU AU computes the physical addresses that will be sent out to memory or

I/O by the BU. Real address mode protected virtual address mode CS, DS, SS, ES registers


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Register organization

Eight 16-bit GPRs

AX, BX, CX, DX, BP, SP, SI, DI

Four 16-bit segment regs.

DS, CS, SS, ES.

Status and control reg.

Flag reg.

Instruction pointer (IP)


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Signal description

COD/INTA: This output signal, in combination with M/IOsignal and S1 S0 distinguishes different memory, I/Oand INTR cycles.

BUSY and ERROR: BUSY=0 ; Processor suspend the execution and wait until it

becomes 1

An active ERROR signal causes the 80286 to perform theprocessor extension interrupt while executing the WAIT and ESCinstruction.

The active ERROR signal indicates to 80286 that the processorextension has committed a mistake and hence it is reactivating theprocessor extension interrupt.

CAP: A 0.047f, 12v capacitor must be connected between thisinput pin and ground to filter the output of the internal substrate biasgenerator. For correct operation of 80286 the capacitor must becharged to its operating voltage.


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Flag register

X NT IO PL O D I T S Z X Ac X P X Cy

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

O Overflow Flag TS Task switch

D Direction EM Emulate processor extension

I Interrupt Flag MP Monitor processor extension

T Trap Flag PE Protection enable

S Sign Flag NT Nested task flag

Z Zero Flag IO

Ac Auxiliary Carry Flag PL

P Parity Flag

Cy Carry Flag

X Not used

TS EM MP PE

I/O privilege level

Machine status word


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Interrupts of 80286

Divide error exception - 0

Single step interrupt - 1

NMI interrupt - 2

Break-point interrupt - 3

INTO detected overflow exception - 4

BOUND range exceeded exception 5Invalid opcode exception - 6

Processor extension not available - 7 (ESC or WAIT)

exception

Inter reserved, do not use - 8-15

Processor extension error interrupt - 16 (ESC or WAIT)

Inter reserved, do not use - 17-31

User Defined - 32-255


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Maskable Interrupt INTR

Non-maskable Interrupt NMI

Single Step Interrupt Interrupt Priorities

Order Interrupt

1 Instruction exception2 Single step

3 NMI

4 Processor extension segment overrun

5 INTR

6 INT instruction


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80286 Real Address Mode Operation

After the 80286 is reset, it starts executing in its real address

mode. MS-DOS systems operates in Real Address Mode

In this mode 80286 can address up to 1MB of physicalmemory.

Interrupt Vector Table of the 80286 is located in the first 1KBof memory. (from address 00000h to 003FFh ).

The addresses from FFFF0h to FFFFFh are reserved forsystem initialization.

Functions performed in this mode:

It initializes the IP and other registers of 80286 Initializes the peripheral

Enables interrupts

Sets up descriptor tables

Prepares for entering the protected virtual address mode.


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Protected Virtual Address Mode Operation (PVAM)

The 80286 is able to address 1Gbyte if virtual memory per task.

Swapping

Unswapping

Program is divides into Segments or pages

Segments or pages have been associated with a data structurecalled as a descriptor.

Descriptor contains segment base address, segment limit,

segment type,

privilege level,

segment availability in physical memory,

descriptor type and

segment use by another task.

Descriptor table.


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Descriptors and Their Types

Special types of descriptors which are used to carry out additional functionslike

Transfer of control Task switching

1. Data segment descriptors

2. System segment descriptors Store system data and execution state of a task for multitasking

system.

1. Gate descriptors The gate descriptors control the access to entry points of the code

to be executed.

1. Interrupt descriptors These are used to store task gates, interrupt gates and trap gates.

Segment descriptor cache registers: 6-Byte format

Local and Global descriptor table: LDTs & GDTs are 8K array.


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PRIVILEGE

The 80286 supports a four level hierarchical

privilege mechanism to control the access todescriptors to prevent

unwanted access to any of the code or data segments.

Unintentional interference in the higher privilege leveltasks.

(level 0 is the most privilege level while level 4 is theleast)

The privilege levels provide protection within atask.


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PROTECTION

The 80286 supports three basic mechanisms to provide

protection:1. Restricted use of segments (segment load check):

This is accomplished with the help of read/write privileges.

The segment usages are restricted by classifying the

corresponding descriptors under LDT and GDT.

1. Restricted Accesses to Segment (operation reference check):

This is accomplished using descriptor usages limitations and

the rules of privilege check

1. Privileged Instructions or Operations (privileged instruction

check):

These are to be executed or carried out at certain privilege

levels determined by current privilege level (CPL) and I/O

privilege level (IOPL) as defined by the flag register.


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Special Operations

Processor reset and initialization

The processor is reset by applying a high on RESET input thatterminates all execution and internal bus activities till RESET remainshigh.

Task switch operation

A no. of task allocation strategies like FCFS, STF, Time sharing, etc. In case of time sharing, the CPUs time is divided into equal duration

slices. The switch-over operation from one task to another is called as task

switch operation. This operation is carried out using a JMP or CALL to a new segment of

the new task.

Pointer testing instructions

The pointer testing instructions of 80286 use the memory managementhardware to verify whether the loaded selector value refers to a validsegment without generating any exception.


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Protected mode initialization

The initialization of protected mode is carried out in real mode bysetting the internal registers of 80286 suitably. To enter into protected mode, 80286 executes LMSW (load

MSW) instruction that set PE flag.

How to enter protected mode?

The execution of instruction LIDT (load interrupt descriptor tablebase) prepares the 80286 for protected virtual address mode.

Then the PE flag of MSW is set to enter the PVAM, using theLMSW instruction.

Halt

This instruction stops program execution and prevents the CPUfrom restarting, till it is interrupted or RESET is asserted.

If the CPU is interrupted in the HALT state, the execution startsfrom the next instruction after HLT.


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80286 BUS INTERFACE

The I/O devices are also addressed using even and oddaddress banks technique, using A0 and BHE.

The 80286 bus cycles are of six types Memory read

Memory write

I/O read

I/O write Interrupt acknowledge

Halt.

The 80286 bus at a particular instant may be in either of thesefour states:

1. Idle state (Ti)

2. Perform command state (Tc)

3. Send status state (Tc)4. Hold state (TH)


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80386 p

32-bit p

4 GB physical memory

16K - segment size

Page size 4KB

8 debug registers DR0-DR7 80386 has an on-chip address translation

80386DX 132 pins, 20MHz, 33MHz

80386SX 16-bit data bus

24-bit address bus


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Architecture of 80386


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1. Central Processing Unit (CPU) Execution Unit

1. 8 General Purpose Registers

2. 8 Special Purpose Registers

Instruction Unit1. 16-byte instruction code queue

2. 3-byte instruction decoded queue

3. The barrel shifter increases the speed of all shift and rotate operations

1. Memory Management Unit (MMU)

Segment Unit1. 4-GB size of segment

2. Segment and offset for relocability

3. SU provides a 4 level protection mechanism for protection and isolating thesystems code and data.

Page Unit1. Each segment is further divided into pages

2. 4KB- page size

3. Page Unit works under Segment Unit

4. It converts linear address into physical address

2. Bus Control Unit (BCU) Bus control unit had a prioritizer to resolve the priority of the various bus

requests.


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Signals

BE0# to BE3# :

80386 can be viewed as a 4-byte wide memory access mechanism. Theselines enable four banks (i.e. 1byte/2byte/3byte/4byte data transfer

simultaneously)

W/R : write/read control bit

D/C : data/control bit

M/IO : LOCK# :

ADS# : Address status indicates address bus and bus cycle definition

NA# : Next address allows address pipe lining

READY# :

BS16# : Bus size 16 allows the interfacing of 16-bit devices with the

32-bit wide 80386 data bus i.e. two bus cycles = 32 bit data.

HOLD :

HLDA :


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BUSY#: Co-processor is busy and main processor is in

waiting state.

ERROR# : Co-processor has encounter an error.

PEREQ : Processor extension request. i.e. CPU fetches a

data from co-processor.

INTR :

NMI :

RESET :

N/C : No connections pins are expected to be left open

while connecting the 80386 in the circuit.


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Register

organization


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FLAG Register

VM Flag : If this is set, 80386 enters the virtual 8086 mode within the

protected mode

RF-Resume flag : This is used with the debug register breakpoints, i.e. any

debug fault is ignored during the instruction cycle.


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Addressing Modes:

Eleven addressing modesScaled Indexed Mode

Based Scaled Indexed Mode.Based Scaled Indexed mode with Displacement

Data Types

Bit Bit field

Bit string Signed byte Unsigned byte Offset Pointer BCD Packed BCD Character Strings


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Descriptors tables

LDT

GDT

IDT, etc

Control registers

CR0,CR2,CR3 Load, store instructions are available to access theseregisters.


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Modes

1. RAM

1. After reset FFFF FFF0h under the RAM

2. Interrupt Vector table 0000 003FFh -- 1KB

2. PROTECED MODE

1. 4-GB --- PA

2. 64-TB --- virtual memory/task


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Real Addressing Mode physical address


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Physical Address formation in Protected mode

4


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Virtual 8086 mode


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PENTIUM PROCESSOR

The Pentium processor has 237 pins, arranged in a pin grid

array (PGA)

64 pins are data pins --- D0-D63

8 pins are parity --- DP0-DP7

Parity errors are indicated by these pins

Address bus (with parity check bit) --- A3-A31

BE0-BE7: are used to select the eight memory banks to

accomplish an 8-byte data transfer


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RISC Processors

RISC: Reduced Instruction Set Computer

CISC : complex instructions

Increase in processor die size

Consumes more power and silicon

Needs more cooling arrangement.

RISC: Small, highly optimized set of instructions

Every instruction is executed in a single clock after itis fetched and decoded.

Very fast execution

Less power consumption


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John Cocke of IBM research in New York, who had

first originated the RISC concept in 1974.

First time RISC is implemented in IBM 801 system

in John project

IBM RISC processors starting with R6000 series

were designed based on the concepts of IBM 801.

HYBRID ARCHITECTURE RISC AND CISC CONVERGENCE

Pentium and Athlon family of processors

SIMD : single Instruction Multiple Data


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The Advantages of RISC

RISC instructions, being simple, can be hard-

wired Processor can work at a high clock frequency

and thus yields higher speed.

On-chip MMU, Floating point arithmetic units. Chip cost is low

More devises can place on chip

Compilers produce more efficient codes inRISC p

Loading and decoding of instructions in a

RISC processor is simple and fast.


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Design issues of RISC processor

Register Windowing

Massive Pipelining

Single cycle instruction execution

SOME RISC PROCESSORS

1. MIPS

2. Sun Ultra SPARC

UNIT-VII Advanced Micro Processors

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